1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
28 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \
62 #define HAL_TCL1_RING_ID(ab)			((ab)->hw_params->regs->hal_tcl1_ring_id)  argument
63 #define HAL_TCL1_RING_MISC(ab) \  argument
64 	((ab)->hw_params->regs->hal_tcl1_ring_misc)
65 #define HAL_TCL1_RING_TP_ADDR_LSB(ab) \  argument
66 	((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_lsb)
67 #define HAL_TCL1_RING_TP_ADDR_MSB(ab) \  argument
68 	((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_msb)
69 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) \  argument
70 	((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix0)
71 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) \  argument
72 	((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix1)
73 #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) \  argument
74 	((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_lsb)
75 #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) \  argument
76 	((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_msb)
77 #define HAL_TCL1_RING_MSI1_DATA(ab) \  argument
78 	((ab)->hw_params->regs->hal_tcl1_ring_msi1_data)
80 #define HAL_TCL_RING_BASE_LSB(ab) \  argument
81 	((ab)->hw_params->regs->hal_tcl_ring_base_lsb)
83 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab)				\  argument
84 	(HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB)
85 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab)				\  argument
86 	(HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB)
87 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab)				\  argument
88 	(HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB)
90 	(HAL_TCL1_RING_BASE_MSB - HAL_TCL1_RING_BASE_LSB)
91 #define HAL_TCL1_RING_ID_OFFSET(ab)				\  argument
92 	(HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB)
93 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab)			\  argument
94 	(HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB)
95 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) \  argument
96 		(HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB)
97 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) \  argument
98 		(HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB)
99 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) \  argument
100 		(HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB)
101 #define HAL_TCL1_RING_MISC_OFFSET(ab) \  argument
102 		(HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB)
111 		(HAL_TCL1_RING_TP - HAL_TCL1_RING_HP)
114 #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \  argument
115 	((ab)->hw_params->regs->hal_tcl_status_ring_base_lsb)
123 #define HAL_WBM_PPE_RELEASE_RING_BASE_LSB(ab) \  argument
124 	((ab)->hw_params->regs->hal_ppe_rel_ring_base)
129 #define HAL_REO1_MISC_CTRL_ADDR(ab) \  argument
130 	((ab)->hw_params->regs->hal_reo1_misc_ctrl_addr)
135 #define HAL_REO1_SW_COOKIE_CFG0(ab)	((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg0)  argument
136 #define HAL_REO1_SW_COOKIE_CFG1(ab)	((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg1)  argument
137 #define HAL_REO1_QDESC_LUT_BASE0(ab)	((ab)->hw_params->regs->hal_reo1_qdesc_lut_base0)  argument
138 #define HAL_REO1_QDESC_LUT_BASE1(ab)	((ab)->hw_params->regs->hal_reo1_qdesc_lut_base1)  argument
139 #define HAL_REO1_RING_BASE_LSB(ab)	((ab)->hw_params->regs->hal_reo1_ring_base_lsb)  argument
140 #define HAL_REO1_RING_BASE_MSB(ab)	((ab)->hw_params->regs->hal_reo1_ring_base_msb)  argument
141 #define HAL_REO1_RING_ID(ab)		((ab)->hw_params->regs->hal_reo1_ring_id)  argument
142 #define HAL_REO1_RING_MISC(ab)		((ab)->hw_params->regs->hal_reo1_ring_misc)  argument
143 #define HAL_REO1_RING_HP_ADDR_LSB(ab)	((ab)->hw_params->regs->hal_reo1_ring_hp_addr_lsb)  argument
144 #define HAL_REO1_RING_HP_ADDR_MSB(ab)	((ab)->hw_params->regs->hal_reo1_ring_hp_addr_msb)  argument
145 #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) \  argument
146 	((ab)->hw_params->regs->hal_reo1_ring_producer_int_setup)
147 #define HAL_REO1_RING_MSI1_BASE_LSB(ab)	\  argument
148 	((ab)->hw_params->regs->hal_reo1_ring_msi1_base_lsb)
149 #define HAL_REO1_RING_MSI1_BASE_MSB(ab)	\  argument
150 	((ab)->hw_params->regs->hal_reo1_ring_msi1_base_msb)
151 #define HAL_REO1_RING_MSI1_DATA(ab)	((ab)->hw_params->regs->hal_reo1_ring_msi1_data)  argument
152 #define HAL_REO2_RING_BASE_LSB(ab)	((ab)->hw_params->regs->hal_reo2_ring_base)  argument
153 #define HAL_REO1_AGING_THRESH_IX_0(ab)	((ab)->hw_params->regs->hal_reo1_aging_thres_ix0)  argument
154 #define HAL_REO1_AGING_THRESH_IX_1(ab)	((ab)->hw_params->regs->hal_reo1_aging_thres_ix1)  argument
155 #define HAL_REO1_AGING_THRESH_IX_2(ab)	((ab)->hw_params->regs->hal_reo1_aging_thres_ix2)  argument
156 #define HAL_REO1_AGING_THRESH_IX_3(ab)	((ab)->hw_params->regs->hal_reo1_aging_thres_ix3)  argument
163 #define HAL_REO1_RING_TP_OFFSET			(HAL_REO1_RING_TP - HAL_REO1_RING_HP)
166 #define HAL_REO_SW0_RING_BASE_LSB(ab) \  argument
167 	((ab)->hw_params->regs->hal_reo2_sw0_ring_base)
173 #define HAL_REO_CMD_RING_BASE_LSB(ab) \  argument
174 	((ab)->hw_params->regs->hal_reo_cmd_ring_base)
180 #define	HAL_SW2REO_RING_BASE_LSB(ab) \  argument
181 	((ab)->hw_params->regs->hal_sw2reo_ring_base)
182 #define HAL_SW2REO1_RING_BASE_LSB(ab) \  argument
183 	((ab)->hw_params->regs->hal_sw2reo1_ring_base)
200 #define HAL_REO_STATUS_RING_BASE_LSB(ab) \  argument
201 	((ab)->hw_params->regs->hal_reo_status_ring_base)
205 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab) \  argument
206 	((ab)->hw_params->regs->hal_wbm_idle_ring_base_lsb)
207 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(ab) \  argument
208 	((ab)->hw_params->regs->hal_wbm_idle_ring_misc_addr)
209 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(ab) \  argument
210 	((ab)->hw_params->regs->hal_wbm_r0_idle_list_cntl_addr)
211 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(ab) \  argument
212 	((ab)->hw_params->regs->hal_wbm_r0_idle_list_size_addr)
213 #define HAL_WBM_SCATTERED_RING_BASE_LSB(ab) \  argument
214 	((ab)->hw_params->regs->hal_wbm_scattered_ring_base_lsb)
215 #define HAL_WBM_SCATTERED_RING_BASE_MSB(ab) \  argument
216 	((ab)->hw_params->regs->hal_wbm_scattered_ring_base_msb)
217 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(ab) \  argument
218 	((ab)->hw_params->regs->hal_wbm_scattered_desc_head_info_ix0)
219 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(ab) \  argument
220 	((ab)->hw_params->regs->hal_wbm_scattered_desc_head_info_ix1)
221 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(ab) \  argument
222 	((ab)->hw_params->regs->hal_wbm_scattered_desc_tail_info_ix0)
223 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(ab) \  argument
224 	((ab)->hw_params->regs->hal_wbm_scattered_desc_tail_info_ix1)
225 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(ab) \  argument
226 	((ab)->hw_params->regs->hal_wbm_scattered_desc_ptr_hp_addr)
232 #define HAL_WBM_SW_RELEASE_RING_BASE_LSB(ab) \  argument
233 	((ab)->hw_params->regs->hal_wbm_sw_release_ring_base_lsb)
234 #define HAL_WBM_SW1_RELEASE_RING_BASE_LSB(ab) \  argument
235 	((ab)->hw_params->regs->hal_wbm_sw1_release_ring_base_lsb)
242 #define HAL_WBM0_RELEASE_RING_BASE_LSB(ab) \  argument
243 	((ab)->hw_params->regs->hal_wbm0_release_ring_base_lsb)
245 #define HAL_WBM1_RELEASE_RING_BASE_LSB(ab) \  argument
246 	((ab)->hw_params->regs->hal_wbm1_release_ring_base_lsb)
501 #define HAL_SRNG_NUM_DMAC_RINGS (HAL_SRNG_RING_ID_DMAC_CMN_ID_END - \
503 #define HAL_SRNG_RINGS_PER_PMAC (HAL_SRNG_RING_ID_PMAC1_ID_END - \
649 	/* Interrupt timer threshold - in micro seconds */
652 	/* Interrupt batch counter threshold - in number of ring entries */
676 	 * TBD: See if this is required - register address can be derived
697 			/* Tail pointer location to be updated by SW - This
726 			/* Head pointer location to be updated by SW - This
732 			/* Low threshold - in number of ring entries */
741 /* Interrupt mitigation - Batch threshold in terms of number of frames */
746 /* Interrupt mitigation - timer threshold in us */
774  *	descriptor list, where the chip 0 WBM is chosen in case of a multi-chip config
776  *	descriptor list, where the chip 1 WBM is chosen in case of a multi-chip config
778  *	descriptor list, where the chip 2 WBM is chosen in case of a multi-chip config
780  * @HAL_RX_BUF_RBM_SW0_BM: For ring 0 -- returned to host
781  * @HAL_RX_BUF_RBM_SW1_BM: For ring 1 -- returned to host
782  * @HAL_RX_BUF_RBM_SW2_BM: For ring 2 -- returned to host
783  * @HAL_RX_BUF_RBM_SW3_BM: For ring 3 -- returned to host
784  * @HAL_RX_BUF_RBM_SW4_BM: For ring 4 -- returned to host
785  * @HAL_RX_BUF_RBM_SW5_BM: For ring 5 -- returned to host
786  * @HAL_RX_BUF_RBM_SW6_BM: For ring 6 -- returned to host
914 	u32 rx_bitmap[8]; /* Bitmap from 0-255 */
1073 	int (*create_srng_config)(struct ath12k_base *ab);
1089 void ath12k_hal_reo_init_cmd_ring(struct ath12k_base *ab,
1091 void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map);
1092 void ath12k_hal_setup_link_idle_list(struct ath12k_base *ab,
1097 dma_addr_t ath12k_hal_srng_get_tp_addr(struct ath12k_base *ab,
1099 dma_addr_t ath12k_hal_srng_get_hp_addr(struct ath12k_base *ab,
1108 int ath12k_hal_srng_get_entrysize(struct ath12k_base *ab, u32 ring_type);
1109 int ath12k_hal_srng_get_max_entries(struct ath12k_base *ab, u32 ring_type);
1110 void ath12k_hal_srng_get_params(struct ath12k_base *ab, struct hal_srng *srng,
1112 void *ath12k_hal_srng_dst_get_next_entry(struct ath12k_base *ab,
1114 void *ath12k_hal_srng_dst_peek(struct ath12k_base *ab, struct hal_srng *srng);
1115 int ath12k_hal_srng_dst_num_free(struct ath12k_base *ab, struct hal_srng *srng,
1117 void *ath12k_hal_srng_src_get_next_reaped(struct ath12k_base *ab,
1119 void *ath12k_hal_srng_src_reap_next(struct ath12k_base *ab,
1121 void *ath12k_hal_srng_src_get_next_entry(struct ath12k_base *ab,
1123 int ath12k_hal_srng_src_num_free(struct ath12k_base *ab, struct hal_srng *srng,
1125 void ath12k_hal_srng_access_begin(struct ath12k_base *ab,
1127 void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng);
1128 int ath12k_hal_srng_setup(struct ath12k_base *ab, enum hal_ring_type type,
1133 void ath12k_hal_dump_srng_stats(struct ath12k_base *ab);
1134 void ath12k_hal_srng_get_shadow_config(struct ath12k_base *ab,
1136 int ath12k_hal_srng_update_shadow_config(struct ath12k_base *ab,
1139 void ath12k_hal_srng_shadow_config(struct ath12k_base *ab);
1140 void ath12k_hal_srng_shadow_update_hp_tp(struct ath12k_base *ab,