Lines Matching refs:reg_start
531 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
532 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
537 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
538 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
541 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
542 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
547 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
548 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP; in ath12k_hal_srng_create_config_qcn9274()
551 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
552 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP; in ath12k_hal_srng_create_config_qcn9274()
555 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB; in ath12k_hal_srng_create_config_qcn9274()
556 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
561 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
562 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
565 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
566 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
569 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_BASE_LSB; in ath12k_hal_srng_create_config_qcn9274()
570 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
577 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_BASE_LSB; in ath12k_hal_srng_create_config_qcn9274()
578 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
585 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + in ath12k_hal_srng_create_config_qcn9274()
587 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_STATUS_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
594 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
595 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
598 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + in ath12k_hal_srng_create_config_qcn9274()
600 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
606 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
607 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
618 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_BASE_LSB; in ath12k_hal_srng_create_config_qcn9274()
619 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
622 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + in ath12k_hal_srng_create_config_qcn9274()
624 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_PPE_RELEASE_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
971 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
972 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
977 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
978 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
982 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
983 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
986 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
987 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP; in ath12k_hal_srng_create_config_wcn7850()
990 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
991 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP; in ath12k_hal_srng_create_config_wcn7850()
995 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB; in ath12k_hal_srng_create_config_wcn7850()
996 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1001 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1002 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1005 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1006 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1010 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_BASE_LSB; in ath12k_hal_srng_create_config_wcn7850()
1011 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1019 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_BASE_LSB; in ath12k_hal_srng_create_config_wcn7850()
1020 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1028 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + in ath12k_hal_srng_create_config_wcn7850()
1030 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_STATUS_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1037 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1038 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1042 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + in ath12k_hal_srng_create_config_wcn7850()
1044 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1047 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1048 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1243 srng_config->reg_start[HAL_SRNG_REG_GRP_R0] + in ath12k_hal_ce_dst_setup()
1933 srng->hwreg_base[i] = srng_config->reg_start[i] + in ath12k_hal_srng_setup()
2053 target_reg = srng_config->reg_start[HAL_HP_OFFSET_IN_REG_START]; in ath12k_hal_srng_update_shadow_config()