Lines Matching refs:u32

147 	u32 bdf_addr;
161 	u32 qmi_service_ins_id;
163 	u32 ce_count;
165 	u32 target_ce_count;
167 	u32 svc_to_ce_map_len;
198 	u32 num_vdevs;
199 	u32 num_peers;
201 	u32 hal_desc_sz;
225 		u32 start;
226 		u32 end;
230 	u32 tx_ring_size;
248 	u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);
259 	u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);
266 	u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);
267 	u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);
275 	u32 (*get_ring_selector)(struct sk_buff *skb);
352 	u32 hal_tcl1_ring_base_lsb;
353 	u32 hal_tcl1_ring_base_msb;
354 	u32 hal_tcl1_ring_id;
355 	u32 hal_tcl1_ring_misc;
356 	u32 hal_tcl1_ring_tp_addr_lsb;
357 	u32 hal_tcl1_ring_tp_addr_msb;
358 	u32 hal_tcl1_ring_consumer_int_setup_ix0;
359 	u32 hal_tcl1_ring_consumer_int_setup_ix1;
360 	u32 hal_tcl1_ring_msi1_base_lsb;
361 	u32 hal_tcl1_ring_msi1_base_msb;
362 	u32 hal_tcl1_ring_msi1_data;
363 	u32 hal_tcl2_ring_base_lsb;
364 	u32 hal_tcl_ring_base_lsb;
366 	u32 hal_tcl_status_ring_base_lsb;
368 	u32 hal_reo1_ring_base_lsb;
369 	u32 hal_reo1_ring_base_msb;
370 	u32 hal_reo1_ring_id;
371 	u32 hal_reo1_ring_misc;
372 	u32 hal_reo1_ring_hp_addr_lsb;
373 	u32 hal_reo1_ring_hp_addr_msb;
374 	u32 hal_reo1_ring_producer_int_setup;
375 	u32 hal_reo1_ring_msi1_base_lsb;
376 	u32 hal_reo1_ring_msi1_base_msb;
377 	u32 hal_reo1_ring_msi1_data;
378 	u32 hal_reo2_ring_base_lsb;
379 	u32 hal_reo1_aging_thresh_ix_0;
380 	u32 hal_reo1_aging_thresh_ix_1;
381 	u32 hal_reo1_aging_thresh_ix_2;
382 	u32 hal_reo1_aging_thresh_ix_3;
384 	u32 hal_reo1_ring_hp;
385 	u32 hal_reo1_ring_tp;
386 	u32 hal_reo2_ring_hp;
388 	u32 hal_reo_tcl_ring_base_lsb;
389 	u32 hal_reo_tcl_ring_hp;
391 	u32 hal_reo_status_ring_base_lsb;
392 	u32 hal_reo_status_hp;
394 	u32 hal_reo_cmd_ring_base_lsb;
395 	u32 hal_reo_cmd_ring_hp;
397 	u32 hal_sw2reo_ring_base_lsb;
398 	u32 hal_sw2reo_ring_hp;
400 	u32 hal_seq_wcss_umac_ce0_src_reg;
401 	u32 hal_seq_wcss_umac_ce0_dst_reg;
402 	u32 hal_seq_wcss_umac_ce1_src_reg;
403 	u32 hal_seq_wcss_umac_ce1_dst_reg;
405 	u32 hal_wbm_idle_link_ring_base_lsb;
406 	u32 hal_wbm_idle_link_ring_misc;
408 	u32 hal_wbm_release_ring_base_lsb;
410 	u32 hal_wbm0_release_ring_base_lsb;
411 	u32 hal_wbm1_release_ring_base_lsb;
413 	u32 pcie_qserdes_sysclk_en_sel;
414 	u32 pcie_pcs_osc_dtct_config_base;
416 	u32 hal_shadow_base_addr;
417 	u32 hal_reo1_misc_ctl;