Lines Matching +full:0 +full:x11d
10 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
12 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
51 HAL_MACTX_CBF_START = 0 /* 0x0 */,
52 HAL_PHYRX_DATA = 1 /* 0x1 */,
53 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */,
54 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */,
55 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */,
56 HAL_MACTX_DATA_RESP = 5 /* 0x5 */,
57 HAL_MACTX_CBF_DATA = 6 /* 0x6 */,
58 HAL_MACTX_CBF_DONE = 7 /* 0x7 */,
59 HAL_MACRX_CBF_READ_REQUEST = 8 /* 0x8 */,
60 HAL_MACRX_CBF_DATA_REQUEST = 9 /* 0x9 */,
61 HAL_MACRX_EXPECT_NDP_RECEPTION = 10 /* 0xa */,
62 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 11 /* 0xb */,
63 HAL_MACRX_NDP_TIMEOUT = 12 /* 0xc */,
64 HAL_MACRX_ABORT_ACK = 13 /* 0xd */,
65 HAL_MACRX_REQ_IMPLICIT_FB = 14 /* 0xe */,
66 HAL_MACRX_CHAIN_MASK = 15 /* 0xf */,
67 HAL_MACRX_NAP_USER = 16 /* 0x10 */,
68 HAL_MACRX_ABORT_REQUEST = 17 /* 0x11 */,
69 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 18 /* 0x12 */,
70 HAL_PHYTX_ABORT_ACK = 19 /* 0x13 */,
71 HAL_PHYTX_ABORT_REQUEST = 20 /* 0x14 */,
72 HAL_PHYTX_PKT_END = 21 /* 0x15 */,
73 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 22 /* 0x16 */,
74 HAL_PHYTX_REQUEST_CTRL_INFO = 23 /* 0x17 */,
75 HAL_PHYTX_DATA_REQUEST = 24 /* 0x18 */,
76 HAL_PHYTX_BF_CV_LOADING_DONE = 25 /* 0x19 */,
77 HAL_PHYTX_NAP_ACK = 26 /* 0x1a */,
78 HAL_PHYTX_NAP_DONE = 27 /* 0x1b */,
79 HAL_PHYTX_OFF_ACK = 28 /* 0x1c */,
80 HAL_PHYTX_ON_ACK = 29 /* 0x1d */,
81 HAL_PHYTX_SYNTH_OFF_ACK = 30 /* 0x1e */,
82 HAL_PHYTX_DEBUG16 = 31 /* 0x1f */,
83 HAL_MACTX_ABORT_REQUEST = 32 /* 0x20 */,
84 HAL_MACTX_ABORT_ACK = 33 /* 0x21 */,
85 HAL_MACTX_PKT_END = 34 /* 0x22 */,
86 HAL_MACTX_PRE_PHY_DESC = 35 /* 0x23 */,
87 HAL_MACTX_BF_PARAMS_COMMON = 36 /* 0x24 */,
88 HAL_MACTX_BF_PARAMS_PER_USER = 37 /* 0x25 */,
89 HAL_MACTX_PREFETCH_CV = 38 /* 0x26 */,
90 HAL_MACTX_USER_DESC_COMMON = 39 /* 0x27 */,
91 HAL_MACTX_USER_DESC_PER_USER = 40 /* 0x28 */,
92 HAL_EXAMPLE_USER_TLV_16 = 41 /* 0x29 */,
93 HAL_EXAMPLE_TLV_16 = 42 /* 0x2a */,
94 HAL_MACTX_PHY_OFF = 43 /* 0x2b */,
95 HAL_MACTX_PHY_ON = 44 /* 0x2c */,
96 HAL_MACTX_SYNTH_OFF = 45 /* 0x2d */,
97 HAL_MACTX_EXPECT_CBF_COMMON = 46 /* 0x2e */,
98 HAL_MACTX_EXPECT_CBF_PER_USER = 47 /* 0x2f */,
99 HAL_MACTX_PHY_DESC = 48 /* 0x30 */,
100 HAL_MACTX_L_SIG_A = 49 /* 0x31 */,
101 HAL_MACTX_L_SIG_B = 50 /* 0x32 */,
102 HAL_MACTX_HT_SIG = 51 /* 0x33 */,
103 HAL_MACTX_VHT_SIG_A = 52 /* 0x34 */,
104 HAL_MACTX_VHT_SIG_B_SU20 = 53 /* 0x35 */,
105 HAL_MACTX_VHT_SIG_B_SU40 = 54 /* 0x36 */,
106 HAL_MACTX_VHT_SIG_B_SU80 = 55 /* 0x37 */,
107 HAL_MACTX_VHT_SIG_B_SU160 = 56 /* 0x38 */,
108 HAL_MACTX_VHT_SIG_B_MU20 = 57 /* 0x39 */,
109 HAL_MACTX_VHT_SIG_B_MU40 = 58 /* 0x3a */,
110 HAL_MACTX_VHT_SIG_B_MU80 = 59 /* 0x3b */,
111 HAL_MACTX_VHT_SIG_B_MU160 = 60 /* 0x3c */,
112 HAL_MACTX_SERVICE = 61 /* 0x3d */,
113 HAL_MACTX_HE_SIG_A_SU = 62 /* 0x3e */,
114 HAL_MACTX_HE_SIG_A_MU_DL = 63 /* 0x3f */,
115 HAL_MACTX_HE_SIG_A_MU_UL = 64 /* 0x40 */,
116 HAL_MACTX_HE_SIG_B1_MU = 65 /* 0x41 */,
117 HAL_MACTX_HE_SIG_B2_MU = 66 /* 0x42 */,
118 HAL_MACTX_HE_SIG_B2_OFDMA = 67 /* 0x43 */,
119 HAL_MACTX_DELETE_CV = 68 /* 0x44 */,
120 HAL_MACTX_MU_UPLINK_COMMON = 69 /* 0x45 */,
121 HAL_MACTX_MU_UPLINK_USER_SETUP = 70 /* 0x46 */,
122 HAL_MACTX_OTHER_TRANSMIT_INFO = 71 /* 0x47 */,
123 HAL_MACTX_PHY_NAP = 72 /* 0x48 */,
124 HAL_MACTX_DEBUG = 73 /* 0x49 */,
125 HAL_PHYRX_ABORT_ACK = 74 /* 0x4a */,
126 HAL_PHYRX_GENERATED_CBF_DETAILS = 75 /* 0x4b */,
127 HAL_PHYRX_RSSI_LEGACY = 76 /* 0x4c */,
128 HAL_PHYRX_RSSI_HT = 77 /* 0x4d */,
129 HAL_PHYRX_USER_INFO = 78 /* 0x4e */,
130 HAL_PHYRX_PKT_END = 79 /* 0x4f */,
131 HAL_PHYRX_DEBUG = 80 /* 0x50 */,
132 HAL_PHYRX_CBF_TRANSFER_DONE = 81 /* 0x51 */,
133 HAL_PHYRX_CBF_TRANSFER_ABORT = 82 /* 0x52 */,
134 HAL_PHYRX_L_SIG_A = 83 /* 0x53 */,
135 HAL_PHYRX_L_SIG_B = 84 /* 0x54 */,
136 HAL_PHYRX_HT_SIG = 85 /* 0x55 */,
137 HAL_PHYRX_VHT_SIG_A = 86 /* 0x56 */,
138 HAL_PHYRX_VHT_SIG_B_SU20 = 87 /* 0x57 */,
139 HAL_PHYRX_VHT_SIG_B_SU40 = 88 /* 0x58 */,
140 HAL_PHYRX_VHT_SIG_B_SU80 = 89 /* 0x59 */,
141 HAL_PHYRX_VHT_SIG_B_SU160 = 90 /* 0x5a */,
142 HAL_PHYRX_VHT_SIG_B_MU20 = 91 /* 0x5b */,
143 HAL_PHYRX_VHT_SIG_B_MU40 = 92 /* 0x5c */,
144 HAL_PHYRX_VHT_SIG_B_MU80 = 93 /* 0x5d */,
145 HAL_PHYRX_VHT_SIG_B_MU160 = 94 /* 0x5e */,
146 HAL_PHYRX_HE_SIG_A_SU = 95 /* 0x5f */,
147 HAL_PHYRX_HE_SIG_A_MU_DL = 96 /* 0x60 */,
148 HAL_PHYRX_HE_SIG_A_MU_UL = 97 /* 0x61 */,
149 HAL_PHYRX_HE_SIG_B1_MU = 98 /* 0x62 */,
150 HAL_PHYRX_HE_SIG_B2_MU = 99 /* 0x63 */,
151 HAL_PHYRX_HE_SIG_B2_OFDMA = 100 /* 0x64 */,
152 HAL_PHYRX_OTHER_RECEIVE_INFO = 101 /* 0x65 */,
153 HAL_PHYRX_COMMON_USER_INFO = 102 /* 0x66 */,
154 HAL_PHYRX_DATA_DONE = 103 /* 0x67 */,
155 HAL_RECEIVE_RSSI_INFO = 104 /* 0x68 */,
156 HAL_RECEIVE_USER_INFO = 105 /* 0x69 */,
157 HAL_MIMO_CONTROL_INFO = 106 /* 0x6a */,
158 HAL_RX_LOCATION_INFO = 107 /* 0x6b */,
159 HAL_COEX_TX_REQ = 108 /* 0x6c */,
160 HAL_DUMMY = 109 /* 0x6d */,
161 HAL_RX_TIMING_OFFSET_INFO = 110 /* 0x6e */,
162 HAL_EXAMPLE_TLV_32_NAME = 111 /* 0x6f */,
163 HAL_MPDU_LIMIT = 112 /* 0x70 */,
164 HAL_NA_LENGTH_END = 113 /* 0x71 */,
165 HAL_OLE_BUF_STATUS = 114 /* 0x72 */,
166 HAL_PCU_PPDU_SETUP_DONE = 115 /* 0x73 */,
167 HAL_PCU_PPDU_SETUP_END = 116 /* 0x74 */,
168 HAL_PCU_PPDU_SETUP_INIT = 117 /* 0x75 */,
169 HAL_PCU_PPDU_SETUP_START = 118 /* 0x76 */,
170 HAL_PDG_FES_SETUP = 119 /* 0x77 */,
171 HAL_PDG_RESPONSE = 120 /* 0x78 */,
172 HAL_PDG_TX_REQ = 121 /* 0x79 */,
173 HAL_SCH_WAIT_INSTR = 122 /* 0x7a */,
174 HAL_SCHEDULER_TLV = 123 /* 0x7b */,
175 HAL_TQM_FLOW_EMPTY_STATUS = 124 /* 0x7c */,
176 HAL_TQM_FLOW_NOT_EMPTY_STATUS = 125 /* 0x7d */,
177 HAL_TQM_GEN_MPDU_LENGTH_LIST = 126 /* 0x7e */,
178 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 127 /* 0x7f */,
179 HAL_TQM_GEN_MPDUS = 128 /* 0x80 */,
180 HAL_TQM_GEN_MPDUS_STATUS = 129 /* 0x81 */,
181 HAL_TQM_REMOVE_MPDU = 130 /* 0x82 */,
182 HAL_TQM_REMOVE_MPDU_STATUS = 131 /* 0x83 */,
183 HAL_TQM_REMOVE_MSDU = 132 /* 0x84 */,
184 HAL_TQM_REMOVE_MSDU_STATUS = 133 /* 0x85 */,
185 HAL_TQM_UPDATE_TX_MPDU_COUNT = 134 /* 0x86 */,
186 HAL_TQM_WRITE_CMD = 135 /* 0x87 */,
187 HAL_OFDMA_TRIGGER_DETAILS = 136 /* 0x88 */,
188 HAL_TX_DATA = 137 /* 0x89 */,
189 HAL_TX_FES_SETUP = 138 /* 0x8a */,
190 HAL_RX_PACKET = 139 /* 0x8b */,
191 HAL_EXPECTED_RESPONSE = 140 /* 0x8c */,
192 HAL_TX_MPDU_END = 141 /* 0x8d */,
193 HAL_TX_MPDU_START = 142 /* 0x8e */,
194 HAL_TX_MSDU_END = 143 /* 0x8f */,
195 HAL_TX_MSDU_START = 144 /* 0x90 */,
196 HAL_TX_SW_MODE_SETUP = 145 /* 0x91 */,
197 HAL_TXPCU_BUFFER_STATUS = 146 /* 0x92 */,
198 HAL_TXPCU_USER_BUFFER_STATUS = 147 /* 0x93 */,
199 HAL_DATA_TO_TIME_CONFIG = 148 /* 0x94 */,
200 HAL_EXAMPLE_USER_TLV_32 = 149 /* 0x95 */,
201 HAL_MPDU_INFO = 150 /* 0x96 */,
202 HAL_PDG_USER_SETUP = 151 /* 0x97 */,
203 HAL_TX_11AH_SETUP = 152 /* 0x98 */,
204 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 153 /* 0x99 */,
205 HAL_TX_PEER_ENTRY = 154 /* 0x9a */,
206 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 155 /* 0x9b */,
207 HAL_EXAMPLE_STRUCT_NAME = 156 /* 0x9c */,
208 HAL_PCU_PPDU_SETUP_END_INFO = 157 /* 0x9d */,
209 HAL_PPDU_RATE_SETTING = 158 /* 0x9e */,
210 HAL_PROT_RATE_SETTING = 159 /* 0x9f */,
211 HAL_RX_MPDU_DETAILS = 160 /* 0xa0 */,
212 HAL_EXAMPLE_USER_TLV_42 = 161 /* 0xa1 */,
213 HAL_RX_MSDU_LINK = 162 /* 0xa2 */,
214 HAL_RX_REO_QUEUE = 163 /* 0xa3 */,
215 HAL_ADDR_SEARCH_ENTRY = 164 /* 0xa4 */,
216 HAL_SCHEDULER_CMD = 165 /* 0xa5 */,
217 HAL_TX_FLUSH = 166 /* 0xa6 */,
218 HAL_TQM_ENTRANCE_RING = 167 /* 0xa7 */,
219 HAL_TX_DATA_WORD = 168 /* 0xa8 */,
220 HAL_TX_MPDU_DETAILS = 169 /* 0xa9 */,
221 HAL_TX_MPDU_LINK = 170 /* 0xaa */,
222 HAL_TX_MPDU_LINK_PTR = 171 /* 0xab */,
223 HAL_TX_MPDU_QUEUE_HEAD = 172 /* 0xac */,
224 HAL_TX_MPDU_QUEUE_EXT = 173 /* 0xad */,
225 HAL_TX_MPDU_QUEUE_EXT_PTR = 174 /* 0xae */,
226 HAL_TX_MSDU_DETAILS = 175 /* 0xaf */,
227 HAL_TX_MSDU_EXTENSION = 176 /* 0xb0 */,
228 HAL_TX_MSDU_FLOW = 177 /* 0xb1 */,
229 HAL_TX_MSDU_LINK = 178 /* 0xb2 */,
230 HAL_TX_MSDU_LINK_ENTRY_PTR = 179 /* 0xb3 */,
231 HAL_RESPONSE_RATE_SETTING = 180 /* 0xb4 */,
232 HAL_TXPCU_BUFFER_BASICS = 181 /* 0xb5 */,
233 HAL_UNIFORM_DESCRIPTOR_HEADER = 182 /* 0xb6 */,
234 HAL_UNIFORM_TQM_CMD_HEADER = 183 /* 0xb7 */,
235 HAL_UNIFORM_TQM_STATUS_HEADER = 184 /* 0xb8 */,
236 HAL_USER_RATE_SETTING = 185 /* 0xb9 */,
237 HAL_WBM_BUFFER_RING = 186 /* 0xba */,
238 HAL_WBM_LINK_DESCRIPTOR_RING = 187 /* 0xbb */,
239 HAL_WBM_RELEASE_RING = 188 /* 0xbc */,
240 HAL_TX_FLUSH_REQ = 189 /* 0xbd */,
241 HAL_RX_MSDU_DETAILS = 190 /* 0xbe */,
242 HAL_TQM_WRITE_CMD_STATUS = 191 /* 0xbf */,
243 HAL_TQM_GET_MPDU_QUEUE_STATS = 192 /* 0xc0 */,
244 HAL_TQM_GET_MSDU_FLOW_STATS = 193 /* 0xc1 */,
245 HAL_EXAMPLE_USER_CTLV_32 = 194 /* 0xc2 */,
246 HAL_TX_FES_STATUS_START = 195 /* 0xc3 */,
247 HAL_TX_FES_STATUS_USER_PPDU = 196 /* 0xc4 */,
248 HAL_TX_FES_STATUS_USER_RESPONSE = 197 /* 0xc5 */,
249 HAL_TX_FES_STATUS_END = 198 /* 0xc6 */,
250 HAL_RX_TRIG_INFO = 199 /* 0xc7 */,
251 HAL_RXPCU_TX_SETUP_CLEAR = 200 /* 0xc8 */,
252 HAL_RX_FRAME_BITMAP_REQ = 201 /* 0xc9 */,
253 HAL_RX_FRAME_BITMAP_ACK = 202 /* 0xca */,
254 HAL_COEX_RX_STATUS = 203 /* 0xcb */,
255 HAL_RX_START_PARAM = 204 /* 0xcc */,
256 HAL_RX_PPDU_START = 205 /* 0xcd */,
257 HAL_RX_PPDU_END = 206 /* 0xce */,
258 HAL_RX_MPDU_START = 207 /* 0xcf */,
259 HAL_RX_MPDU_END = 208 /* 0xd0 */,
260 HAL_RX_MSDU_START = 209 /* 0xd1 */,
261 HAL_RX_MSDU_END = 210 /* 0xd2 */,
262 HAL_RX_ATTENTION = 211 /* 0xd3 */,
263 HAL_RECEIVED_RESPONSE_INFO = 212 /* 0xd4 */,
264 HAL_RX_PHY_SLEEP = 213 /* 0xd5 */,
265 HAL_RX_HEADER = 214 /* 0xd6 */,
266 HAL_RX_PEER_ENTRY = 215 /* 0xd7 */,
267 HAL_RX_FLUSH = 216 /* 0xd8 */,
268 HAL_RX_RESPONSE_REQUIRED_INFO = 217 /* 0xd9 */,
269 HAL_RX_FRAMELESS_BAR_DETAILS = 218 /* 0xda */,
270 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 219 /* 0xdb */,
271 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 220 /* 0xdc */,
272 HAL_TX_CBF_INFO = 221 /* 0xdd */,
273 HAL_PCU_PPDU_SETUP_USER = 222 /* 0xde */,
274 HAL_RX_MPDU_PCU_START = 223 /* 0xdf */,
275 HAL_RX_PM_INFO = 224 /* 0xe0 */,
276 HAL_RX_USER_PPDU_END = 225 /* 0xe1 */,
277 HAL_RX_PRE_PPDU_START = 226 /* 0xe2 */,
278 HAL_RX_PREAMBLE = 227 /* 0xe3 */,
279 HAL_TX_FES_SETUP_COMPLETE = 228 /* 0xe4 */,
280 HAL_TX_LAST_MPDU_FETCHED = 229 /* 0xe5 */,
281 HAL_TXDMA_STOP_REQUEST = 230 /* 0xe6 */,
282 HAL_RXPCU_SETUP = 231 /* 0xe7 */,
283 HAL_RXPCU_USER_SETUP = 232 /* 0xe8 */,
284 HAL_TX_FES_STATUS_ACK_OR_BA = 233 /* 0xe9 */,
285 HAL_TQM_ACKED_MPDU = 234 /* 0xea */,
286 HAL_COEX_TX_RESP = 235 /* 0xeb */,
287 HAL_COEX_TX_STATUS = 236 /* 0xec */,
288 HAL_MACTX_COEX_PHY_CTRL = 237 /* 0xed */,
289 HAL_COEX_STATUS_BROADCAST = 238 /* 0xee */,
290 HAL_RESPONSE_START_STATUS = 239 /* 0xef */,
291 HAL_RESPONSE_END_STATUS = 240 /* 0xf0 */,
292 HAL_CRYPTO_STATUS = 241 /* 0xf1 */,
293 HAL_RECEIVED_TRIGGER_INFO = 242 /* 0xf2 */,
294 HAL_REO_ENTRANCE_RING = 243 /* 0xf3 */,
295 HAL_RX_MPDU_LINK = 244 /* 0xf4 */,
296 HAL_COEX_TX_STOP_CTRL = 245 /* 0xf5 */,
297 HAL_RX_PPDU_ACK_REPORT = 246 /* 0xf6 */,
298 HAL_RX_PPDU_NO_ACK_REPORT = 247 /* 0xf7 */,
299 HAL_SCH_COEX_STATUS = 248 /* 0xf8 */,
300 HAL_SCHEDULER_COMMAND_STATUS = 249 /* 0xf9 */,
301 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 250 /* 0xfa */,
302 HAL_TX_FES_STATUS_PROT = 251 /* 0xfb */,
303 HAL_TX_FES_STATUS_START_PPDU = 252 /* 0xfc */,
304 HAL_TX_FES_STATUS_START_PROT = 253 /* 0xfd */,
305 HAL_TXPCU_PHYTX_DEBUG32 = 254 /* 0xfe */,
306 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 255 /* 0xff */,
307 HAL_TX_MPDU_COUNT_TRANSFER_END = 256 /* 0x100 */,
308 HAL_WHO_ANCHOR_OFFSET = 257 /* 0x101 */,
309 HAL_WHO_ANCHOR_VALUE = 258 /* 0x102 */,
310 HAL_WHO_CCE_INFO = 259 /* 0x103 */,
311 HAL_WHO_COMMIT = 260 /* 0x104 */,
312 HAL_WHO_COMMIT_DONE = 261 /* 0x105 */,
313 HAL_WHO_FLUSH = 262 /* 0x106 */,
314 HAL_WHO_L2_LLC = 263 /* 0x107 */,
315 HAL_WHO_L2_PAYLOAD = 264 /* 0x108 */,
316 HAL_WHO_L3_CHECKSUM = 265 /* 0x109 */,
317 HAL_WHO_L3_INFO = 266 /* 0x10a */,
318 HAL_WHO_L4_CHECKSUM = 267 /* 0x10b */,
319 HAL_WHO_L4_INFO = 268 /* 0x10c */,
320 HAL_WHO_MSDU = 269 /* 0x10d */,
321 HAL_WHO_MSDU_MISC = 270 /* 0x10e */,
322 HAL_WHO_PACKET_DATA = 271 /* 0x10f */,
323 HAL_WHO_PACKET_HDR = 272 /* 0x110 */,
324 HAL_WHO_PPDU_END = 273 /* 0x111 */,
325 HAL_WHO_PPDU_START = 274 /* 0x112 */,
326 HAL_WHO_TSO = 275 /* 0x113 */,
327 HAL_WHO_WMAC_HEADER_PV0 = 276 /* 0x114 */,
328 HAL_WHO_WMAC_HEADER_PV1 = 277 /* 0x115 */,
329 HAL_WHO_WMAC_IV = 278 /* 0x116 */,
330 HAL_MPDU_INFO_END = 279 /* 0x117 */,
331 HAL_MPDU_INFO_BITMAP = 280 /* 0x118 */,
332 HAL_TX_QUEUE_EXTENSION = 281 /* 0x119 */,
333 HAL_RX_PEER_ENTRY_DETAILS = 282 /* 0x11a */,
334 HAL_RX_REO_QUEUE_REFERENCE = 283 /* 0x11b */,
335 HAL_RX_REO_QUEUE_EXT = 284 /* 0x11c */,
336 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 285 /* 0x11d */,
337 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 286 /* 0x11e */,
338 HAL_TQM_ACKED_MPDU_STATUS = 287 /* 0x11f */,
339 HAL_TQM_ADD_MSDU_STATUS = 288 /* 0x120 */,
340 HAL_RX_MPDU_LINK_PTR = 289 /* 0x121 */,
341 HAL_REO_DESTINATION_RING = 290 /* 0x122 */,
342 HAL_TQM_LIST_GEN_DONE = 291 /* 0x123 */,
343 HAL_WHO_TERMINATE = 292 /* 0x124 */,
344 HAL_TX_LAST_MPDU_END = 293 /* 0x125 */,
345 HAL_TX_CV_DATA = 294 /* 0x126 */,
346 HAL_TCL_ENTRANCE_FROM_PPE_RING = 295 /* 0x127 */,
347 HAL_PPDU_TX_END = 296 /* 0x128 */,
348 HAL_PROT_TX_END = 297 /* 0x129 */,
349 HAL_PDG_RESPONSE_RATE_SETTING = 298 /* 0x12a */,
350 HAL_MPDU_INFO_GLOBAL_END = 299 /* 0x12b */,
351 HAL_TQM_SCH_INSTR_GLOBAL_END = 300 /* 0x12c */,
352 HAL_RX_PPDU_END_USER_STATS = 301 /* 0x12d */,
353 HAL_RX_PPDU_END_USER_STATS_EXT = 302 /* 0x12e */,
354 HAL_NO_ACK_REPORT = 303 /* 0x12f */,
355 HAL_ACK_REPORT = 304 /* 0x130 */,
356 HAL_UNIFORM_REO_CMD_HEADER = 305 /* 0x131 */,
357 HAL_REO_GET_QUEUE_STATS = 306 /* 0x132 */,
358 HAL_REO_FLUSH_QUEUE = 307 /* 0x133 */,
359 HAL_REO_FLUSH_CACHE = 308 /* 0x134 */,
360 HAL_REO_UNBLOCK_CACHE = 309 /* 0x135 */,
361 HAL_UNIFORM_REO_STATUS_HEADER = 310 /* 0x136 */,
362 HAL_REO_GET_QUEUE_STATS_STATUS = 311 /* 0x137 */,
363 HAL_REO_FLUSH_QUEUE_STATUS = 312 /* 0x138 */,
364 HAL_REO_FLUSH_CACHE_STATUS = 313 /* 0x139 */,
365 HAL_REO_UNBLOCK_CACHE_STATUS = 314 /* 0x13a */,
366 HAL_TQM_FLUSH_CACHE = 315 /* 0x13b */,
367 HAL_TQM_UNBLOCK_CACHE = 316 /* 0x13c */,
368 HAL_TQM_FLUSH_CACHE_STATUS = 317 /* 0x13d */,
369 HAL_TQM_UNBLOCK_CACHE_STATUS = 318 /* 0x13e */,
370 HAL_RX_PPDU_END_STATUS_DONE = 319 /* 0x13f */,
371 HAL_RX_STATUS_BUFFER_DONE = 320 /* 0x140 */,
372 HAL_BUFFER_ADDR_INFO = 321 /* 0x141 */,
373 HAL_RX_MSDU_DESC_INFO = 322 /* 0x142 */,
374 HAL_RX_MPDU_DESC_INFO = 323 /* 0x143 */,
375 HAL_TCL_DATA_CMD = 324 /* 0x144 */,
376 HAL_TCL_GSE_CMD = 325 /* 0x145 */,
377 HAL_TCL_EXIT_BASE = 326 /* 0x146 */,
378 HAL_TCL_COMPACT_EXIT_RING = 327 /* 0x147 */,
379 HAL_TCL_REGULAR_EXIT_RING = 328 /* 0x148 */,
380 HAL_TCL_EXTENDED_EXIT_RING = 329 /* 0x149 */,
381 HAL_UPLINK_COMMON_INFO = 330 /* 0x14a */,
382 HAL_UPLINK_USER_SETUP_INFO = 331 /* 0x14b */,
383 HAL_TX_DATA_SYNC = 332 /* 0x14c */,
384 HAL_PHYRX_CBF_READ_REQUEST_ACK = 333 /* 0x14d */,
385 HAL_TCL_STATUS_RING = 334 /* 0x14e */,
386 HAL_TQM_GET_MPDU_HEAD_INFO = 335 /* 0x14f */,
387 HAL_TQM_SYNC_CMD = 336 /* 0x150 */,
388 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 337 /* 0x151 */,
389 HAL_TQM_SYNC_CMD_STATUS = 338 /* 0x152 */,
390 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 339 /* 0x153 */,
391 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 340 /* 0x154 */,
392 HAL_REO_FLUSH_TIMEOUT_LIST = 341 /* 0x155 */,
393 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 342 /* 0x156 */,
394 HAL_REO_TO_PPE_RING = 343 /* 0x157 */,
395 HAL_RX_MPDU_INFO = 344 /* 0x158 */,
396 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 345 /* 0x159 */,
397 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 346 /* 0x15a */,
398 HAL_EXAMPLE_USER_TLV_32_NAME = 347 /* 0x15b */,
399 HAL_RX_PPDU_START_USER_INFO = 348 /* 0x15c */,
400 HAL_RX_RXPCU_CLASSIFICATION_OVERVIEW = 349 /* 0x15d */,
401 HAL_RX_RING_MASK = 350 /* 0x15e */,
402 HAL_WHO_CLASSIFY_INFO = 351 /* 0x15f */,
403 HAL_TXPT_CLASSIFY_INFO = 352 /* 0x160 */,
404 HAL_RXPT_CLASSIFY_INFO = 353 /* 0x161 */,
405 HAL_TX_FLOW_SEARCH_ENTRY = 354 /* 0x162 */,
406 HAL_RX_FLOW_SEARCH_ENTRY = 355 /* 0x163 */,
407 HAL_RECEIVED_TRIGGER_INFO_DETAILS = 356 /* 0x164 */,
408 HAL_COEX_MAC_NAP = 357 /* 0x165 */,
409 HAL_MACRX_ABORT_REQUEST_INFO = 358 /* 0x166 */,
410 HAL_MACTX_ABORT_REQUEST_INFO = 359 /* 0x167 */,
411 HAL_PHYRX_ABORT_REQUEST_INFO = 360 /* 0x168 */,
412 HAL_PHYTX_ABORT_REQUEST_INFO = 361 /* 0x169 */,
413 HAL_RXPCU_PPDU_END_INFO = 362 /* 0x16a */,
414 HAL_WHO_MESH_CONTROL = 363 /* 0x16b */,
415 HAL_L_SIG_A_INFO = 364 /* 0x16c */,
416 HAL_L_SIG_B_INFO = 365 /* 0x16d */,
417 HAL_HT_SIG_INFO = 366 /* 0x16e */,
418 HAL_VHT_SIG_A_INFO = 367 /* 0x16f */,
419 HAL_VHT_SIG_B_SU20_INFO = 368 /* 0x170 */,
420 HAL_VHT_SIG_B_SU40_INFO = 369 /* 0x171 */,
421 HAL_VHT_SIG_B_SU80_INFO = 370 /* 0x172 */,
422 HAL_VHT_SIG_B_SU160_INFO = 371 /* 0x173 */,
423 HAL_VHT_SIG_B_MU20_INFO = 372 /* 0x174 */,
424 HAL_VHT_SIG_B_MU40_INFO = 373 /* 0x175 */,
425 HAL_VHT_SIG_B_MU80_INFO = 374 /* 0x176 */,
426 HAL_VHT_SIG_B_MU160_INFO = 375 /* 0x177 */,
427 HAL_SERVICE_INFO = 376 /* 0x178 */,
428 HAL_HE_SIG_A_SU_INFO = 377 /* 0x179 */,
429 HAL_HE_SIG_A_MU_DL_INFO = 378 /* 0x17a */,
430 HAL_HE_SIG_A_MU_UL_INFO = 379 /* 0x17b */,
431 HAL_HE_SIG_B1_MU_INFO = 380 /* 0x17c */,
432 HAL_HE_SIG_B2_MU_INFO = 381 /* 0x17d */,
433 HAL_HE_SIG_B2_OFDMA_INFO = 382 /* 0x17e */,
434 HAL_PDG_SW_MODE_BW_START = 383 /* 0x17f */,
435 HAL_PDG_SW_MODE_BW_END = 384 /* 0x180 */,
436 HAL_PDG_WAIT_FOR_MAC_REQUEST = 385 /* 0x181 */,
437 HAL_PDG_WAIT_FOR_PHY_REQUEST = 386 /* 0x182 */,
438 HAL_SCHEDULER_END = 387 /* 0x183 */,
439 HAL_PEER_TABLE_ENTRY = 388 /* 0x184 */,
440 HAL_SW_PEER_INFO = 389 /* 0x185 */,
441 HAL_RXOLE_CCE_CLASSIFY_INFO = 390 /* 0x186 */,
442 HAL_TCL_CCE_CLASSIFY_INFO = 391 /* 0x187 */,
443 HAL_RXOLE_CCE_INFO = 392 /* 0x188 */,
444 HAL_TCL_CCE_INFO = 393 /* 0x189 */,
445 HAL_TCL_CCE_SUPERRULE = 394 /* 0x18a */,
446 HAL_CCE_RULE = 395 /* 0x18b */,
447 HAL_RX_PPDU_START_DROPPED = 396 /* 0x18c */,
448 HAL_RX_PPDU_END_DROPPED = 397 /* 0x18d */,
449 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 398 /* 0x18e */,
450 HAL_RX_MPDU_START_DROPPED = 399 /* 0x18f */,
451 HAL_RX_MSDU_START_DROPPED = 400 /* 0x190 */,
452 HAL_RX_MSDU_END_DROPPED = 401 /* 0x191 */,
453 HAL_RX_MPDU_END_DROPPED = 402 /* 0x192 */,
454 HAL_RX_ATTENTION_DROPPED = 403 /* 0x193 */,
455 HAL_TXPCU_USER_SETUP = 404 /* 0x194 */,
456 HAL_RXPCU_USER_SETUP_EXT = 405 /* 0x195 */,
457 HAL_CE_SRC_DESC = 406 /* 0x196 */,
458 HAL_CE_STAT_DESC = 407 /* 0x197 */,
459 HAL_RXOLE_CCE_SUPERRULE = 408 /* 0x198 */,
460 HAL_TX_RATE_STATS_INFO = 409 /* 0x199 */,
461 HAL_CMD_PART_0_END = 410 /* 0x19a */,
462 HAL_MACTX_SYNTH_ON = 411 /* 0x19b */,
463 HAL_SCH_CRITICAL_TLV_REFERENCE = 412 /* 0x19c */,
464 HAL_TQM_MPDU_GLOBAL_START = 413 /* 0x19d */,
465 HAL_EXAMPLE_TLV_32 = 414 /* 0x19e */,
466 HAL_TQM_UPDATE_TX_MSDU_FLOW = 415 /* 0x19f */,
467 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 416 /* 0x1a0 */,
468 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 417 /* 0x1a1 */,
469 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 418 /* 0x1a2 */,
470 HAL_REO_UPDATE_RX_REO_QUEUE = 419 /* 0x1a3 */,
471 HAL_CE_DST_DESC = 420 /* 0x1a4 */,
472 HAL_TLV_BASE = 511 /* 0x1ff */,
486 #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0)
500 #define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0)
573 #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU BIT(0)
600 * 'Msdu_continuation' set to 0. This implies that when an msdu
678 #define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
684 #define HAL_REO_DEST_RING_INFO1_REORDER_INFO_VALID BIT(0)
760 * 0 - Idle ring
786 #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
791 #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0)
854 * 0 - Idle ring
862 #define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0)
869 #define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0)
881 #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0)
888 #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
929 #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0)
940 #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0)
955 #define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(0)
965 #define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0)
974 #define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0)
981 #define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0)
1067 * 0 - Normal search, 1 - Index based address search,
1147 * 0 refers to the IDLE ring
1156 * At initialization time, this value is set to 0. On the
1159 * count value continues with 0 again.
1208 #define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0)
1238 * 0: FSE select 1: ASE select
1256 #define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0)
1261 #define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0)
1285 * 0: FSE select 1: ASE select
1299 #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
1306 #define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0)
1334 * each dword read (4 bytes), the byte 0 is swapped with byte 3
1341 * For each dword write (4 bytes), the byte 0 is swapped with
1371 * 0 refers to the IDLE ring
1380 * At initialization time, this value is set to 0. On the
1383 * count value continues with 0 again.
1396 #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
1420 * 0 refers to the IDLE ring
1429 * At initialization time, this value is set to 0. On the
1432 * count value continues with 0 again.
1451 #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0)
1502 * 0 refers to the IDLE ring
1511 * At initialization time, this value is set to 0. On the
1514 * count value continues with 0 again.
1527 #define HAL_TX_RATE_STATS_INFO0_VALID BIT(0)
1631 * set to value 0, which represents the 'NULL' pointer. When all MSDU
1636 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1647 #define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)
1650 #define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)
1658 #define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0)
1779 * not fetched and hence sw_peer_id and tid = 0
1781 * buffer_or_desc_type = e_num 0
1786 * hence sw_peer_id and tid = 0
1788 * buffer_or_desc_type = e_num 0
1813 * At initialization time, this value is set to 0. On the
1816 * count value continues with 0 again.
1890 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0)
1907 #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0)
1941 #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0)
1943 #define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0)
1960 #define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0)
1967 #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0)
1974 #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0)
1977 #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0)
2039 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA
2040 * session, with window size of 0). The 3 values here are the main values
2043 * A BA window size of 0 (=> one frame entry bitmat), means that there is
2069 #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
2094 #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0)
2110 #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0)
2127 #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0)
2143 #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0)
2170 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0)
2173 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0)
2180 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0)
2183 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0)
2280 #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0)
2282 #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0)
2302 * 0 - No error has been detected while executing this command
2311 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0)
2337 * 0 - No error has been detected while executing this command
2343 * 0 - No blocking related errors found
2351 * 0 - miss; 1 - hit
2359 * In REO, this is always 0
2364 * 0 - No error found
2378 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0)
2397 * 0 - No error has been detected while executing this command
2403 * 0 - Unblock a blocking resource
2411 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0)
2414 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0)
2434 * 0 - No error has been detected while executing this command
2454 #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0)
2455 #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0)
2456 #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0)
2457 #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0)
2458 #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0)