Lines Matching +full:3 +full:- +full:ring
1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
21 #define HAL_MAX_AVAIL_BLK_RES 3
28 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \
35 #define HAL_SHADOW_BASE_ADDR(ab) ab->hw_params.regs->hal_shadow_base_addr
47 (ab->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg)
49 (ab->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg)
51 (ab->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg)
53 (ab->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg)
59 /* SW2TCL(x) R0 ring configuration address */
62 #define HAL_TCL1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_lsb
63 #define HAL_TCL1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_msb
64 #define HAL_TCL1_RING_ID(ab) ab->hw_params.regs->hal_tcl1_ring_id
65 #define HAL_TCL1_RING_MISC(ab) ab->hw_params.regs->hal_tcl1_ring_misc
67 ab->hw_params.regs->hal_tcl1_ring_tp_addr_lsb
69 ab->hw_params.regs->hal_tcl1_ring_tp_addr_msb
71 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0
73 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1
75 ab->hw_params.regs->hal_tcl1_ring_msi1_base_lsb
77 ab->hw_params.regs->hal_tcl1_ring_msi1_base_msb
79 ab->hw_params.regs->hal_tcl1_ring_msi1_data
80 #define HAL_TCL2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl2_ring_base_lsb
81 #define HAL_TCL_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl_ring_base_lsb
84 (HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
86 (HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
88 (HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB(ab))
90 (HAL_TCL1_RING_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
92 (HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB(ab))
94 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB(ab))
96 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB(ab))
98 (HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
100 (HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
102 (HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB(ab))
104 /* SW2TCL(x) R2 ring pointers (head/tail) address */
111 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP)
113 /* TCL STATUS ring address */
115 ab->hw_params.regs->hal_tcl_status_ring_base_lsb
118 /* REO2SW(x) R0 ring configuration address */
124 #define HAL_REO1_MISC_CTL(ab) ab->hw_params.regs->hal_reo1_misc_ctl
125 #define HAL_REO1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo1_ring_base_lsb
126 #define HAL_REO1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_reo1_ring_base_msb
127 #define HAL_REO1_RING_ID(ab) ab->hw_params.regs->hal_reo1_ring_id
128 #define HAL_REO1_RING_MISC(ab) ab->hw_params.regs->hal_reo1_ring_misc
130 ab->hw_params.regs->hal_reo1_ring_hp_addr_lsb
132 ab->hw_params.regs->hal_reo1_ring_hp_addr_msb
134 ab->hw_params.regs->hal_reo1_ring_producer_int_setup
136 ab->hw_params.regs->hal_reo1_ring_msi1_base_lsb
138 ab->hw_params.regs->hal_reo1_ring_msi1_base_msb
140 ab->hw_params.regs->hal_reo1_ring_msi1_data
141 #define HAL_REO2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo2_ring_base_lsb
143 ab->hw_params.regs->hal_reo1_aging_thresh_ix_0
145 ab->hw_params.regs->hal_reo1_aging_thresh_ix_1
147 ab->hw_params.regs->hal_reo1_aging_thresh_ix_2
149 ab->hw_params.regs->hal_reo1_aging_thresh_ix_3
152 (HAL_REO1_RING_MSI1_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
154 (HAL_REO1_RING_MSI1_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
156 (HAL_REO1_RING_MSI1_DATA(ab) - HAL_REO1_RING_BASE_LSB(ab))
158 (HAL_REO1_RING_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
159 #define HAL_REO1_RING_ID_OFFSET(ab) (HAL_REO1_RING_ID(ab) - HAL_REO1_RING_BASE_LSB(ab))
161 (HAL_REO1_RING_PRODUCER_INT_SETUP(ab) - HAL_REO1_RING_BASE_LSB(ab))
163 (HAL_REO1_RING_HP_ADDR_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
165 (HAL_REO1_RING_HP_ADDR_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
167 (HAL_REO1_RING_MISC(ab) - HAL_REO1_RING_BASE_LSB(ab))
169 /* REO2SW(x) R2 ring pointers (head/tail) address */
170 #define HAL_REO1_RING_HP(ab) ab->hw_params.regs->hal_reo1_ring_hp
171 #define HAL_REO1_RING_TP(ab) ab->hw_params.regs->hal_reo1_ring_tp
172 #define HAL_REO2_RING_HP(ab) ab->hw_params.regs->hal_reo2_ring_hp
174 #define HAL_REO1_RING_TP_OFFSET(ab) (HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab))
176 /* REO2TCL R0 ring configuration address */
178 ab->hw_params.regs->hal_reo_tcl_ring_base_lsb
180 /* REO2TCL R2 ring pointer (head/tail) address */
181 #define HAL_REO_TCL_RING_HP(ab) ab->hw_params.regs->hal_reo_tcl_ring_hp
185 ab->hw_params.regs->hal_reo_cmd_ring_base_lsb
188 #define HAL_REO_CMD_HP(ab) ab->hw_params.regs->hal_reo_cmd_ring_hp
192 ab->hw_params.regs->hal_sw2reo_ring_base_lsb
195 #define HAL_SW2REO_RING_HP(ab) ab->hw_params.regs->hal_sw2reo_ring_hp
197 /* CE ring R0 address */
202 /* CE ring R2 address */
208 ab->hw_params.regs->hal_reo_status_ring_base_lsb
209 #define HAL_REO_STATUS_HP(ab) ab->hw_params.regs->hal_reo_status_hp
213 (ab->hw_params.regs->hal_wbm_idle_link_ring_base_lsb)
215 (ab->hw_params.regs->hal_wbm_idle_link_ring_misc)
231 (ab->hw_params.regs->hal_wbm_release_ring_base_lsb)
238 (ab->hw_params.regs->hal_wbm0_release_ring_base_lsb)
240 (ab->hw_params.regs->hal_wbm1_release_ring_base_lsb)
246 /* TCL ring field mask and offset */
251 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3)
263 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3)
271 /* REO ring field mask and offset */
276 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3)
286 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3)
289 /* CE ring bit field mask and shift */
296 /* WBM ring bit field mask and shift */
419 #define HAL_SRNG_NUM_LMACS 3
421 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \
470 HAL_REO_CMD_UNBLOCK_CACHE = 3,
489 HAL_REO_CMD_RESOURCE_BLOCKED = 3,
531 /* Common SRNG ring structure for source and destination rings */
533 /* Unique SRNG ring ID */
536 /* Ring initialization done */
539 /* Interrupt/MSI value assigned to this ring */
542 /* Physical base address of the ring */
545 /* Virtual base address of the ring */
548 /* Number of entries in ring */
551 /* Ring size */
554 /* Ring size mask */
557 /* Size of ring entry */
560 /* Interrupt timer threshold - in micro seconds */
563 /* Interrupt batch counter threshold - in number of ring entries */
575 /* Lock for serializing ring index updates */
578 /* Start offset of SRNG register groups for this ring
579 * TBD: See if this is required - register address can be derived
580 * from ring ID
586 /* Source or Destination ring */
600 /* Tail pointer location to be updated by SW - This
629 /* Head pointer location to be updated by SW - This
635 /* Low threshold - in number of ring entries */
644 /* Interrupt mitigation - Batch threshold in terms of number of frames */
649 /* Interrupt mitigation - timer threshold in us */
673 * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host
674 * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host
675 * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host
676 * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host
695 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3)
784 #define HAL_HASH_ROUTING_RING_SW3 3
802 u32 rx_bitmap[8]; /* Bitmap from 0-255 */
900 /* Shared memory for ring pointer updates from host to FW */