Lines Matching +full:0 +full:x000fc000
13 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
57 * 0. The PPDU start status will only be valid when this bit
66 * address 1 bit 0 is set indicating mcast/bcast and the BSSID
227 * ring 0. Field is filled in by the RX_DMA.
243 HTT_RX_MPDU_ENCRYPT_WEP40 = 0,
256 #define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff
257 #define RX_MPDU_START_INFO0_PEER_IDX_LSB 0
258 #define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000
260 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000
268 #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000
318 * 0: WEP40
329 * Bits [31:0] of the PN number extracted from the IV field
330 * WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] is
333 * WEPSeed[1], pn1}. Only pn[47:0] is valid.
334 * AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1,
335 * pn0}. Only pn[47:0] is valid.
336 * WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11,
339 * pn[47:0] are valid.
361 #define RX_MPDU_END_INFO0_RESERVED_0_MASK 0x00001fff
362 #define RX_MPDU_END_INFO0_RESERVED_0_LSB 0
363 #define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000
415 #define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK 0x00003fff
416 #define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB 0
417 #define RX_MSDU_START_INFO0_IP_OFFSET_MASK 0x000fc000
419 #define RX_MSDU_START_INFO0_RING_MASK_MASK 0x00f00000
421 #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000
424 #define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK 0x000000ff
425 #define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB 0
426 #define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK 0x00000300
428 #define RX_MSDU_START_INFO1_SA_IDX_MASK 0x07ff0000
437 #define RX_MSDU_START_INFO2_DA_IDX_MASK 0x000007ff
438 #define RX_MSDU_START_INFO2_DA_IDX_LSB 0
439 #define RX_MSDU_START_INFO2_IP_PROTO_FIELD_MASK 0x00ff0000
447 * - 0 bytes for no security
457 RX_MSDU_DECAP_RAW = 0,
519 * Only valid if tcp_prot or udp_prot is set. The value 0
527 * IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0,
528 * protocol[7:0]}.
529 * IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0,
530 * next_header[7:0]}
531 * UDP case: sort_port[15:0], dest_port[15:0]
532 * TCP case: sort_port[15:0], dest_port[15:0],
533 * {header_length[3:0], 6'b0, flags[5:0], window_size[15:0]},
534 * {16'b0, urgent_ptr[15:0]}, all options except 32-bit
544 * 0: RAW: No decapsulation
570 * the TCP payload is 0.
580 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff
581 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB 0
597 #define RX_MSDU_END_INFO1_TCP_FLAG_MASK 0x000001ff
598 #define RX_MSDU_END_INFO1_TCP_FLAG_LSB 0
599 #define RX_MSDU_END_INFO1_L3_HDR_PAD_MASK 0x00001c00
601 #define RX_MSDU_END_INFO1_WINDOW_SIZE_MASK 0xffff0000
605 #define RX_MSDU_END_INFO2_DA_OFFSET_MASK 0x0000003f
606 #define RX_MSDU_END_INFO2_DA_OFFSET_LSB 0
607 #define RX_MSDU_END_INFO2_SA_OFFSET_MASK 0x00000fc0
609 #define RX_MSDU_END_INFO2_TYPE_OFFSET_MASK 0x0003f000
666 * WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start
689 * have both first_mpdu and last_mpdu bits set to 0.
712 #define HTT_RX_PPDU_START_PREAMBLE_LEGACY 0x04
713 #define HTT_RX_PPDU_START_PREAMBLE_HT 0x08
714 #define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF 0x09
715 #define HTT_RX_PPDU_START_PREAMBLE_VHT 0x0C
716 #define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D
718 #define RX_PPDU_START_INFO0_IS_GREENFIELD BIT(0)
720 #define RX_PPDU_START_INFO1_L_SIG_RATE_MASK 0x0000000f
721 #define RX_PPDU_START_INFO1_L_SIG_RATE_LSB 0
722 #define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK 0x0001ffe0
724 #define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK 0x00fc0000
726 #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000
731 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff
732 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB 0
734 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff
735 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB 0
738 #define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff
739 #define RX_PPDU_START_INFO4_VHT_SIG_B_LSB 0
741 #define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff
742 #define RX_PPDU_START_INFO5_SERVICE_LSB 0
766 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
767 * Value of 0x80 indicates invalid.
770 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
771 * Value of 0x80 indicates invalid.
774 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
775 * Value of 0x80 indicates invalid.
778 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
779 * Value of 0x80 indicates invalid.
783 * Value of 0x80 indicates invalid.
787 * Value of 0x80 indicates invalid.
791 * Value of 0x80 indicates invalid.
795 * Value of 0x80 indicates invalid.
799 * Value of 0x80 indicates invalid.
803 * Value of 0x80 indicates invalid.
807 * Value of 0x80 indicates invalid.
811 * Value of 0x80 indicates invalid.
815 * Value of 0x80 indicates invalid.
819 * Value of 0x80 indicates invalid.
823 * Value of 0x80 indicates invalid.
827 * Value of 0x80 indicates invalid.
831 * bandwidths. Value of 0x80 indicates invalid.
834 * Reserved: HW should fill with 0, FW should ignore.
840 * Reserved: HW should fill with 0, FW should ignore.
843 * If l_sig_rate_select is 0:
844 * 0x8: OFDM 48 Mbps
845 * 0x9: OFDM 24 Mbps
846 * 0xA: OFDM 12 Mbps
847 * 0xB: OFDM 6 Mbps
848 * 0xC: OFDM 54 Mbps
849 * 0xD: OFDM 36 Mbps
850 * 0xE: OFDM 18 Mbps
851 * 0xF: OFDM 9 Mbps
853 * 0x8: CCK 11 Mbps long preamble
854 * 0x9: CCK 5.5 Mbps long preamble
855 * 0xA: CCK 2 Mbps long preamble
856 * 0xB: CCK 1 Mbps long preamble
857 * 0xC: CCK 11 Mbps short preamble
858 * 0xD: CCK 5.5 Mbps short preamble
859 * 0xE: CCK 2 Mbps short preamble
876 * 0x4: Legacy (OFDM/CCK)
877 * 0x8: HT
878 * 0x9: HT with TxBF
879 * 0xC: VHT
880 * 0xD: VHT with TxBF
881 * 0x80 - 0xFF: Reserved for special baseband data types such
885 * If preamble_type == 0x8 or 0x9
887 * If preamble_type == 0xC or 0xD
893 * Reserved: HW should fill with 0, FW should ignore.
896 * If preamble_type == 0x8 or 0x9
898 * If preamble_type == 0xC or 0xD
908 * Reserved: HW should fill with 0, FW should ignore.
912 * 0s since the BB does not plan on decoding VHT SIG-B.
915 * Reserved: HW should fill with 0, FW should ignore.
919 * packets will have service field of 0.
922 * Reserved: HW should fill with 0, FW should ignore.
925 #define RX_PPDU_END_FLAGS_PHY_ERR BIT(0)
929 #define RX_PPDU_END_INFO0_RX_ANTENNA_MASK 0x00ffffff
930 #define RX_PPDU_END_INFO0_RX_ANTENNA_LSB 0
934 #define RX_PPDU_END_INFO1_PEER_IDX_MASK 0x1ffc
936 #define RX_PPDU_END_INFO1_BB_DATA BIT(0)
970 #define RX_PPDU_END_RTT_CORRELATION_VALUE_MASK 0x00ffffff
971 #define RX_PPDU_END_RTT_CORRELATION_VALUE_LSB 0
972 #define RX_PPDU_END_RTT_UNUSED_MASK 0x7f000000
986 #define RX_PKT_END_INFO0_RX_SUCCESS BIT(0)
993 #define RX_LOCATION_INFO_RTT_CORR_VAL_MASK 0x0001ffff
994 #define RX_LOCATION_INFO_RTT_CORR_VAL_LSB 0
995 #define RX_LOCATION_INFO_FAC_STATUS_MASK 0x000c0000
997 #define RX_LOCATION_INFO_PKT_BW_MASK 0x00700000
999 #define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_MASK 0x01800000
1019 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK 0x00003fff
1020 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB 0
1021 #define RX_LOCATION_INFO0_RTT_FAC_VHT_MASK 0x1fff8000
1023 #define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK 0xc0000000
1028 #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK 0x0000000c
1030 #define RX_LOCATION_INFO1_PKT_BW_MASK 0x00000030
1032 #define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK 0x0000ff00
1034 #define RX_LOCATION_INFO1_RTT_MSC_RATE_MASK 0x000f0000
1036 #define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK 0x00300000
1038 #define RX_LOCATION_INFO1_TIMING_BACKOFF_MASK 0x07c00000
1040 #define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK 0x18000000
1042 #define RX_LOCATION_INFO1_RTT_CFR_STATUS BIT(0)
1094 RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP = BIT(0),
1115 #define RX_PPDU_END_RX_TIMING_OFFSET_MASK 0x00000fff
1116 #define RX_PPDU_END_RX_TIMING_OFFSET_LSB 0
1118 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_MASK 0x00ffffff
1119 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_LSB 0
1181 * EVM for pilot 0. Contain EVM for streams: 0, 1, 2 and 3.
1184 * EVM for pilot 1. Contain EVM for streams: 0, 1, 2 and 3.
1187 * EVM for pilot 2. Contain EVM for streams: 0, 1, 2 and 3.
1190 * EVM for pilot 3. Contain EVM for streams: 0, 1, 2 and 3.
1193 * EVM for pilot 4. Contain EVM for streams: 0, 1, 2 and 3.
1196 * EVM for pilot 5. Contain EVM for streams: 0, 1, 2 and 3.
1199 * EVM for pilot 6. Contain EVM for streams: 0, 1, 2 and 3.
1202 * EVM for pilot 7. Contain EVM for streams: 0, 1, 2 and 3.
1205 * EVM for pilot 8. Contain EVM for streams: 0, 1, 2 and 3.
1208 * EVM for pilot 9. Contain EVM for streams: 0, 1, 2 and 3.
1211 * EVM for pilot 10. Contain EVM for streams: 0, 1, 2 and 3.
1214 * EVM for pilot 11. Contain EVM for streams: 0, 1, 2 and 3.
1217 * EVM for pilot 12. Contain EVM for streams: 0, 1, 2 and 3.
1220 * EVM for pilot 13. Contain EVM for streams: 0, 1, 2 and 3.
1223 * EVM for pilot 14. Contain EVM for streams: 0, 1, 2 and 3.
1226 * EVM for pilot 15. Contain EVM for streams: 0, 1, 2 and 3.
1244 * nsec. The value starts at 0 and increments to 79 and
1245 * returns to 0 and repeats. This information is valid for
1263 * Reserved: HW should fill with 0, FW should ignore.
1280 * Reserved: HW should fill with 0, FW should ignore.
1284 * PPDUs where the BB descriptor preamble type is 0x80 to 0xFF
1289 * Reserved: HW should fill with 0, FW should ignore.
1295 * to 0.
1298 #define FW_RX_DESC_INFO0_DISCARD BIT(0)
1301 #define FW_RX_DESC_INFO0_EXT_MASK 0xC0
1308 #define FW_RX_DESC_FLAGS_FIRST_MSDU (1 << 0)