728 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)  in ath10k_pci_read32()  function
737 	return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);  in ath10k_pci_soc_read32()
747 	return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);  in ath10k_pci_reg_read32()
760 	cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_irq_pending()
782 	(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_disable_and_clear_legacy_irq()
795 	(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_enable_legacy_irq()
901 	val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)  in ath10k_pci_qca988x_targ_cpu_to_ce_addr()
916 	val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)  in ath10k_pci_qca6174_targ_cpu_to_ce_addr()
926 	val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);  in ath10k_pci_qca99x0_targ_cpu_to_ce_addr()
1645 	val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_set_ram_config()
1975 		val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_irq_msi_fw_mask()
2003 		val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_irq_msi_fw_unmask()
2364 	val = ath10k_pci_read32(ar, addr);  in ath10k_pci_wake_target_cpu()
2639 	return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &  in ath10k_pci_has_fw_crashed()
2647 	val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);  in ath10k_pci_fw_crashed_clear()
2656 	val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);  in ath10k_pci_has_device_gone()
3103 		reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET);  in ath10k_pci_read_eeprom()
3126 	reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET);  in ath10k_pci_read_eeprom()
3182 	.read32			= ath10k_pci_read32,
3389 		val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);  in ath10k_pci_wait_for_target_init()