Lines Matching +full:hdr +full:- +full:engine
1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
62 /* PCI-E QCA988X V2 (Ubiquiti branded) */
65 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
66 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
67 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
68 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
69 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
70 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
71 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
72 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */
128 /* CE0: host->target HTC control and raw streams */
137 /* CE1: target->host HTT + HTC control */
146 /* CE2: target->host WMI */
155 /* CE3: host->target WMI */
164 /* CE4: host->target HTT */
173 /* CE5: target->host HTT (HIF->HTT) */
198 /* CE8: target->host pktlog */
232 /* Target firmware's Copy Engine configuration. */
234 /* CE0: host->target HTC control and raw streams */
244 /* CE1: target->host HTT + HTC control */
254 /* CE2: target->host WMI */
264 /* CE3: host->target WMI */
274 /* CE4: host->target HTT */
286 /* CE5: target->host HTT (HIF->HTT) */
316 /* CE8 target->host packtlog */
342 * Map from service/endpoint to Copy Engine.
349 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
354 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
359 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
364 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
369 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
374 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
379 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
384 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
389 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
394 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
399 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
404 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
409 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
414 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
419 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
424 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
441 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in ath10k_pci_is_awake()
444 u32 val = bus_read_4((struct resource *)ar_pci->mem, PCIE_LOCAL_BASE_ADDRESS + in ath10k_pci_is_awake()
455 lockdep_assert_held(&ar_pci->ps_lock); in __ath10k_pci_wake()
458 ar_pci->ps_wake_refcount, ar_pci->ps_awake); in __ath10k_pci_wake()
462 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in __ath10k_pci_wake()
465 bus_write_4((struct resource *)ar_pci->mem, in __ath10k_pci_wake()
475 lockdep_assert_held(&ar_pci->ps_lock); in __ath10k_pci_sleep()
478 ar_pci->ps_wake_refcount, ar_pci->ps_awake); in __ath10k_pci_sleep()
482 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in __ath10k_pci_sleep()
485 bus_write_4((struct resource *)ar_pci->mem, in __ath10k_pci_sleep()
489 ar_pci->ps_awake = false; in __ath10k_pci_sleep()
512 return -ETIMEDOUT; in ath10k_pci_wake_wait()
521 if (ar_pci->pci_ps) in ath10k_pci_force_wake()
524 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_force_wake()
526 if (!ar_pci->ps_awake) { in ath10k_pci_force_wake()
529 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in ath10k_pci_force_wake()
532 bus_write_4((struct resource *)ar_pci->mem, in ath10k_pci_force_wake()
539 ar_pci->ps_awake = true; in ath10k_pci_force_wake()
542 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_force_wake()
552 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_force_sleep()
556 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in ath10k_pci_force_sleep()
559 bus_write_4((struct resource *)ar_pci->mem, in ath10k_pci_force_sleep()
563 ar_pci->ps_awake = false; in ath10k_pci_force_sleep()
565 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_force_sleep()
574 if (ar_pci->pci_ps == 0) in ath10k_pci_wake()
577 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_wake()
580 ar_pci->ps_wake_refcount, ar_pci->ps_awake); in ath10k_pci_wake()
585 if (!ar_pci->ps_awake) { in ath10k_pci_wake()
590 ar_pci->ps_awake = true; in ath10k_pci_wake()
594 ar_pci->ps_wake_refcount++; in ath10k_pci_wake()
595 WARN_ON(ar_pci->ps_wake_refcount == 0); in ath10k_pci_wake()
598 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_wake()
608 if (ar_pci->pci_ps == 0) in ath10k_pci_sleep()
611 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_sleep()
614 ar_pci->ps_wake_refcount, ar_pci->ps_awake); in ath10k_pci_sleep()
616 if (WARN_ON(ar_pci->ps_wake_refcount == 0)) in ath10k_pci_sleep()
619 ar_pci->ps_wake_refcount--; in ath10k_pci_sleep()
621 mod_timer(&ar_pci->ps_timer, jiffies + in ath10k_pci_sleep()
625 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_sleep()
631 struct ath10k *ar = ar_pci->ar; in ath10k_pci_ps_timer()
634 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_ps_timer()
637 ar_pci->ps_wake_refcount, ar_pci->ps_awake); in ath10k_pci_ps_timer()
639 if (ar_pci->ps_wake_refcount > 0) in ath10k_pci_ps_timer()
645 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_ps_timer()
653 if (ar_pci->pci_ps == 0) { in ath10k_pci_sleep_sync()
658 del_timer_sync(&ar_pci->ps_timer); in ath10k_pci_sleep_sync()
660 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_sleep_sync()
661 WARN_ON(ar_pci->ps_wake_refcount > 0); in ath10k_pci_sleep_sync()
663 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_sleep_sync()
671 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { in ath10k_bus_pci_write32()
672 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", in ath10k_bus_pci_write32()
673 offset, offset + sizeof(value), ar_pci->mem_len); in ath10k_bus_pci_write32()
685 iowrite32(value, ar_pci->mem + offset); in ath10k_bus_pci_write32()
687 bus_write_4((struct resource *)ar_pci->mem, offset, value); in ath10k_bus_pci_write32()
698 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { in ath10k_bus_pci_read32()
699 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", in ath10k_bus_pci_read32()
700 offset, offset + sizeof(val), ar_pci->mem_len); in ath10k_bus_pci_read32()
712 val = ioread32(ar_pci->mem + offset); in ath10k_bus_pci_read32()
714 val = bus_read_4((struct resource *)ar_pci->mem, offset); in ath10k_bus_pci_read32()
725 ce->bus_ops->write32(ar, offset, value); in ath10k_pci_write32()
732 return ce->bus_ops->read32(ar, offset); in ath10k_pci_read32()
803 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI) in ath10k_pci_get_irq_method()
811 struct ath10k *ar = pipe->hif_ce_state; in __ath10k_pci_rx_post_buf()
813 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; in __ath10k_pci_rx_post_buf()
818 skb = dev_alloc_skb(pipe->buf_sz); in __ath10k_pci_rx_post_buf()
820 return -ENOMEM; in __ath10k_pci_rx_post_buf()
822 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); in __ath10k_pci_rx_post_buf()
824 paddr = dma_map_single(ar->dev, skb->data, in __ath10k_pci_rx_post_buf()
825 skb->len + skb_tailroom(skb), in __ath10k_pci_rx_post_buf()
827 if (unlikely(dma_mapping_error(ar->dev, paddr))) { in __ath10k_pci_rx_post_buf()
830 return -EIO; in __ath10k_pci_rx_post_buf()
833 ATH10K_SKB_RXCB(skb)->paddr = paddr; in __ath10k_pci_rx_post_buf()
835 spin_lock_bh(&ce->ce_lock); in __ath10k_pci_rx_post_buf()
836 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr); in __ath10k_pci_rx_post_buf()
837 spin_unlock_bh(&ce->ce_lock); in __ath10k_pci_rx_post_buf()
839 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), in __ath10k_pci_rx_post_buf()
850 struct ath10k *ar = pipe->hif_ce_state; in ath10k_pci_rx_post_pipe()
853 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; in ath10k_pci_rx_post_pipe()
856 if (pipe->buf_sz == 0) in ath10k_pci_rx_post_pipe()
859 if (!ce_pipe->dest_ring) in ath10k_pci_rx_post_pipe()
862 spin_lock_bh(&ce->ce_lock); in ath10k_pci_rx_post_pipe()
864 spin_unlock_bh(&ce->ce_lock); in ath10k_pci_rx_post_pipe()
869 if (ret == -ENOSPC) in ath10k_pci_rx_post_pipe()
872 mod_timer(&ar_pci->rx_post_retry, jiffies + in ath10k_pci_rx_post_pipe()
876 num--; in ath10k_pci_rx_post_pipe()
886 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); in ath10k_pci_rx_post()
892 struct ath10k *ar = ar_pci->ar; in ath10k_pci_rx_replenish_retry()
935 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr)) in ath10k_pci_targ_cpu_to_ce_addr()
936 return -ENOTSUPP; in ath10k_pci_targ_cpu_to_ce_addr()
938 return ar_pci->targ_cpu_to_ce_addr(ar, addr); in ath10k_pci_targ_cpu_to_ce_addr()
964 mutex_lock(&ar_pci->ce_diag_mutex); in ath10k_pci_diag_read_mem()
965 ce_diag = ar_pci->ce_diag; in ath10k_pci_diag_read_mem()
970 * 1) 4-byte alignment in ath10k_pci_diag_read_mem()
971 * 2) Buffer in DMA-able space in ath10k_pci_diag_read_mem()
975 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, in ath10k_pci_diag_read_mem()
978 ret = -ENOMEM; in ath10k_pci_diag_read_mem()
1012 ret = -EBUSY; in ath10k_pci_diag_read_mem()
1024 ret = -EBUSY; in ath10k_pci_diag_read_mem()
1030 ret = -EIO; in ath10k_pci_diag_read_mem()
1035 ret = -EIO; in ath10k_pci_diag_read_mem()
1039 remaining_bytes -= nbytes; in ath10k_pci_diag_read_mem()
1049 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, in ath10k_pci_diag_read_mem()
1052 mutex_unlock(&ar_pci->ce_diag_mutex); in ath10k_pci_diag_read_mem()
1119 mutex_lock(&ar_pci->ce_diag_mutex); in ath10k_pci_diag_write_mem()
1120 ce_diag = ar_pci->ce_diag; in ath10k_pci_diag_write_mem()
1125 * 1) 4-byte alignment in ath10k_pci_diag_write_mem()
1126 * 2) Buffer in DMA-able space in ath10k_pci_diag_write_mem()
1130 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, in ath10k_pci_diag_write_mem()
1133 ret = -ENOMEM; in ath10k_pci_diag_write_mem()
1163 * Request CE to send caller-supplied data that in ath10k_pci_diag_write_mem()
1176 ret = -EBUSY; in ath10k_pci_diag_write_mem()
1188 ret = -EBUSY; in ath10k_pci_diag_write_mem()
1194 ret = -EIO; in ath10k_pci_diag_write_mem()
1199 ret = -EIO; in ath10k_pci_diag_write_mem()
1203 remaining_bytes -= nbytes; in ath10k_pci_diag_write_mem()
1210 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, in ath10k_pci_diag_write_mem()
1218 mutex_unlock(&ar_pci->ce_diag_mutex); in ath10k_pci_diag_write_mem()
1233 struct ath10k *ar = ce_state->ar; in ath10k_pci_htc_tx_cb()
1254 struct ath10k *ar = ce_state->ar; in ath10k_pci_process_rx_cb()
1256 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; in ath10k_pci_process_rx_cb()
1266 max_nbytes = skb->len + skb_tailroom(skb); in ath10k_pci_process_rx_cb()
1267 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, in ath10k_pci_process_rx_cb()
1283 ce_state->id, skb->len); in ath10k_pci_process_rx_cb()
1285 skb->data, skb->len); in ath10k_pci_process_rx_cb()
1297 struct ath10k *ar = ce_state->ar; in ath10k_pci_process_htt_rx_cb()
1299 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; in ath10k_pci_process_htt_rx_cb()
1300 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl; in ath10k_pci_process_htt_rx_cb()
1315 max_nbytes = skb->len + skb_tailroom(skb); in ath10k_pci_process_htt_rx_cb()
1323 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, in ath10k_pci_process_htt_rx_cb()
1332 ce_state->id, skb->len); in ath10k_pci_process_htt_rx_cb()
1334 skb->data, skb->len); in ath10k_pci_process_htt_rx_cb()
1336 orig_len = skb->len; in ath10k_pci_process_htt_rx_cb()
1338 skb_push(skb, orig_len - skb->len); in ath10k_pci_process_htt_rx_cb()
1343 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, in ath10k_pci_process_htt_rx_cb()
1344 skb->len + skb_tailroom(skb), in ath10k_pci_process_htt_rx_cb()
1359 * HTT Rx (target->host) is processed. in ath10k_pci_htt_htc_rx_cb()
1361 ath10k_ce_per_engine_service(ce_state->ar, 4); in ath10k_pci_htt_htc_rx_cb()
1378 struct ath10k *ar = ce_state->ar; in ath10k_pci_htt_tx_cb()
1386 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, in ath10k_pci_htt_tx_cb()
1387 skb->len, DMA_TO_DEVICE); in ath10k_pci_htt_tx_cb()
1402 * HTT Rx (target->host) is processed. in ath10k_pci_htt_rx_cb()
1404 ath10k_ce_per_engine_service(ce_state->ar, 4); in ath10k_pci_htt_rx_cb()
1414 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; in ath10k_pci_hif_tx_sg()
1415 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; in ath10k_pci_hif_tx_sg()
1416 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; in ath10k_pci_hif_tx_sg()
1422 spin_lock_bh(&ce->ce_lock); in ath10k_pci_hif_tx_sg()
1424 nentries_mask = src_ring->nentries_mask; in ath10k_pci_hif_tx_sg()
1425 sw_index = src_ring->sw_index; in ath10k_pci_hif_tx_sg()
1426 write_index = src_ring->write_index; in ath10k_pci_hif_tx_sg()
1429 write_index, sw_index - 1) < n_items)) { in ath10k_pci_hif_tx_sg()
1430 err = -ENOBUFS; in ath10k_pci_hif_tx_sg()
1434 for (i = 0; i < n_items - 1; i++) { in ath10k_pci_hif_tx_sg()
1451 /* `i` is equal to `n_items -1` after for() */ in ath10k_pci_hif_tx_sg()
1461 * XXX-BZ specific debug; the DELAY makes things work for one chipset. in ath10k_pci_hif_tx_sg()
1483 spin_unlock_bh(&ce->ce_lock); in ath10k_pci_hif_tx_sg()
1487 for (; i > 0; i--) in ath10k_pci_hif_tx_sg()
1490 spin_unlock_bh(&ce->ce_lock); in ath10k_pci_hif_tx_sg()
1506 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); in ath10k_pci_hif_get_free_queue_number()
1515 lockdep_assert_held(&ar->dump_mutex); in ath10k_pci_dump_registers()
1540 crash_data->registers[i] = reg_dump_values[i]; in ath10k_pci_dump_registers()
1554 cur_section = &mem_region->section_table.sections[0]; in ath10k_pci_dump_memory_section()
1556 if (mem_region->start > cur_section->start) { in ath10k_pci_dump_memory_section()
1558 mem_region->start, cur_section->start); in ath10k_pci_dump_memory_section()
1562 skip_size = cur_section->start - mem_region->start; in ath10k_pci_dump_memory_section()
1575 section_size = cur_section->end - cur_section->start; in ath10k_pci_dump_memory_section()
1579 cur_section->start, in ath10k_pci_dump_memory_section()
1580 cur_section->end); in ath10k_pci_dump_memory_section()
1584 if ((i + 1) == mem_region->section_table.size) { in ath10k_pci_dump_memory_section()
1591 if (cur_section->end > next_section->start) { in ath10k_pci_dump_memory_section()
1593 next_section->start, in ath10k_pci_dump_memory_section()
1594 cur_section->end); in ath10k_pci_dump_memory_section()
1598 skip_size = next_section->start - cur_section->end; in ath10k_pci_dump_memory_section()
1606 buf_len -= skip_size + section_size; in ath10k_pci_dump_memory_section()
1609 ret = ath10k_pci_diag_read_mem(ar, cur_section->start, in ath10k_pci_dump_memory_section()
1613 cur_section->start, ret); in ath10k_pci_dump_memory_section()
1650 return -EIO; in ath10k_pci_set_ram_config()
1665 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG); in ath10k_pci_dump_memory_sram()
1667 base_addr = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_PCIE_BAR0_START_REG); in ath10k_pci_dump_memory_sram()
1669 base_addr += region->start; in ath10k_pci_dump_memory_sram()
1671 for (i = 0; i < region->len; i += 4) { in ath10k_pci_dump_memory_sram()
1673 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG); in ath10k_pci_dump_memory_sram()
1674 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG); in ath10k_pci_dump_memory_sram()
1676 bus_write_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_ADDR_REG, base_addr + i); in ath10k_pci_dump_memory_sram()
1677 *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_DATA_REG); in ath10k_pci_dump_memory_sram()
1681 return region->len; in ath10k_pci_dump_memory_sram()
1693 mutex_lock(&ar->conf_mutex); in ath10k_pci_dump_memory_reg()
1694 if (ar->state != ATH10K_STATE_ON) { in ath10k_pci_dump_memory_reg()
1696 ret = -EIO; in ath10k_pci_dump_memory_reg()
1700 for (i = 0; i < region->len; i += 4) in ath10k_pci_dump_memory_reg()
1702 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i); in ath10k_pci_dump_memory_reg()
1704 *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, region->start + i); in ath10k_pci_dump_memory_reg()
1707 ret = region->len; in ath10k_pci_dump_memory_reg()
1709 mutex_unlock(&ar->conf_mutex); in ath10k_pci_dump_memory_reg()
1720 if (current_region->section_table.size > 0) in ath10k_pci_dump_memory_generic()
1725 current_region->len); in ath10k_pci_dump_memory_generic()
1731 current_region->start, in ath10k_pci_dump_memory_generic()
1733 current_region->len); in ath10k_pci_dump_memory_generic()
1736 current_region->name, ret); in ath10k_pci_dump_memory_generic()
1740 return current_region->len; in ath10k_pci_dump_memory_generic()
1748 struct ath10k_dump_ram_data_hdr *hdr; in ath10k_pci_dump_memory() local
1754 lockdep_assert_held(&ar->dump_mutex); in ath10k_pci_dump_memory()
1763 current_region = &mem_layout->region_table.regions[0]; in ath10k_pci_dump_memory()
1765 buf = crash_data->ramdump_buf; in ath10k_pci_dump_memory()
1766 buf_len = crash_data->ramdump_buf_len; in ath10k_pci_dump_memory()
1770 for (i = 0; i < mem_layout->region_table.size; i++) { in ath10k_pci_dump_memory()
1773 if (current_region->len > buf_len) { in ath10k_pci_dump_memory()
1775 current_region->name, in ath10k_pci_dump_memory()
1776 current_region->len, in ath10k_pci_dump_memory()
1784 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 || in ath10k_pci_dump_memory()
1785 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) { in ath10k_pci_dump_memory()
1786 shift = current_region->start >> 20; in ath10k_pci_dump_memory()
1791 current_region->name, ret); in ath10k_pci_dump_memory()
1797 hdr = (void *)buf; in ath10k_pci_dump_memory()
1798 buf += sizeof(*hdr); in ath10k_pci_dump_memory()
1799 buf_len -= sizeof(*hdr); in ath10k_pci_dump_memory()
1801 switch (current_region->type) { in ath10k_pci_dump_memory()
1821 hdr->region_type = cpu_to_le32(current_region->type); in ath10k_pci_dump_memory()
1822 hdr->start = cpu_to_le32(current_region->start); in ath10k_pci_dump_memory()
1823 hdr->length = cpu_to_le32(count); in ath10k_pci_dump_memory()
1830 buf_len -= count; in ath10k_pci_dump_memory()
1841 struct ath10k *ar = ar_pci->ar; in ath10k_pci_fw_dump_work()
1844 mutex_lock(&ar->dump_mutex); in ath10k_pci_fw_dump_work()
1846 spin_lock_bh(&ar->data_lock); in ath10k_pci_fw_dump_work()
1847 ar->stats.fw_crash_counter++; in ath10k_pci_fw_dump_work()
1848 spin_unlock_bh(&ar->data_lock); in ath10k_pci_fw_dump_work()
1853 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); in ath10k_pci_fw_dump_work()
1863 mutex_unlock(&ar->dump_mutex); in ath10k_pci_fw_dump_work()
1872 queue_work(ar->workqueue, &ar_pci->dump_work); in ath10k_pci_fw_crashed_dump()
1897 if (resources > (ar_pci->attr[pipe].src_nentries >> 1)) in ath10k_pci_hif_send_complete_check()
1907 del_timer_sync(&ar_pci->rx_post_retry); in ath10k_pci_rx_retry_sync()
1921 entry = &ar_pci->serv_to_pipe[i]; in ath10k_pci_hif_map_service_to_pipe()
1923 if (__le32_to_cpu(entry->service_id) != service_id) in ath10k_pci_hif_map_service_to_pipe()
1926 switch (__le32_to_cpu(entry->pipedir)) { in ath10k_pci_hif_map_service_to_pipe()
1931 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath10k_pci_hif_map_service_to_pipe()
1936 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath10k_pci_hif_map_service_to_pipe()
1942 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath10k_pci_hif_map_service_to_pipe()
1943 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath10k_pci_hif_map_service_to_pipe()
1951 return -ENOENT; in ath10k_pci_hif_map_service_to_pipe()
1970 switch (ar->hw_rev) { in ath10k_pci_irq_msi_fw_mask()
1998 switch (ar->hw_rev) { in ath10k_pci_irq_msi_fw_unmask()
2033 synchronize_irq(ar_pci->pdev->irq); in ath10k_pci_irq_sync()
2054 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, in ath10k_pci_hif_start()
2055 ar_pci->link_ctl); in ath10k_pci_hif_start()
2068 ar = pci_pipe->hif_ce_state; in ath10k_pci_rx_pipe_cleanup()
2069 ce_pipe = pci_pipe->ce_hdl; in ath10k_pci_rx_pipe_cleanup()
2070 ce_ring = ce_pipe->dest_ring; in ath10k_pci_rx_pipe_cleanup()
2075 if (!pci_pipe->buf_sz) in ath10k_pci_rx_pipe_cleanup()
2078 for (i = 0; i < ce_ring->nentries; i++) { in ath10k_pci_rx_pipe_cleanup()
2079 skb = ce_ring->per_transfer_context[i]; in ath10k_pci_rx_pipe_cleanup()
2083 ce_ring->per_transfer_context[i] = NULL; in ath10k_pci_rx_pipe_cleanup()
2085 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, in ath10k_pci_rx_pipe_cleanup()
2086 skb->len + skb_tailroom(skb), in ath10k_pci_rx_pipe_cleanup()
2100 ar = pci_pipe->hif_ce_state; in ath10k_pci_tx_pipe_cleanup()
2101 ce_pipe = pci_pipe->ce_hdl; in ath10k_pci_tx_pipe_cleanup()
2102 ce_ring = ce_pipe->src_ring; in ath10k_pci_tx_pipe_cleanup()
2107 if (!pci_pipe->buf_sz) in ath10k_pci_tx_pipe_cleanup()
2110 for (i = 0; i < ce_ring->nentries; i++) { in ath10k_pci_tx_pipe_cleanup()
2111 skb = ce_ring->per_transfer_context[i]; in ath10k_pci_tx_pipe_cleanup()
2115 ce_ring->per_transfer_context[i] = NULL; in ath10k_pci_tx_pipe_cleanup()
2137 pipe_info = &ar_pci->pipe_info[pipe_num]; in ath10k_pci_buffer_cleanup()
2169 cancel_work_sync(&ar_pci->dump_work); in ath10k_pci_hif_stop()
2176 * For ranged MSI the CE-related interrupts can be masked. However in ath10k_pci_hif_stop()
2186 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_hif_stop()
2187 WARN_ON(ar_pci->ps_wake_refcount > 0); in ath10k_pci_hif_stop()
2188 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_hif_stop()
2196 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; in ath10k_pci_hif_exchange_bmi_msg()
2197 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; in ath10k_pci_hif_exchange_bmi_msg()
2198 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; in ath10k_pci_hif_exchange_bmi_msg()
2199 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; in ath10k_pci_hif_exchange_bmi_msg()
2209 return -EINVAL; in ath10k_pci_hif_exchange_bmi_msg()
2212 return -EINVAL; in ath10k_pci_hif_exchange_bmi_msg()
2216 return -ENOMEM; in ath10k_pci_hif_exchange_bmi_msg()
2218 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); in ath10k_pci_hif_exchange_bmi_msg()
2219 ret = dma_mapping_error(ar->dev, req_paddr); in ath10k_pci_hif_exchange_bmi_msg()
2221 ret = -EIO; in ath10k_pci_hif_exchange_bmi_msg()
2228 ret = -ENOMEM; in ath10k_pci_hif_exchange_bmi_msg()
2232 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, in ath10k_pci_hif_exchange_bmi_msg()
2234 ret = dma_mapping_error(ar->dev, resp_paddr); in ath10k_pci_hif_exchange_bmi_msg()
2236 ret = -EIO; in ath10k_pci_hif_exchange_bmi_msg()
2246 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); in ath10k_pci_hif_exchange_bmi_msg()
2259 /* non-zero means we did not time out */ in ath10k_pci_hif_exchange_bmi_msg()
2268 dma_unmap_single(ar->dev, resp_paddr, in ath10k_pci_hif_exchange_bmi_msg()
2272 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); in ath10k_pci_hif_exchange_bmi_msg()
2292 xfer->tx_done = true; in ath10k_pci_bmi_send_done()
2297 struct ath10k *ar = ce_state->ar; in ath10k_pci_bmi_recv_data()
2308 if (!xfer->wait_for_resp) { in ath10k_pci_bmi_recv_data()
2313 xfer->resp_len = nbytes; in ath10k_pci_bmi_recv_data()
2314 xfer->rx_done = true; in ath10k_pci_bmi_recv_data()
2331 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) { in ath10k_pci_bmi_wait()
2339 /* Using LinuxKPI we'll hang for-ever as there's no wake_up */ in ath10k_pci_bmi_wait()
2344 ret = -ETIMEDOUT; in ath10k_pci_bmi_wait()
2347 dur = jiffies - started; in ath10k_pci_bmi_wait()
2375 switch (ar_pci->pdev->device) { in ath10k_pci_get_num_banks()
2385 switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) { in ath10k_pci_get_num_banks()
2411 return ce->bus_ops->get_num_banks(ar); in ath10k_bus_get_num_banks()
2428 /* Download to Target the CE Config and the service-to-CE map */ in ath10k_pci_init_config()
2432 /* Supply Target-side CE configuration */ in ath10k_pci_init_config()
2441 ret = -EIO; in ath10k_pci_init_config()
2456 ret = -EIO; in ath10k_pci_init_config()
2462 ar_pci->pipe_config, in ath10k_pci_init_config()
2481 ret = -EIO; in ath10k_pci_init_config()
2487 ar_pci->serv_to_pipe, in ath10k_pci_init_config()
2562 /* For QCA6174 we're overriding the Copy Engine 5 configuration, in ath10k_pci_override_ce_config()
2566 /* Override Host's Copy Engine 5 configuration */ in ath10k_pci_override_ce_config()
2567 attr = &ar_pci->attr[5]; in ath10k_pci_override_ce_config()
2568 attr->src_sz_max = 0; in ath10k_pci_override_ce_config()
2569 attr->dest_nentries = 0; in ath10k_pci_override_ce_config()
2571 /* Override Target firmware's Copy Engine configuration */ in ath10k_pci_override_ce_config()
2572 config = &ar_pci->pipe_config[5]; in ath10k_pci_override_ce_config()
2573 config->pipedir = __cpu_to_le32(PIPEDIR_OUT); in ath10k_pci_override_ce_config()
2574 config->nbytes_max = __cpu_to_le32(2048); in ath10k_pci_override_ce_config()
2576 /* Map from service/endpoint to Copy Engine */ in ath10k_pci_override_ce_config()
2577 ar_pci->serv_to_pipe[15].pipenum = __cpu_to_le32(1); in ath10k_pci_override_ce_config()
2588 pipe = &ar_pci->pipe_info[i]; in ath10k_pci_alloc_pipes()
2589 pipe->ce_hdl = &ce->ce_states[i]; in ath10k_pci_alloc_pipes()
2590 pipe->pipe_num = i; in ath10k_pci_alloc_pipes()
2591 pipe->hif_ce_state = ar; in ath10k_pci_alloc_pipes()
2593 ret = ath10k_ce_alloc_pipe(ar, i, &ar_pci->attr[i]); in ath10k_pci_alloc_pipes()
2595 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", in ath10k_pci_alloc_pipes()
2602 ar_pci->ce_diag = pipe->ce_hdl; in ath10k_pci_alloc_pipes()
2606 pipe->buf_sz = (size_t)(ar_pci->attr[i].src_sz_max); in ath10k_pci_alloc_pipes()
2626 ret = ath10k_ce_init_pipe(ar, i, &ar_pci->attr[i]); in ath10k_pci_init_pipes()
2628 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", in ath10k_pci_init_pipes()
2719 spin_lock_bh(&ar->data_lock); in ath10k_pci_warm_reset()
2720 ar->stats.fw_warm_reset_counter++; in ath10k_pci_warm_reset()
2721 spin_unlock_bh(&ar->data_lock); in ath10k_pci_warm_reset()
2726 * were to access copy engine while host performs copy engine reset in ath10k_pci_warm_reset()
2727 * then it is possible for the device to confuse pci-e controller to in ath10k_pci_warm_reset()
2761 if (!ar_pci->pci_soft_reset) in ath10k_pci_safe_chip_reset()
2762 return -ENOTSUPP; in ath10k_pci_safe_chip_reset()
2764 return ar_pci->pci_soft_reset(ar); in ath10k_pci_safe_chip_reset()
2790 /* FIXME: Sometimes copy engine doesn't recover after warm in ath10k_pci_qca988x_chip_reset()
2795 * Reading any host interest register via copy engine is in ath10k_pci_qca988x_chip_reset()
2801 ath10k_warn(ar, "failed to init copy engine: %d\n", in ath10k_pci_qca988x_chip_reset()
2809 ath10k_warn(ar, "failed to poke copy engine: %d\n", in ath10k_pci_qca988x_chip_reset()
2820 return -EPERM; in ath10k_pci_qca988x_chip_reset()
2901 if (WARN_ON(!ar_pci->pci_hard_reset)) in ath10k_pci_chip_reset()
2902 return -ENOTSUPP; in ath10k_pci_chip_reset()
2904 return ar_pci->pci_hard_reset(ar); in ath10k_pci_chip_reset()
2915 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, in ath10k_pci_hif_power_up()
2916 &ar_pci->link_ctl); in ath10k_pci_hif_power_up()
2917 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, in ath10k_pci_hif_power_up()
2918 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); in ath10k_pci_hif_power_up()
2923 * The target may be in an undefined state with an AUX-powered Target in ath10k_pci_hif_power_up()
2987 /* The grace timer can still be counting down and ar->ps_awake be true. in ath10k_pci_suspend()
3008 struct pci_dev *pdev = ar_pci->pdev; in ath10k_pci_resume()
3019 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries in ath10k_pci_resume()
3070 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */ in ath10k_pci_enable_eeprom()
3107 wait_limit--; in ath10k_pci_read_eeprom()
3114 return -ETIMEDOUT; in ath10k_pci_read_eeprom()
3122 return -EIO; in ath10k_pci_read_eeprom()
3140 return -EOPNOTSUPP; in ath10k_pci_hif_fetch_cal_eeprom()
3142 calsize = ar->hw_params.cal_data_len; in ath10k_pci_hif_fetch_cal_eeprom()
3145 return -ENOMEM; in ath10k_pci_hif_fetch_cal_eeprom()
3166 return -EINVAL; in ath10k_pci_hif_fetch_cal_eeprom()
3190 * Top-level interrupt handler for all PCI interrupts from a Target.
3191 * When a block of MSI interrupts is allocated, this top-level handler
3192 * is not used; instead, we directly call the correct sub-handler.
3209 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) && in ath10k_pci_interrupt_handler()
3215 napi_schedule(&ar->napi); in ath10k_pci_interrupt_handler()
3240 * received after processing all copy engine pipes by NAPI poll in ath10k_pci_napi_poll()
3263 ret = request_irq(ar_pci->pdev->irq, in ath10k_pci_request_irq_msi()
3268 ar_pci->pdev->irq, ret); in ath10k_pci_request_irq_msi()
3280 ret = request_irq(ar_pci->pdev->irq, in ath10k_pci_request_irq_legacy()
3285 ar_pci->pdev->irq, ret); in ath10k_pci_request_irq_legacy()
3296 switch (ar_pci->oper_irq_mode) { in ath10k_pci_request_irq()
3302 return -EINVAL; in ath10k_pci_request_irq()
3310 free_irq(ar_pci->pdev->irq, ar); in ath10k_pci_free_irq()
3315 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll); in ath10k_pci_init_napi()
3331 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI; in ath10k_pci_init_irq()
3332 ret = pci_enable_msi(ar_pci->pdev); in ath10k_pci_init_irq()
3348 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; in ath10k_pci_init_irq()
3366 switch (ar_pci->oper_irq_mode) { in ath10k_pci_deinit_irq()
3371 pci_disable_msi(ar_pci->pdev); in ath10k_pci_deinit_irq()
3405 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) in ath10k_pci_wait_for_target_init()
3417 return -EIO; in ath10k_pci_wait_for_target_init()
3422 return -ECOMM; in ath10k_pci_wait_for_target_init()
3428 return -ETIMEDOUT; in ath10k_pci_wait_for_target_init()
3441 spin_lock_bh(&ar->data_lock); in ath10k_pci_cold_reset()
3443 ar->stats.fw_cold_reset_counter++; in ath10k_pci_cold_reset()
3445 spin_unlock_bh(&ar->data_lock); in ath10k_pci_cold_reset()
3473 struct pci_dev *pdev = ar_pci->pdev; in ath10k_pci_claim()
3492 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in ath10k_pci_claim()
3494 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); in ath10k_pci_claim()
3505 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); in ath10k_pci_claim()
3506 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); in ath10k_pci_claim()
3507 if (!ar_pci->mem) { in ath10k_pci_claim()
3509 ret = -EIO; in ath10k_pci_claim()
3513 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem); in ath10k_pci_claim()
3528 struct pci_dev *pdev = ar_pci->pdev; in ath10k_pci_release()
3530 pci_iounmap(pdev, ar_pci->mem); in ath10k_pci_release()
3544 if (supp_chip->dev_id == dev_id && in ath10k_pci_chip_is_supported()
3545 supp_chip->rev_id == rev_id) in ath10k_pci_chip_is_supported()
3558 spin_lock_init(&ce->ce_lock); in ath10k_pci_setup_resource()
3559 spin_lock_init(&ar_pci->ps_lock); in ath10k_pci_setup_resource()
3560 mutex_init(&ar_pci->ce_diag_mutex); in ath10k_pci_setup_resource()
3562 INIT_WORK(&ar_pci->dump_work, ath10k_pci_fw_dump_work); in ath10k_pci_setup_resource()
3564 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0); in ath10k_pci_setup_resource()
3566 ar_pci->attr = kmemdup(pci_host_ce_config_wlan, in ath10k_pci_setup_resource()
3569 if (!ar_pci->attr) in ath10k_pci_setup_resource()
3570 return -ENOMEM; in ath10k_pci_setup_resource()
3572 ar_pci->pipe_config = kmemdup(pci_target_ce_config_wlan, in ath10k_pci_setup_resource()
3575 if (!ar_pci->pipe_config) { in ath10k_pci_setup_resource()
3576 ret = -ENOMEM; in ath10k_pci_setup_resource()
3580 ar_pci->serv_to_pipe = kmemdup(pci_target_service_to_ce_map_wlan, in ath10k_pci_setup_resource()
3583 if (!ar_pci->serv_to_pipe) { in ath10k_pci_setup_resource()
3584 ret = -ENOMEM; in ath10k_pci_setup_resource()
3593 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", in ath10k_pci_setup_resource()
3601 kfree(ar_pci->serv_to_pipe); in ath10k_pci_setup_resource()
3603 kfree(ar_pci->pipe_config); in ath10k_pci_setup_resource()
3605 kfree(ar_pci->attr); in ath10k_pci_setup_resource()
3614 netif_napi_del(&ar->napi); in ath10k_pci_release_resource()
3617 kfree(ar_pci->attr); in ath10k_pci_release_resource()
3618 kfree(ar_pci->pipe_config); in ath10k_pci_release_resource()
3619 kfree(ar_pci->serv_to_pipe); in ath10k_pci_release_resource()
3641 switch (pci_dev->device) { in ath10k_pci_probe()
3696 return -ENOTSUPP; in ath10k_pci_probe()
3699 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, in ath10k_pci_probe()
3702 dev_err(&pdev->dev, "failed to allocate core\n"); in ath10k_pci_probe()
3703 return -ENOMEM; in ath10k_pci_probe()
3707 pdev->vendor, pdev->device, in ath10k_pci_probe()
3708 pdev->subsystem_vendor, pdev->subsystem_device); in ath10k_pci_probe()
3711 ar_pci->pdev = pdev; in ath10k_pci_probe()
3712 ar_pci->dev = &pdev->dev; in ath10k_pci_probe()
3713 ar_pci->ar = ar; in ath10k_pci_probe()
3714 ar->dev_id = pci_dev->device; in ath10k_pci_probe()
3715 ar_pci->pci_ps = pci_ps; in ath10k_pci_probe()
3716 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops; in ath10k_pci_probe()
3717 ar_pci->pci_soft_reset = pci_soft_reset; in ath10k_pci_probe()
3718 ar_pci->pci_hard_reset = pci_hard_reset; in ath10k_pci_probe()
3719 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; in ath10k_pci_probe()
3720 ar->ce_priv = &ar_pci->ce; in ath10k_pci_probe()
3722 ar->id.vendor = pdev->vendor; in ath10k_pci_probe()
3723 ar->id.device = pdev->device; in ath10k_pci_probe()
3724 ar->id.subsystem_vendor = pdev->subsystem_vendor; in ath10k_pci_probe()
3725 ar->id.subsystem_device = pdev->subsystem_device; in ath10k_pci_probe()
3727 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0); in ath10k_pci_probe()
3757 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode, in ath10k_pci_probe()
3768 /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that in ath10k_pci_probe()
3776 if (!ath10k_pci_chip_is_supported(pdev->device, in ath10k_pci_probe()
3778 ret = -ENODEV; in ath10k_pci_probe()
3792 ret = -ENODEV; in ath10k_pci_probe()
3796 if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) { in ath10k_pci_probe()
3797 ret = -ENODEV; in ath10k_pci_probe()
3811 pdev->device, bus_params.chip_id); in ath10k_pci_probe()
3893 .bsd_probe_return = (BUS_PROBE_DEFAULT - 1),