Lines Matching +full:- +full:ar
1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
62 /* PCI-E QCA988X V2 (Ubiquiti branded) */
65 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
66 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
67 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
68 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
69 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
70 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
71 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
72 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */
108 static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
109 static int ath10k_pci_cold_reset(struct ath10k *ar);
110 static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
111 static int ath10k_pci_init_irq(struct ath10k *ar);
112 static int ath10k_pci_deinit_irq(struct ath10k *ar);
113 static int ath10k_pci_request_irq(struct ath10k *ar);
114 static void ath10k_pci_free_irq(struct ath10k *ar);
115 static int ath10k_pci_bmi_wait(struct ath10k *ar,
119 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
128 /* CE0: host->target HTC control and raw streams */
137 /* CE1: target->host HTT + HTC control */
146 /* CE2: target->host WMI */
155 /* CE3: host->target WMI */
164 /* CE4: host->target HTT */
173 /* CE5: target->host HTT (HIF->HTT) */
198 /* CE8: target->host pktlog */
234 /* CE0: host->target HTC control and raw streams */
244 /* CE1: target->host HTT + HTC control */
254 /* CE2: target->host WMI */
264 /* CE3: host->target WMI */
274 /* CE4: host->target HTT */
286 /* CE5: target->host HTT (HIF->HTT) */
316 /* CE8 target->host packtlog */
349 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
354 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
359 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
364 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
369 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
374 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
379 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
384 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
389 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
394 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
399 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
404 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
409 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
414 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
419 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
424 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
437 static bool ath10k_pci_is_awake(struct ath10k *ar) in ath10k_pci_is_awake() argument
439 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_is_awake()
441 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in ath10k_pci_is_awake()
444 u32 val = bus_read_4((struct resource *)ar_pci->mem, PCIE_LOCAL_BASE_ADDRESS + in ath10k_pci_is_awake()
451 static void __ath10k_pci_wake(struct ath10k *ar) in __ath10k_pci_wake() argument
453 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in __ath10k_pci_wake()
455 lockdep_assert_held(&ar_pci->ps_lock); in __ath10k_pci_wake()
457 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n", in __ath10k_pci_wake()
458 ar_pci->ps_wake_refcount, ar_pci->ps_awake); in __ath10k_pci_wake()
462 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in __ath10k_pci_wake()
465 bus_write_4((struct resource *)ar_pci->mem, in __ath10k_pci_wake()
471 static void __ath10k_pci_sleep(struct ath10k *ar) in __ath10k_pci_sleep() argument
473 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in __ath10k_pci_sleep()
475 lockdep_assert_held(&ar_pci->ps_lock); in __ath10k_pci_sleep()
477 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n", in __ath10k_pci_sleep()
478 ar_pci->ps_wake_refcount, ar_pci->ps_awake); in __ath10k_pci_sleep()
482 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in __ath10k_pci_sleep()
485 bus_write_4((struct resource *)ar_pci->mem, in __ath10k_pci_sleep()
489 ar_pci->ps_awake = false; in __ath10k_pci_sleep()
492 static int ath10k_pci_wake_wait(struct ath10k *ar) in ath10k_pci_wake_wait() argument
498 if (ath10k_pci_is_awake(ar)) { in ath10k_pci_wake_wait()
500 …ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n", in ath10k_pci_wake_wait()
512 return -ETIMEDOUT; in ath10k_pci_wake_wait()
515 static int ath10k_pci_force_wake(struct ath10k *ar) in ath10k_pci_force_wake() argument
517 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_force_wake()
521 if (ar_pci->pci_ps) in ath10k_pci_force_wake()
524 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_force_wake()
526 if (!ar_pci->ps_awake) { in ath10k_pci_force_wake()
529 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in ath10k_pci_force_wake()
532 bus_write_4((struct resource *)ar_pci->mem, in ath10k_pci_force_wake()
537 ret = ath10k_pci_wake_wait(ar); in ath10k_pci_force_wake()
539 ar_pci->ps_awake = true; in ath10k_pci_force_wake()
542 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_force_wake()
547 static void ath10k_pci_force_sleep(struct ath10k *ar) in ath10k_pci_force_sleep() argument
549 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_force_sleep()
552 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_force_sleep()
556 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in ath10k_pci_force_sleep()
559 bus_write_4((struct resource *)ar_pci->mem, in ath10k_pci_force_sleep()
563 ar_pci->ps_awake = false; in ath10k_pci_force_sleep()
565 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_force_sleep()
568 static int ath10k_pci_wake(struct ath10k *ar) in ath10k_pci_wake() argument
570 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_wake()
574 if (ar_pci->pci_ps == 0) in ath10k_pci_wake()
577 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_wake()
579 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n", in ath10k_pci_wake()
580 ar_pci->ps_wake_refcount, ar_pci->ps_awake); in ath10k_pci_wake()
585 if (!ar_pci->ps_awake) { in ath10k_pci_wake()
586 __ath10k_pci_wake(ar); in ath10k_pci_wake()
588 ret = ath10k_pci_wake_wait(ar); in ath10k_pci_wake()
590 ar_pci->ps_awake = true; in ath10k_pci_wake()
594 ar_pci->ps_wake_refcount++; in ath10k_pci_wake()
595 WARN_ON(ar_pci->ps_wake_refcount == 0); in ath10k_pci_wake()
598 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_wake()
603 static void ath10k_pci_sleep(struct ath10k *ar) in ath10k_pci_sleep() argument
605 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_sleep()
608 if (ar_pci->pci_ps == 0) in ath10k_pci_sleep()
611 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_sleep()
613 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n", in ath10k_pci_sleep()
614 ar_pci->ps_wake_refcount, ar_pci->ps_awake); in ath10k_pci_sleep()
616 if (WARN_ON(ar_pci->ps_wake_refcount == 0)) in ath10k_pci_sleep()
619 ar_pci->ps_wake_refcount--; in ath10k_pci_sleep()
621 mod_timer(&ar_pci->ps_timer, jiffies + in ath10k_pci_sleep()
625 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_sleep()
631 struct ath10k *ar = ar_pci->ar; in ath10k_pci_ps_timer() local
634 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_ps_timer()
636 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n", in ath10k_pci_ps_timer()
637 ar_pci->ps_wake_refcount, ar_pci->ps_awake); in ath10k_pci_ps_timer()
639 if (ar_pci->ps_wake_refcount > 0) in ath10k_pci_ps_timer()
642 __ath10k_pci_sleep(ar); in ath10k_pci_ps_timer()
645 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_ps_timer()
648 static void ath10k_pci_sleep_sync(struct ath10k *ar) in ath10k_pci_sleep_sync() argument
650 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_sleep_sync()
653 if (ar_pci->pci_ps == 0) { in ath10k_pci_sleep_sync()
654 ath10k_pci_force_sleep(ar); in ath10k_pci_sleep_sync()
658 del_timer_sync(&ar_pci->ps_timer); in ath10k_pci_sleep_sync()
660 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_sleep_sync()
661 WARN_ON(ar_pci->ps_wake_refcount > 0); in ath10k_pci_sleep_sync()
662 __ath10k_pci_sleep(ar); in ath10k_pci_sleep_sync()
663 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_sleep_sync()
666 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value) in ath10k_bus_pci_write32() argument
668 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_bus_pci_write32()
671 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { in ath10k_bus_pci_write32()
672 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", in ath10k_bus_pci_write32()
673 offset, offset + sizeof(value), ar_pci->mem_len); in ath10k_bus_pci_write32()
677 ret = ath10k_pci_wake(ar); in ath10k_bus_pci_write32()
679 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n", in ath10k_bus_pci_write32()
685 iowrite32(value, ar_pci->mem + offset); in ath10k_bus_pci_write32()
687 bus_write_4((struct resource *)ar_pci->mem, offset, value); in ath10k_bus_pci_write32()
689 ath10k_pci_sleep(ar); in ath10k_bus_pci_write32()
692 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) in ath10k_bus_pci_read32() argument
694 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_bus_pci_read32()
698 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { in ath10k_bus_pci_read32()
699 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", in ath10k_bus_pci_read32()
700 offset, offset + sizeof(val), ar_pci->mem_len); in ath10k_bus_pci_read32()
704 ret = ath10k_pci_wake(ar); in ath10k_bus_pci_read32()
706 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n", in ath10k_bus_pci_read32()
712 val = ioread32(ar_pci->mem + offset); in ath10k_bus_pci_read32()
714 val = bus_read_4((struct resource *)ar_pci->mem, offset); in ath10k_bus_pci_read32()
716 ath10k_pci_sleep(ar); in ath10k_bus_pci_read32()
721 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) in ath10k_pci_write32() argument
723 struct ath10k_ce *ce = ath10k_ce_priv(ar); in ath10k_pci_write32()
725 ce->bus_ops->write32(ar, offset, value); in ath10k_pci_write32()
728 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) in ath10k_pci_read32() argument
730 struct ath10k_ce *ce = ath10k_ce_priv(ar); in ath10k_pci_read32()
732 return ce->bus_ops->read32(ar, offset); in ath10k_pci_read32()
735 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) in ath10k_pci_soc_read32() argument
737 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); in ath10k_pci_soc_read32()
740 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) in ath10k_pci_soc_write32() argument
742 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); in ath10k_pci_soc_write32()
745 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) in ath10k_pci_reg_read32() argument
747 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr); in ath10k_pci_reg_read32()
750 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) in ath10k_pci_reg_write32() argument
752 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); in ath10k_pci_reg_write32()
755 bool ath10k_pci_irq_pending(struct ath10k *ar) in ath10k_pci_irq_pending() argument
760 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + in ath10k_pci_irq_pending()
768 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) in ath10k_pci_disable_and_clear_legacy_irq() argument
774 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, in ath10k_pci_disable_and_clear_legacy_irq()
776 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, in ath10k_pci_disable_and_clear_legacy_irq()
782 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + in ath10k_pci_disable_and_clear_legacy_irq()
786 void ath10k_pci_enable_legacy_irq(struct ath10k *ar) in ath10k_pci_enable_legacy_irq() argument
788 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + in ath10k_pci_enable_legacy_irq()
795 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + in ath10k_pci_enable_legacy_irq()
799 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) in ath10k_pci_get_irq_method() argument
801 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_get_irq_method()
803 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI) in ath10k_pci_get_irq_method()
811 struct ath10k *ar = pipe->hif_ce_state; in __ath10k_pci_rx_post_buf() local
812 struct ath10k_ce *ce = ath10k_ce_priv(ar); in __ath10k_pci_rx_post_buf()
813 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; in __ath10k_pci_rx_post_buf()
818 skb = dev_alloc_skb(pipe->buf_sz); in __ath10k_pci_rx_post_buf()
820 return -ENOMEM; in __ath10k_pci_rx_post_buf()
822 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); in __ath10k_pci_rx_post_buf()
824 paddr = dma_map_single(ar->dev, skb->data, in __ath10k_pci_rx_post_buf()
825 skb->len + skb_tailroom(skb), in __ath10k_pci_rx_post_buf()
827 if (unlikely(dma_mapping_error(ar->dev, paddr))) { in __ath10k_pci_rx_post_buf()
828 ath10k_warn(ar, "failed to dma map pci rx buf\n"); in __ath10k_pci_rx_post_buf()
830 return -EIO; in __ath10k_pci_rx_post_buf()
833 ATH10K_SKB_RXCB(skb)->paddr = paddr; in __ath10k_pci_rx_post_buf()
835 spin_lock_bh(&ce->ce_lock); in __ath10k_pci_rx_post_buf()
836 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr); in __ath10k_pci_rx_post_buf()
837 spin_unlock_bh(&ce->ce_lock); in __ath10k_pci_rx_post_buf()
839 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), in __ath10k_pci_rx_post_buf()
850 struct ath10k *ar = pipe->hif_ce_state; in ath10k_pci_rx_post_pipe() local
851 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_rx_post_pipe()
852 struct ath10k_ce *ce = ath10k_ce_priv(ar); in ath10k_pci_rx_post_pipe()
853 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; in ath10k_pci_rx_post_pipe()
856 if (pipe->buf_sz == 0) in ath10k_pci_rx_post_pipe()
859 if (!ce_pipe->dest_ring) in ath10k_pci_rx_post_pipe()
862 spin_lock_bh(&ce->ce_lock); in ath10k_pci_rx_post_pipe()
864 spin_unlock_bh(&ce->ce_lock); in ath10k_pci_rx_post_pipe()
869 if (ret == -ENOSPC) in ath10k_pci_rx_post_pipe()
871 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); in ath10k_pci_rx_post_pipe()
872 mod_timer(&ar_pci->rx_post_retry, jiffies + in ath10k_pci_rx_post_pipe()
876 num--; in ath10k_pci_rx_post_pipe()
880 void ath10k_pci_rx_post(struct ath10k *ar) in ath10k_pci_rx_post() argument
882 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_rx_post()
886 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); in ath10k_pci_rx_post()
892 struct ath10k *ar = ar_pci->ar; in ath10k_pci_rx_replenish_retry() local
894 ath10k_pci_rx_post(ar); in ath10k_pci_rx_replenish_retry()
897 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) in ath10k_pci_qca988x_targ_cpu_to_ce_addr() argument
901 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) in ath10k_pci_qca988x_targ_cpu_to_ce_addr()
912 static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) in ath10k_pci_qca6174_targ_cpu_to_ce_addr() argument
916 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) in ath10k_pci_qca6174_targ_cpu_to_ce_addr()
922 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) in ath10k_pci_qca99x0_targ_cpu_to_ce_addr() argument
926 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); in ath10k_pci_qca99x0_targ_cpu_to_ce_addr()
931 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) in ath10k_pci_targ_cpu_to_ce_addr() argument
933 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_targ_cpu_to_ce_addr()
935 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr)) in ath10k_pci_targ_cpu_to_ce_addr()
936 return -ENOTSUPP; in ath10k_pci_targ_cpu_to_ce_addr()
938 return ar_pci->targ_cpu_to_ce_addr(ar, addr); in ath10k_pci_targ_cpu_to_ce_addr()
947 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, in ath10k_pci_diag_read_mem() argument
949 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, u8 *data, in ath10k_pci_diag_read_mem()
953 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_diag_read_mem()
964 mutex_lock(&ar_pci->ce_diag_mutex); in ath10k_pci_diag_read_mem()
965 ce_diag = ar_pci->ce_diag; in ath10k_pci_diag_read_mem()
970 * 1) 4-byte alignment in ath10k_pci_diag_read_mem()
971 * 2) Buffer in DMA-able space in ath10k_pci_diag_read_mem()
975 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, in ath10k_pci_diag_read_mem()
978 ret = -ENOMEM; in ath10k_pci_diag_read_mem()
989 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); in ath10k_pci_diag_read_mem()
1012 ret = -EBUSY; in ath10k_pci_diag_read_mem()
1024 ret = -EBUSY; in ath10k_pci_diag_read_mem()
1030 ret = -EIO; in ath10k_pci_diag_read_mem()
1035 ret = -EIO; in ath10k_pci_diag_read_mem()
1039 remaining_bytes -= nbytes; in ath10k_pci_diag_read_mem()
1049 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, in ath10k_pci_diag_read_mem()
1052 mutex_unlock(&ar_pci->ce_diag_mutex); in ath10k_pci_diag_read_mem()
1057 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) in ath10k_pci_diag_read32() argument
1063 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); in ath10k_pci_diag_read32()
1065 ret = ath10k_pci_diag_read_mem(ar, address, (u8 *)&val, sizeof(val)); in ath10k_pci_diag_read32()
1072 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, in __ath10k_pci_diag_read_hi() argument
1080 ret = ath10k_pci_diag_read32(ar, host_addr, &addr); in __ath10k_pci_diag_read_hi()
1082 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", in __ath10k_pci_diag_read_hi()
1087 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); in __ath10k_pci_diag_read_hi()
1089 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", in __ath10k_pci_diag_read_hi()
1097 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ argument
1098 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1100 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, in ath10k_pci_diag_write_mem() argument
1107 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_diag_write_mem()
1119 mutex_lock(&ar_pci->ce_diag_mutex); in ath10k_pci_diag_write_mem()
1120 ce_diag = ar_pci->ce_diag; in ath10k_pci_diag_write_mem()
1125 * 1) 4-byte alignment in ath10k_pci_diag_write_mem()
1126 * 2) Buffer in DMA-able space in ath10k_pci_diag_write_mem()
1130 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, in ath10k_pci_diag_write_mem()
1133 ret = -ENOMEM; in ath10k_pci_diag_write_mem()
1147 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); in ath10k_pci_diag_write_mem()
1163 * Request CE to send caller-supplied data that in ath10k_pci_diag_write_mem()
1176 ret = -EBUSY; in ath10k_pci_diag_write_mem()
1188 ret = -EBUSY; in ath10k_pci_diag_write_mem()
1194 ret = -EIO; in ath10k_pci_diag_write_mem()
1199 ret = -EIO; in ath10k_pci_diag_write_mem()
1203 remaining_bytes -= nbytes; in ath10k_pci_diag_write_mem()
1210 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, in ath10k_pci_diag_write_mem()
1215 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", in ath10k_pci_diag_write_mem()
1218 mutex_unlock(&ar_pci->ce_diag_mutex); in ath10k_pci_diag_write_mem()
1223 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) in ath10k_pci_diag_write32() argument
1227 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); in ath10k_pci_diag_write32()
1233 struct ath10k *ar = ce_state->ar; in ath10k_pci_htc_tx_cb() local
1247 ath10k_htc_tx_completion_handler(ar, skb); in ath10k_pci_htc_tx_cb()
1251 void (*callback)(struct ath10k *ar, in ath10k_pci_process_rx_cb() argument
1254 struct ath10k *ar = ce_state->ar; in ath10k_pci_process_rx_cb() local
1255 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_process_rx_cb()
1256 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; in ath10k_pci_process_rx_cb()
1266 max_nbytes = skb->len + skb_tailroom(skb); in ath10k_pci_process_rx_cb()
1267 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, in ath10k_pci_process_rx_cb()
1271 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", in ath10k_pci_process_rx_cb()
1282 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", in ath10k_pci_process_rx_cb()
1283 ce_state->id, skb->len); in ath10k_pci_process_rx_cb()
1284 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", in ath10k_pci_process_rx_cb()
1285 skb->data, skb->len); in ath10k_pci_process_rx_cb()
1287 callback(ar, skb); in ath10k_pci_process_rx_cb()
1294 void (*callback)(struct ath10k *ar, in ath10k_pci_process_htt_rx_cb() argument
1297 struct ath10k *ar = ce_state->ar; in ath10k_pci_process_htt_rx_cb() local
1298 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_process_htt_rx_cb()
1299 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; in ath10k_pci_process_htt_rx_cb()
1300 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl; in ath10k_pci_process_htt_rx_cb()
1315 max_nbytes = skb->len + skb_tailroom(skb); in ath10k_pci_process_htt_rx_cb()
1318 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", in ath10k_pci_process_htt_rx_cb()
1323 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, in ath10k_pci_process_htt_rx_cb()
1331 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", in ath10k_pci_process_htt_rx_cb()
1332 ce_state->id, skb->len); in ath10k_pci_process_htt_rx_cb()
1333 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", in ath10k_pci_process_htt_rx_cb()
1334 skb->data, skb->len); in ath10k_pci_process_htt_rx_cb()
1336 orig_len = skb->len; in ath10k_pci_process_htt_rx_cb()
1337 callback(ar, skb); in ath10k_pci_process_htt_rx_cb()
1338 skb_push(skb, orig_len - skb->len); in ath10k_pci_process_htt_rx_cb()
1343 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, in ath10k_pci_process_htt_rx_cb()
1344 skb->len + skb_tailroom(skb), in ath10k_pci_process_htt_rx_cb()
1359 * HTT Rx (target->host) is processed. in ath10k_pci_htt_htc_rx_cb()
1361 ath10k_ce_per_engine_service(ce_state->ar, 4); in ath10k_pci_htt_htc_rx_cb()
1378 struct ath10k *ar = ce_state->ar; in ath10k_pci_htt_tx_cb() local
1386 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, in ath10k_pci_htt_tx_cb()
1387 skb->len, DMA_TO_DEVICE); in ath10k_pci_htt_tx_cb()
1388 ath10k_htt_hif_tx_complete(ar, skb); in ath10k_pci_htt_tx_cb()
1392 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) in ath10k_pci_htt_rx_deliver() argument
1395 ath10k_htt_t2h_msg_handler(ar, skb); in ath10k_pci_htt_rx_deliver()
1402 * HTT Rx (target->host) is processed. in ath10k_pci_htt_rx_cb()
1404 ath10k_ce_per_engine_service(ce_state->ar, 4); in ath10k_pci_htt_rx_cb()
1409 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, in ath10k_pci_hif_tx_sg() argument
1412 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_hif_tx_sg()
1413 struct ath10k_ce *ce = ath10k_ce_priv(ar); in ath10k_pci_hif_tx_sg()
1414 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; in ath10k_pci_hif_tx_sg()
1415 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; in ath10k_pci_hif_tx_sg()
1416 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; in ath10k_pci_hif_tx_sg()
1422 spin_lock_bh(&ce->ce_lock); in ath10k_pci_hif_tx_sg()
1424 nentries_mask = src_ring->nentries_mask; in ath10k_pci_hif_tx_sg()
1425 sw_index = src_ring->sw_index; in ath10k_pci_hif_tx_sg()
1426 write_index = src_ring->write_index; in ath10k_pci_hif_tx_sg()
1429 write_index, sw_index - 1) < n_items)) { in ath10k_pci_hif_tx_sg()
1430 err = -ENOBUFS; in ath10k_pci_hif_tx_sg()
1434 for (i = 0; i < n_items - 1; i++) { in ath10k_pci_hif_tx_sg()
1435 ath10k_dbg(ar, ATH10K_DBG_PCI, in ath10k_pci_hif_tx_sg()
1438 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", in ath10k_pci_hif_tx_sg()
1451 /* `i` is equal to `n_items -1` after for() */ in ath10k_pci_hif_tx_sg()
1453 ath10k_dbg(ar, ATH10K_DBG_PCI, in ath10k_pci_hif_tx_sg()
1461 * XXX-BZ specific debug; the DELAY makes things work for one chipset. in ath10k_pci_hif_tx_sg()
1465 ath10k_dbg_dump(ar, ATH10K_DBG_PCI, NULL, "pci tx data: ", in ath10k_pci_hif_tx_sg()
1471 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", in ath10k_pci_hif_tx_sg()
1483 spin_unlock_bh(&ce->ce_lock); in ath10k_pci_hif_tx_sg()
1487 for (; i > 0; i--) in ath10k_pci_hif_tx_sg()
1490 spin_unlock_bh(&ce->ce_lock); in ath10k_pci_hif_tx_sg()
1494 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, in ath10k_pci_hif_diag_read() argument
1497 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); in ath10k_pci_hif_diag_read()
1500 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) in ath10k_pci_hif_get_free_queue_number() argument
1502 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_hif_get_free_queue_number()
1504 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); in ath10k_pci_hif_get_free_queue_number()
1506 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); in ath10k_pci_hif_get_free_queue_number()
1509 static void ath10k_pci_dump_registers(struct ath10k *ar, in ath10k_pci_dump_registers() argument
1515 lockdep_assert_held(&ar->dump_mutex); in ath10k_pci_dump_registers()
1517 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], in ath10k_pci_dump_registers()
1521 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); in ath10k_pci_dump_registers()
1527 ath10k_err(ar, "firmware register dump:\n"); in ath10k_pci_dump_registers()
1529 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", in ath10k_pci_dump_registers()
1540 crash_data->registers[i] = reg_dump_values[i]; in ath10k_pci_dump_registers()
1543 static int ath10k_pci_dump_memory_section(struct ath10k *ar, in ath10k_pci_dump_memory_section() argument
1554 cur_section = &mem_region->section_table.sections[0]; in ath10k_pci_dump_memory_section()
1556 if (mem_region->start > cur_section->start) { in ath10k_pci_dump_memory_section()
1557 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n", in ath10k_pci_dump_memory_section()
1558 mem_region->start, cur_section->start); in ath10k_pci_dump_memory_section()
1562 skip_size = cur_section->start - mem_region->start; in ath10k_pci_dump_memory_section()
1575 section_size = cur_section->end - cur_section->start; in ath10k_pci_dump_memory_section()
1578 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n", in ath10k_pci_dump_memory_section()
1579 cur_section->start, in ath10k_pci_dump_memory_section()
1580 cur_section->end); in ath10k_pci_dump_memory_section()
1584 if ((i + 1) == mem_region->section_table.size) { in ath10k_pci_dump_memory_section()
1591 if (cur_section->end > next_section->start) { in ath10k_pci_dump_memory_section()
1592 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n", in ath10k_pci_dump_memory_section()
1593 next_section->start, in ath10k_pci_dump_memory_section()
1594 cur_section->end); in ath10k_pci_dump_memory_section()
1598 skip_size = next_section->start - cur_section->end; in ath10k_pci_dump_memory_section()
1602 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len); in ath10k_pci_dump_memory_section()
1606 buf_len -= skip_size + section_size; in ath10k_pci_dump_memory_section()
1609 ret = ath10k_pci_diag_read_mem(ar, cur_section->start, in ath10k_pci_dump_memory_section()
1612 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n", in ath10k_pci_dump_memory_section()
1613 cur_section->start, ret); in ath10k_pci_dump_memory_section()
1638 static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config) in ath10k_pci_set_ram_config() argument
1642 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + in ath10k_pci_set_ram_config()
1645 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + in ath10k_pci_set_ram_config()
1648 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n", in ath10k_pci_set_ram_config()
1650 return -EIO; in ath10k_pci_set_ram_config()
1657 static int ath10k_pci_dump_memory_sram(struct ath10k *ar, in ath10k_pci_dump_memory_sram() argument
1661 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_dump_memory_sram()
1665 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG); in ath10k_pci_dump_memory_sram()
1667 base_addr = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_PCIE_BAR0_START_REG); in ath10k_pci_dump_memory_sram()
1669 base_addr += region->start; in ath10k_pci_dump_memory_sram()
1671 for (i = 0; i < region->len; i += 4) { in ath10k_pci_dump_memory_sram()
1673 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG); in ath10k_pci_dump_memory_sram()
1674 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG); in ath10k_pci_dump_memory_sram()
1676 bus_write_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_ADDR_REG, base_addr + i); in ath10k_pci_dump_memory_sram()
1677 *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_DATA_REG); in ath10k_pci_dump_memory_sram()
1681 return region->len; in ath10k_pci_dump_memory_sram()
1685 static int ath10k_pci_dump_memory_reg(struct ath10k *ar, in ath10k_pci_dump_memory_reg() argument
1689 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_dump_memory_reg()
1693 mutex_lock(&ar->conf_mutex); in ath10k_pci_dump_memory_reg()
1694 if (ar->state != ATH10K_STATE_ON) { in ath10k_pci_dump_memory_reg()
1695 ath10k_warn(ar, "Skipping pci_dump_memory_reg invalid state\n"); in ath10k_pci_dump_memory_reg()
1696 ret = -EIO; in ath10k_pci_dump_memory_reg()
1700 for (i = 0; i < region->len; i += 4) in ath10k_pci_dump_memory_reg()
1702 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i); in ath10k_pci_dump_memory_reg()
1704 *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, region->start + i); in ath10k_pci_dump_memory_reg()
1707 ret = region->len; in ath10k_pci_dump_memory_reg()
1709 mutex_unlock(&ar->conf_mutex); in ath10k_pci_dump_memory_reg()
1714 static int ath10k_pci_dump_memory_generic(struct ath10k *ar, in ath10k_pci_dump_memory_generic() argument
1720 if (current_region->section_table.size > 0) in ath10k_pci_dump_memory_generic()
1722 return ath10k_pci_dump_memory_section(ar, in ath10k_pci_dump_memory_generic()
1725 current_region->len); in ath10k_pci_dump_memory_generic()
1730 ret = ath10k_pci_diag_read_mem(ar, in ath10k_pci_dump_memory_generic()
1731 current_region->start, in ath10k_pci_dump_memory_generic()
1733 current_region->len); in ath10k_pci_dump_memory_generic()
1735 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n", in ath10k_pci_dump_memory_generic()
1736 current_region->name, ret); in ath10k_pci_dump_memory_generic()
1740 return current_region->len; in ath10k_pci_dump_memory_generic()
1743 static void ath10k_pci_dump_memory(struct ath10k *ar, in ath10k_pci_dump_memory() argument
1754 lockdep_assert_held(&ar->dump_mutex); in ath10k_pci_dump_memory()
1759 mem_layout = ath10k_coredump_get_mem_layout(ar); in ath10k_pci_dump_memory()
1763 current_region = &mem_layout->region_table.regions[0]; in ath10k_pci_dump_memory()
1765 buf = crash_data->ramdump_buf; in ath10k_pci_dump_memory()
1766 buf_len = crash_data->ramdump_buf_len; in ath10k_pci_dump_memory()
1770 for (i = 0; i < mem_layout->region_table.size; i++) { in ath10k_pci_dump_memory()
1773 if (current_region->len > buf_len) { in ath10k_pci_dump_memory()
1774 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n", in ath10k_pci_dump_memory()
1775 current_region->name, in ath10k_pci_dump_memory()
1776 current_region->len, in ath10k_pci_dump_memory()
1784 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 || in ath10k_pci_dump_memory()
1785 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) { in ath10k_pci_dump_memory()
1786 shift = current_region->start >> 20; in ath10k_pci_dump_memory()
1788 ret = ath10k_pci_set_ram_config(ar, shift); in ath10k_pci_dump_memory()
1790 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n", in ath10k_pci_dump_memory()
1791 current_region->name, ret); in ath10k_pci_dump_memory()
1799 buf_len -= sizeof(*hdr); in ath10k_pci_dump_memory()
1801 switch (current_region->type) { in ath10k_pci_dump_memory()
1803 count = ath10k_pci_dump_memory_sram(ar, current_region, buf); in ath10k_pci_dump_memory()
1806 ret = ath10k_pci_dump_memory_reg(ar, current_region, buf); in ath10k_pci_dump_memory()
1813 ret = ath10k_pci_dump_memory_generic(ar, current_region, buf); in ath10k_pci_dump_memory()
1821 hdr->region_type = cpu_to_le32(current_region->type); in ath10k_pci_dump_memory()
1822 hdr->start = cpu_to_le32(current_region->start); in ath10k_pci_dump_memory()
1823 hdr->length = cpu_to_le32(count); in ath10k_pci_dump_memory()
1830 buf_len -= count; in ath10k_pci_dump_memory()
1841 struct ath10k *ar = ar_pci->ar; in ath10k_pci_fw_dump_work() local
1844 mutex_lock(&ar->dump_mutex); in ath10k_pci_fw_dump_work()
1846 spin_lock_bh(&ar->data_lock); in ath10k_pci_fw_dump_work()
1847 ar->stats.fw_crash_counter++; in ath10k_pci_fw_dump_work()
1848 spin_unlock_bh(&ar->data_lock); in ath10k_pci_fw_dump_work()
1850 crash_data = ath10k_coredump_new(ar); in ath10k_pci_fw_dump_work()
1853 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); in ath10k_pci_fw_dump_work()
1857 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid); in ath10k_pci_fw_dump_work()
1858 ath10k_print_driver_info(ar); in ath10k_pci_fw_dump_work()
1859 ath10k_pci_dump_registers(ar, crash_data); in ath10k_pci_fw_dump_work()
1860 ath10k_ce_dump_registers(ar, crash_data); in ath10k_pci_fw_dump_work()
1861 ath10k_pci_dump_memory(ar, crash_data); in ath10k_pci_fw_dump_work()
1863 mutex_unlock(&ar->dump_mutex); in ath10k_pci_fw_dump_work()
1865 ath10k_core_start_recovery(ar); in ath10k_pci_fw_dump_work()
1868 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) in ath10k_pci_fw_crashed_dump() argument
1870 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_fw_crashed_dump()
1872 queue_work(ar->workqueue, &ar_pci->dump_work); in ath10k_pci_fw_crashed_dump()
1875 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, in ath10k_pci_hif_send_complete_check() argument
1878 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_hif_send_complete_check()
1880 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); in ath10k_pci_hif_send_complete_check()
1891 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); in ath10k_pci_hif_send_complete_check()
1897 if (resources > (ar_pci->attr[pipe].src_nentries >> 1)) in ath10k_pci_hif_send_complete_check()
1900 ath10k_ce_per_engine_service(ar, pipe); in ath10k_pci_hif_send_complete_check()
1903 static void ath10k_pci_rx_retry_sync(struct ath10k *ar) in ath10k_pci_rx_retry_sync() argument
1905 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_rx_retry_sync()
1907 del_timer_sync(&ar_pci->rx_post_retry); in ath10k_pci_rx_retry_sync()
1910 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, in ath10k_pci_hif_map_service_to_pipe() argument
1913 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_hif_map_service_to_pipe()
1918 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); in ath10k_pci_hif_map_service_to_pipe()
1921 entry = &ar_pci->serv_to_pipe[i]; in ath10k_pci_hif_map_service_to_pipe()
1923 if (__le32_to_cpu(entry->service_id) != service_id) in ath10k_pci_hif_map_service_to_pipe()
1926 switch (__le32_to_cpu(entry->pipedir)) { in ath10k_pci_hif_map_service_to_pipe()
1931 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath10k_pci_hif_map_service_to_pipe()
1936 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath10k_pci_hif_map_service_to_pipe()
1942 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath10k_pci_hif_map_service_to_pipe()
1943 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath10k_pci_hif_map_service_to_pipe()
1951 return -ENOENT; in ath10k_pci_hif_map_service_to_pipe()
1956 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, in ath10k_pci_hif_get_default_pipe() argument
1959 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); in ath10k_pci_hif_get_default_pipe()
1961 (void)ath10k_pci_hif_map_service_to_pipe(ar, in ath10k_pci_hif_get_default_pipe()
1966 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) in ath10k_pci_irq_msi_fw_mask() argument
1970 switch (ar->hw_rev) { in ath10k_pci_irq_msi_fw_mask()
1975 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + in ath10k_pci_irq_msi_fw_mask()
1978 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + in ath10k_pci_irq_msi_fw_mask()
1994 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) in ath10k_pci_irq_msi_fw_unmask() argument
1998 switch (ar->hw_rev) { in ath10k_pci_irq_msi_fw_unmask()
2003 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + in ath10k_pci_irq_msi_fw_unmask()
2006 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + in ath10k_pci_irq_msi_fw_unmask()
2022 static void ath10k_pci_irq_disable(struct ath10k *ar) in ath10k_pci_irq_disable() argument
2024 ath10k_ce_disable_interrupts(ar); in ath10k_pci_irq_disable()
2025 ath10k_pci_disable_and_clear_legacy_irq(ar); in ath10k_pci_irq_disable()
2026 ath10k_pci_irq_msi_fw_mask(ar); in ath10k_pci_irq_disable()
2029 static void ath10k_pci_irq_sync(struct ath10k *ar) in ath10k_pci_irq_sync() argument
2031 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_irq_sync()
2033 synchronize_irq(ar_pci->pdev->irq); in ath10k_pci_irq_sync()
2036 static void ath10k_pci_irq_enable(struct ath10k *ar) in ath10k_pci_irq_enable() argument
2038 ath10k_ce_enable_interrupts(ar); in ath10k_pci_irq_enable()
2039 ath10k_pci_enable_legacy_irq(ar); in ath10k_pci_irq_enable()
2040 ath10k_pci_irq_msi_fw_unmask(ar); in ath10k_pci_irq_enable()
2043 static int ath10k_pci_hif_start(struct ath10k *ar) in ath10k_pci_hif_start() argument
2045 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_hif_start()
2047 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); in ath10k_pci_hif_start()
2049 ath10k_core_napi_enable(ar); in ath10k_pci_hif_start()
2051 ath10k_pci_irq_enable(ar); in ath10k_pci_hif_start()
2052 ath10k_pci_rx_post(ar); in ath10k_pci_hif_start()
2054 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, in ath10k_pci_hif_start()
2055 ar_pci->link_ctl); in ath10k_pci_hif_start()
2062 struct ath10k *ar; in ath10k_pci_rx_pipe_cleanup() local
2068 ar = pci_pipe->hif_ce_state; in ath10k_pci_rx_pipe_cleanup()
2069 ce_pipe = pci_pipe->ce_hdl; in ath10k_pci_rx_pipe_cleanup()
2070 ce_ring = ce_pipe->dest_ring; in ath10k_pci_rx_pipe_cleanup()
2075 if (!pci_pipe->buf_sz) in ath10k_pci_rx_pipe_cleanup()
2078 for (i = 0; i < ce_ring->nentries; i++) { in ath10k_pci_rx_pipe_cleanup()
2079 skb = ce_ring->per_transfer_context[i]; in ath10k_pci_rx_pipe_cleanup()
2083 ce_ring->per_transfer_context[i] = NULL; in ath10k_pci_rx_pipe_cleanup()
2085 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, in ath10k_pci_rx_pipe_cleanup()
2086 skb->len + skb_tailroom(skb), in ath10k_pci_rx_pipe_cleanup()
2094 struct ath10k *ar; in ath10k_pci_tx_pipe_cleanup() local
2100 ar = pci_pipe->hif_ce_state; in ath10k_pci_tx_pipe_cleanup()
2101 ce_pipe = pci_pipe->ce_hdl; in ath10k_pci_tx_pipe_cleanup()
2102 ce_ring = ce_pipe->src_ring; in ath10k_pci_tx_pipe_cleanup()
2107 if (!pci_pipe->buf_sz) in ath10k_pci_tx_pipe_cleanup()
2110 for (i = 0; i < ce_ring->nentries; i++) { in ath10k_pci_tx_pipe_cleanup()
2111 skb = ce_ring->per_transfer_context[i]; in ath10k_pci_tx_pipe_cleanup()
2115 ce_ring->per_transfer_context[i] = NULL; in ath10k_pci_tx_pipe_cleanup()
2117 ath10k_htc_tx_completion_handler(ar, skb); in ath10k_pci_tx_pipe_cleanup()
2129 static void ath10k_pci_buffer_cleanup(struct ath10k *ar) in ath10k_pci_buffer_cleanup() argument
2131 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_buffer_cleanup()
2137 pipe_info = &ar_pci->pipe_info[pipe_num]; in ath10k_pci_buffer_cleanup()
2143 void ath10k_pci_ce_deinit(struct ath10k *ar) in ath10k_pci_ce_deinit() argument
2148 ath10k_ce_deinit_pipe(ar, i); in ath10k_pci_ce_deinit()
2151 void ath10k_pci_flush(struct ath10k *ar) in ath10k_pci_flush() argument
2153 ath10k_pci_rx_retry_sync(ar); in ath10k_pci_flush()
2154 ath10k_pci_buffer_cleanup(ar); in ath10k_pci_flush()
2157 static void ath10k_pci_hif_stop(struct ath10k *ar) in ath10k_pci_hif_stop() argument
2159 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_hif_stop()
2162 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); in ath10k_pci_hif_stop()
2164 ath10k_pci_irq_disable(ar); in ath10k_pci_hif_stop()
2165 ath10k_pci_irq_sync(ar); in ath10k_pci_hif_stop()
2167 ath10k_core_napi_sync_disable(ar); in ath10k_pci_hif_stop()
2169 cancel_work_sync(&ar_pci->dump_work); in ath10k_pci_hif_stop()
2176 * For ranged MSI the CE-related interrupts can be masked. However in ath10k_pci_hif_stop()
2182 ath10k_pci_safe_chip_reset(ar); in ath10k_pci_hif_stop()
2184 ath10k_pci_flush(ar); in ath10k_pci_hif_stop()
2186 spin_lock_irqsave(&ar_pci->ps_lock, flags); in ath10k_pci_hif_stop()
2187 WARN_ON(ar_pci->ps_wake_refcount > 0); in ath10k_pci_hif_stop()
2188 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); in ath10k_pci_hif_stop()
2191 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, in ath10k_pci_hif_exchange_bmi_msg() argument
2195 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_hif_exchange_bmi_msg()
2196 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; in ath10k_pci_hif_exchange_bmi_msg()
2197 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; in ath10k_pci_hif_exchange_bmi_msg()
2198 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; in ath10k_pci_hif_exchange_bmi_msg()
2199 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; in ath10k_pci_hif_exchange_bmi_msg()
2209 return -EINVAL; in ath10k_pci_hif_exchange_bmi_msg()
2212 return -EINVAL; in ath10k_pci_hif_exchange_bmi_msg()
2216 return -ENOMEM; in ath10k_pci_hif_exchange_bmi_msg()
2218 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); in ath10k_pci_hif_exchange_bmi_msg()
2219 ret = dma_mapping_error(ar->dev, req_paddr); in ath10k_pci_hif_exchange_bmi_msg()
2221 ret = -EIO; in ath10k_pci_hif_exchange_bmi_msg()
2228 ret = -ENOMEM; in ath10k_pci_hif_exchange_bmi_msg()
2232 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, in ath10k_pci_hif_exchange_bmi_msg()
2234 ret = dma_mapping_error(ar->dev, resp_paddr); in ath10k_pci_hif_exchange_bmi_msg()
2236 ret = -EIO; in ath10k_pci_hif_exchange_bmi_msg()
2246 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); in ath10k_pci_hif_exchange_bmi_msg()
2250 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer); in ath10k_pci_hif_exchange_bmi_msg()
2259 /* non-zero means we did not time out */ in ath10k_pci_hif_exchange_bmi_msg()
2268 dma_unmap_single(ar->dev, resp_paddr, in ath10k_pci_hif_exchange_bmi_msg()
2272 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); in ath10k_pci_hif_exchange_bmi_msg()
2292 xfer->tx_done = true; in ath10k_pci_bmi_send_done()
2297 struct ath10k *ar = ce_state->ar; in ath10k_pci_bmi_recv_data() local
2308 if (!xfer->wait_for_resp) { in ath10k_pci_bmi_recv_data()
2309 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); in ath10k_pci_bmi_recv_data()
2313 xfer->resp_len = nbytes; in ath10k_pci_bmi_recv_data()
2314 xfer->rx_done = true; in ath10k_pci_bmi_recv_data()
2317 static int ath10k_pci_bmi_wait(struct ath10k *ar, in ath10k_pci_bmi_wait() argument
2331 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) { in ath10k_pci_bmi_wait()
2339 /* Using LinuxKPI we'll hang for-ever as there's no wake_up */ in ath10k_pci_bmi_wait()
2344 ret = -ETIMEDOUT; in ath10k_pci_bmi_wait()
2347 dur = jiffies - started; in ath10k_pci_bmi_wait()
2349 ath10k_dbg(ar, ATH10K_DBG_BMI, in ath10k_pci_bmi_wait()
2359 static int ath10k_pci_wake_target_cpu(struct ath10k *ar) in ath10k_pci_wake_target_cpu() argument
2364 val = ath10k_pci_read32(ar, addr); in ath10k_pci_wake_target_cpu()
2366 ath10k_pci_write32(ar, addr, val); in ath10k_pci_wake_target_cpu()
2371 static int ath10k_pci_get_num_banks(struct ath10k *ar) in ath10k_pci_get_num_banks() argument
2373 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_get_num_banks()
2375 switch (ar_pci->pdev->device) { in ath10k_pci_get_num_banks()
2385 switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) { in ath10k_pci_get_num_banks()
2403 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); in ath10k_pci_get_num_banks()
2407 static int ath10k_bus_get_num_banks(struct ath10k *ar) in ath10k_bus_get_num_banks() argument
2409 struct ath10k_ce *ce = ath10k_ce_priv(ar); in ath10k_bus_get_num_banks()
2411 return ce->bus_ops->get_num_banks(ar); in ath10k_bus_get_num_banks()
2414 int ath10k_pci_init_config(struct ath10k *ar) in ath10k_pci_init_config() argument
2416 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_init_config()
2428 /* Download to Target the CE Config and the service-to-CE map */ in ath10k_pci_init_config()
2432 /* Supply Target-side CE configuration */ in ath10k_pci_init_config()
2433 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, in ath10k_pci_init_config()
2436 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); in ath10k_pci_init_config()
2441 ret = -EIO; in ath10k_pci_init_config()
2442 ath10k_err(ar, "Invalid pcie state addr\n"); in ath10k_pci_init_config()
2446 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + in ath10k_pci_init_config()
2451 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); in ath10k_pci_init_config()
2456 ret = -EIO; in ath10k_pci_init_config()
2457 ath10k_err(ar, "Invalid pipe cfg addr\n"); in ath10k_pci_init_config()
2461 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, in ath10k_pci_init_config()
2462 ar_pci->pipe_config, in ath10k_pci_init_config()
2467 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); in ath10k_pci_init_config()
2471 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + in ath10k_pci_init_config()
2476 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); in ath10k_pci_init_config()
2481 ret = -EIO; in ath10k_pci_init_config()
2482 ath10k_err(ar, "Invalid svc_to_pipe map\n"); in ath10k_pci_init_config()
2486 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, in ath10k_pci_init_config()
2487 ar_pci->serv_to_pipe, in ath10k_pci_init_config()
2490 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); in ath10k_pci_init_config()
2494 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + in ath10k_pci_init_config()
2499 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); in ath10k_pci_init_config()
2505 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + in ath10k_pci_init_config()
2510 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); in ath10k_pci_init_config()
2517 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); in ath10k_pci_init_config()
2519 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret); in ath10k_pci_init_config()
2526 ealloc_value |= ((ath10k_bus_get_num_banks(ar) << in ath10k_pci_init_config()
2530 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); in ath10k_pci_init_config()
2532 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); in ath10k_pci_init_config()
2539 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); in ath10k_pci_init_config()
2541 ath10k_err(ar, "Failed to get option val: %d\n", ret); in ath10k_pci_init_config()
2547 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); in ath10k_pci_init_config()
2549 ath10k_err(ar, "Failed to set option val: %d\n", ret); in ath10k_pci_init_config()
2556 static void ath10k_pci_override_ce_config(struct ath10k *ar) in ath10k_pci_override_ce_config() argument
2560 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_override_ce_config()
2567 attr = &ar_pci->attr[5]; in ath10k_pci_override_ce_config()
2568 attr->src_sz_max = 0; in ath10k_pci_override_ce_config()
2569 attr->dest_nentries = 0; in ath10k_pci_override_ce_config()
2572 config = &ar_pci->pipe_config[5]; in ath10k_pci_override_ce_config()
2573 config->pipedir = __cpu_to_le32(PIPEDIR_OUT); in ath10k_pci_override_ce_config()
2574 config->nbytes_max = __cpu_to_le32(2048); in ath10k_pci_override_ce_config()
2577 ar_pci->serv_to_pipe[15].pipenum = __cpu_to_le32(1); in ath10k_pci_override_ce_config()
2580 int ath10k_pci_alloc_pipes(struct ath10k *ar) in ath10k_pci_alloc_pipes() argument
2582 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_alloc_pipes()
2584 struct ath10k_ce *ce = ath10k_ce_priv(ar); in ath10k_pci_alloc_pipes()
2588 pipe = &ar_pci->pipe_info[i]; in ath10k_pci_alloc_pipes()
2589 pipe->ce_hdl = &ce->ce_states[i]; in ath10k_pci_alloc_pipes()
2590 pipe->pipe_num = i; in ath10k_pci_alloc_pipes()
2591 pipe->hif_ce_state = ar; in ath10k_pci_alloc_pipes()
2593 ret = ath10k_ce_alloc_pipe(ar, i, &ar_pci->attr[i]); in ath10k_pci_alloc_pipes()
2595 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", in ath10k_pci_alloc_pipes()
2602 ar_pci->ce_diag = pipe->ce_hdl; in ath10k_pci_alloc_pipes()
2606 pipe->buf_sz = (size_t)(ar_pci->attr[i].src_sz_max); in ath10k_pci_alloc_pipes()
2612 void ath10k_pci_free_pipes(struct ath10k *ar) in ath10k_pci_free_pipes() argument
2617 ath10k_ce_free_pipe(ar, i); in ath10k_pci_free_pipes()
2620 int ath10k_pci_init_pipes(struct ath10k *ar) in ath10k_pci_init_pipes() argument
2622 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_init_pipes()
2626 ret = ath10k_ce_init_pipe(ar, i, &ar_pci->attr[i]); in ath10k_pci_init_pipes()
2628 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", in ath10k_pci_init_pipes()
2637 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) in ath10k_pci_has_fw_crashed() argument
2639 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & in ath10k_pci_has_fw_crashed()
2643 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) in ath10k_pci_fw_crashed_clear() argument
2647 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); in ath10k_pci_fw_crashed_clear()
2649 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); in ath10k_pci_fw_crashed_clear()
2652 static bool ath10k_pci_has_device_gone(struct ath10k *ar) in ath10k_pci_has_device_gone() argument
2656 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); in ath10k_pci_has_device_gone()
2661 static void ath10k_pci_warm_reset_si0(struct ath10k *ar) in ath10k_pci_warm_reset_si0() argument
2665 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_si0()
2666 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_si0()
2668 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_si0()
2672 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_si0()
2673 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_si0()
2675 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_si0()
2680 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) in ath10k_pci_warm_reset_cpu() argument
2684 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); in ath10k_pci_warm_reset_cpu()
2686 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_cpu()
2687 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_cpu()
2691 static void ath10k_pci_warm_reset_ce(struct ath10k *ar) in ath10k_pci_warm_reset_ce() argument
2695 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_ce()
2697 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_ce()
2700 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_ce()
2704 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) in ath10k_pci_warm_reset_clear_lf() argument
2708 val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS); in ath10k_pci_warm_reset_clear_lf()
2709 ath10k_pci_soc_write32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS, in ath10k_pci_warm_reset_clear_lf()
2713 static int ath10k_pci_warm_reset(struct ath10k *ar) in ath10k_pci_warm_reset() argument
2717 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); in ath10k_pci_warm_reset()
2719 spin_lock_bh(&ar->data_lock); in ath10k_pci_warm_reset()
2720 ar->stats.fw_warm_reset_counter++; in ath10k_pci_warm_reset()
2721 spin_unlock_bh(&ar->data_lock); in ath10k_pci_warm_reset()
2723 ath10k_pci_irq_disable(ar); in ath10k_pci_warm_reset()
2727 * then it is possible for the device to confuse pci-e controller to in ath10k_pci_warm_reset()
2730 ath10k_pci_warm_reset_si0(ar); in ath10k_pci_warm_reset()
2731 ath10k_pci_warm_reset_cpu(ar); in ath10k_pci_warm_reset()
2732 ath10k_pci_init_pipes(ar); in ath10k_pci_warm_reset()
2733 ath10k_pci_wait_for_target_init(ar); in ath10k_pci_warm_reset()
2735 ath10k_pci_warm_reset_clear_lf(ar); in ath10k_pci_warm_reset()
2736 ath10k_pci_warm_reset_ce(ar); in ath10k_pci_warm_reset()
2737 ath10k_pci_warm_reset_cpu(ar); in ath10k_pci_warm_reset()
2738 ath10k_pci_init_pipes(ar); in ath10k_pci_warm_reset()
2740 ret = ath10k_pci_wait_for_target_init(ar); in ath10k_pci_warm_reset()
2742 ath10k_warn(ar, "failed to wait for target init: %d\n", ret); in ath10k_pci_warm_reset()
2746 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); in ath10k_pci_warm_reset()
2751 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) in ath10k_pci_qca99x0_soft_chip_reset() argument
2753 ath10k_pci_irq_disable(ar); in ath10k_pci_qca99x0_soft_chip_reset()
2754 return ath10k_pci_qca99x0_chip_reset(ar); in ath10k_pci_qca99x0_soft_chip_reset()
2757 static int ath10k_pci_safe_chip_reset(struct ath10k *ar) in ath10k_pci_safe_chip_reset() argument
2759 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_safe_chip_reset()
2761 if (!ar_pci->pci_soft_reset) in ath10k_pci_safe_chip_reset()
2762 return -ENOTSUPP; in ath10k_pci_safe_chip_reset()
2764 return ar_pci->pci_soft_reset(ar); in ath10k_pci_safe_chip_reset()
2767 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) in ath10k_pci_qca988x_chip_reset() argument
2772 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); in ath10k_pci_qca988x_chip_reset()
2782 ret = ath10k_pci_warm_reset(ar); in ath10k_pci_qca988x_chip_reset()
2784 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", in ath10k_pci_qca988x_chip_reset()
2799 ret = ath10k_pci_init_pipes(ar); in ath10k_pci_qca988x_chip_reset()
2801 ath10k_warn(ar, "failed to init copy engine: %d\n", in ath10k_pci_qca988x_chip_reset()
2806 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, in ath10k_pci_qca988x_chip_reset()
2809 ath10k_warn(ar, "failed to poke copy engine: %d\n", in ath10k_pci_qca988x_chip_reset()
2814 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); in ath10k_pci_qca988x_chip_reset()
2819 ath10k_warn(ar, "refusing cold reset as requested\n"); in ath10k_pci_qca988x_chip_reset()
2820 return -EPERM; in ath10k_pci_qca988x_chip_reset()
2823 ret = ath10k_pci_cold_reset(ar); in ath10k_pci_qca988x_chip_reset()
2825 ath10k_warn(ar, "failed to cold reset: %d\n", ret); in ath10k_pci_qca988x_chip_reset()
2829 ret = ath10k_pci_wait_for_target_init(ar); in ath10k_pci_qca988x_chip_reset()
2831 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", in ath10k_pci_qca988x_chip_reset()
2836 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); in ath10k_pci_qca988x_chip_reset()
2841 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) in ath10k_pci_qca6174_chip_reset() argument
2845 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); in ath10k_pci_qca6174_chip_reset()
2849 ret = ath10k_pci_cold_reset(ar); in ath10k_pci_qca6174_chip_reset()
2851 ath10k_warn(ar, "failed to cold reset: %d\n", ret); in ath10k_pci_qca6174_chip_reset()
2855 ret = ath10k_pci_wait_for_target_init(ar); in ath10k_pci_qca6174_chip_reset()
2857 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", in ath10k_pci_qca6174_chip_reset()
2862 ret = ath10k_pci_warm_reset(ar); in ath10k_pci_qca6174_chip_reset()
2864 ath10k_warn(ar, "failed to warm reset: %d\n", ret); in ath10k_pci_qca6174_chip_reset()
2868 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); in ath10k_pci_qca6174_chip_reset()
2873 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) in ath10k_pci_qca99x0_chip_reset() argument
2877 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n"); in ath10k_pci_qca99x0_chip_reset()
2879 ret = ath10k_pci_cold_reset(ar); in ath10k_pci_qca99x0_chip_reset()
2881 ath10k_warn(ar, "failed to cold reset: %d\n", ret); in ath10k_pci_qca99x0_chip_reset()
2885 ret = ath10k_pci_wait_for_target_init(ar); in ath10k_pci_qca99x0_chip_reset()
2887 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", in ath10k_pci_qca99x0_chip_reset()
2892 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n"); in ath10k_pci_qca99x0_chip_reset()
2897 static int ath10k_pci_chip_reset(struct ath10k *ar) in ath10k_pci_chip_reset() argument
2899 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_chip_reset()
2901 if (WARN_ON(!ar_pci->pci_hard_reset)) in ath10k_pci_chip_reset()
2902 return -ENOTSUPP; in ath10k_pci_chip_reset()
2904 return ar_pci->pci_hard_reset(ar); in ath10k_pci_chip_reset()
2907 static int ath10k_pci_hif_power_up(struct ath10k *ar, in ath10k_pci_hif_power_up() argument
2910 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_hif_power_up()
2913 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); in ath10k_pci_hif_power_up()
2915 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, in ath10k_pci_hif_power_up()
2916 &ar_pci->link_ctl); in ath10k_pci_hif_power_up()
2917 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, in ath10k_pci_hif_power_up()
2918 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); in ath10k_pci_hif_power_up()
2923 * The target may be in an undefined state with an AUX-powered Target in ath10k_pci_hif_power_up()
2930 ret = ath10k_pci_chip_reset(ar); in ath10k_pci_hif_power_up()
2932 if (ath10k_pci_has_fw_crashed(ar)) { in ath10k_pci_hif_power_up()
2933 ath10k_warn(ar, "firmware crashed during chip reset\n"); in ath10k_pci_hif_power_up()
2934 ath10k_pci_fw_crashed_clear(ar); in ath10k_pci_hif_power_up()
2935 ath10k_pci_fw_crashed_dump(ar); in ath10k_pci_hif_power_up()
2938 ath10k_err(ar, "failed to reset chip: %d\n", ret); in ath10k_pci_hif_power_up()
2942 ret = ath10k_pci_init_pipes(ar); in ath10k_pci_hif_power_up()
2944 ath10k_err(ar, "failed to initialize CE: %d\n", ret); in ath10k_pci_hif_power_up()
2948 ret = ath10k_pci_init_config(ar); in ath10k_pci_hif_power_up()
2950 ath10k_err(ar, "failed to setup init config: %d\n", ret); in ath10k_pci_hif_power_up()
2954 ret = ath10k_pci_wake_target_cpu(ar); in ath10k_pci_hif_power_up()
2956 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); in ath10k_pci_hif_power_up()
2963 ath10k_pci_ce_deinit(ar); in ath10k_pci_hif_power_up()
2969 void ath10k_pci_hif_power_down(struct ath10k *ar) in ath10k_pci_hif_power_down() argument
2971 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); in ath10k_pci_hif_power_down()
2978 static int ath10k_pci_hif_suspend(struct ath10k *ar) in ath10k_pci_hif_suspend() argument
2985 static int ath10k_pci_suspend(struct ath10k *ar) in ath10k_pci_suspend() argument
2987 /* The grace timer can still be counting down and ar->ps_awake be true. in ath10k_pci_suspend()
2992 ath10k_pci_sleep_sync(ar); in ath10k_pci_suspend()
2998 static int ath10k_pci_hif_resume(struct ath10k *ar) in ath10k_pci_hif_resume() argument
3005 static int ath10k_pci_resume(struct ath10k *ar) in ath10k_pci_resume() argument
3007 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_resume()
3008 struct pci_dev *pdev = ar_pci->pdev; in ath10k_pci_resume()
3012 ret = ath10k_pci_force_wake(ar); in ath10k_pci_resume()
3014 ath10k_err(ar, "failed to wake up target: %d\n", ret); in ath10k_pci_resume()
3019 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries in ath10k_pci_resume()
3046 static void ath10k_pci_enable_eeprom(struct ath10k *ar) in ath10k_pci_enable_eeprom() argument
3049 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0); in ath10k_pci_enable_eeprom()
3052 ath10k_pci_write32(ar, in ath10k_pci_enable_eeprom()
3059 ath10k_pci_write32(ar, in ath10k_pci_enable_eeprom()
3065 ath10k_pci_write32(ar, in ath10k_pci_enable_eeprom()
3070 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */ in ath10k_pci_enable_eeprom()
3071 ath10k_pci_write32(ar, in ath10k_pci_enable_eeprom()
3082 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out) in ath10k_pci_read_eeprom() argument
3091 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg); in ath10k_pci_read_eeprom()
3094 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, in ath10k_pci_read_eeprom()
3103 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET); in ath10k_pci_read_eeprom()
3107 wait_limit--; in ath10k_pci_read_eeprom()
3112 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n", in ath10k_pci_read_eeprom()
3114 return -ETIMEDOUT; in ath10k_pci_read_eeprom()
3118 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg); in ath10k_pci_read_eeprom()
3121 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr); in ath10k_pci_read_eeprom()
3122 return -EIO; in ath10k_pci_read_eeprom()
3126 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET); in ath10k_pci_read_eeprom()
3132 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data, in ath10k_pci_hif_fetch_cal_eeprom() argument
3139 if (!QCA_REV_9887(ar)) in ath10k_pci_hif_fetch_cal_eeprom()
3140 return -EOPNOTSUPP; in ath10k_pci_hif_fetch_cal_eeprom()
3142 calsize = ar->hw_params.cal_data_len; in ath10k_pci_hif_fetch_cal_eeprom()
3145 return -ENOMEM; in ath10k_pci_hif_fetch_cal_eeprom()
3147 ath10k_pci_enable_eeprom(ar); in ath10k_pci_hif_fetch_cal_eeprom()
3150 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]); in ath10k_pci_hif_fetch_cal_eeprom()
3166 return -EINVAL; in ath10k_pci_hif_fetch_cal_eeprom()
3190 * Top-level interrupt handler for all PCI interrupts from a Target.
3191 * When a block of MSI interrupts is allocated, this top-level handler
3192 * is not used; instead, we directly call the correct sub-handler.
3196 struct ath10k *ar = arg; in ath10k_pci_interrupt_handler() local
3197 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_interrupt_handler()
3200 if (ath10k_pci_has_device_gone(ar)) in ath10k_pci_interrupt_handler()
3203 ret = ath10k_pci_force_wake(ar); in ath10k_pci_interrupt_handler()
3205 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret); in ath10k_pci_interrupt_handler()
3209 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) && in ath10k_pci_interrupt_handler()
3210 !ath10k_pci_irq_pending(ar)) in ath10k_pci_interrupt_handler()
3213 ath10k_pci_disable_and_clear_legacy_irq(ar); in ath10k_pci_interrupt_handler()
3214 ath10k_pci_irq_msi_fw_mask(ar); in ath10k_pci_interrupt_handler()
3215 napi_schedule(&ar->napi); in ath10k_pci_interrupt_handler()
3222 struct ath10k *ar = container_of(ctx, struct ath10k, napi); in ath10k_pci_napi_poll() local
3225 if (ath10k_pci_has_fw_crashed(ar)) { in ath10k_pci_napi_poll()
3226 ath10k_pci_fw_crashed_clear(ar); in ath10k_pci_napi_poll()
3227 ath10k_pci_fw_crashed_dump(ar); in ath10k_pci_napi_poll()
3232 ath10k_ce_per_engine_service_any(ar); in ath10k_pci_napi_poll()
3234 done = ath10k_htt_txrx_compl_task(ar, budget); in ath10k_pci_napi_poll()
3246 if (ath10k_ce_interrupt_summary(ar)) { in ath10k_pci_napi_poll()
3250 ath10k_pci_enable_legacy_irq(ar); in ath10k_pci_napi_poll()
3251 ath10k_pci_irq_msi_fw_unmask(ar); in ath10k_pci_napi_poll()
3258 static int ath10k_pci_request_irq_msi(struct ath10k *ar) in ath10k_pci_request_irq_msi() argument
3260 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_request_irq_msi()
3263 ret = request_irq(ar_pci->pdev->irq, in ath10k_pci_request_irq_msi()
3265 IRQF_SHARED, "ath10k_pci", ar); in ath10k_pci_request_irq_msi()
3267 ath10k_warn(ar, "failed to request MSI irq %d: %d\n", in ath10k_pci_request_irq_msi()
3268 ar_pci->pdev->irq, ret); in ath10k_pci_request_irq_msi()
3275 static int ath10k_pci_request_irq_legacy(struct ath10k *ar) in ath10k_pci_request_irq_legacy() argument
3277 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_request_irq_legacy()
3280 ret = request_irq(ar_pci->pdev->irq, in ath10k_pci_request_irq_legacy()
3282 IRQF_SHARED, "ath10k_pci", ar); in ath10k_pci_request_irq_legacy()
3284 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", in ath10k_pci_request_irq_legacy()
3285 ar_pci->pdev->irq, ret); in ath10k_pci_request_irq_legacy()
3292 static int ath10k_pci_request_irq(struct ath10k *ar) in ath10k_pci_request_irq() argument
3294 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_request_irq()
3296 switch (ar_pci->oper_irq_mode) { in ath10k_pci_request_irq()
3298 return ath10k_pci_request_irq_legacy(ar); in ath10k_pci_request_irq()
3300 return ath10k_pci_request_irq_msi(ar); in ath10k_pci_request_irq()
3302 return -EINVAL; in ath10k_pci_request_irq()
3306 static void ath10k_pci_free_irq(struct ath10k *ar) in ath10k_pci_free_irq() argument
3308 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_free_irq()
3310 free_irq(ar_pci->pdev->irq, ar); in ath10k_pci_free_irq()
3313 void ath10k_pci_init_napi(struct ath10k *ar) in ath10k_pci_init_napi() argument
3315 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll); in ath10k_pci_init_napi()
3318 static int ath10k_pci_init_irq(struct ath10k *ar) in ath10k_pci_init_irq() argument
3320 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_init_irq()
3323 ath10k_pci_init_napi(ar); in ath10k_pci_init_irq()
3326 ath10k_info(ar, "limiting irq mode to: %d\n", in ath10k_pci_init_irq()
3331 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI; in ath10k_pci_init_irq()
3332 ret = pci_enable_msi(ar_pci->pdev); in ath10k_pci_init_irq()
3348 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; in ath10k_pci_init_irq()
3350 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, in ath10k_pci_init_irq()
3356 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) in ath10k_pci_deinit_irq_legacy() argument
3358 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, in ath10k_pci_deinit_irq_legacy()
3362 static int ath10k_pci_deinit_irq(struct ath10k *ar) in ath10k_pci_deinit_irq() argument
3364 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_deinit_irq()
3366 switch (ar_pci->oper_irq_mode) { in ath10k_pci_deinit_irq()
3368 ath10k_pci_deinit_irq_legacy(ar); in ath10k_pci_deinit_irq()
3371 pci_disable_msi(ar_pci->pdev); in ath10k_pci_deinit_irq()
3378 int ath10k_pci_wait_for_target_init(struct ath10k *ar) in ath10k_pci_wait_for_target_init() argument
3380 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_wait_for_target_init()
3384 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); in ath10k_pci_wait_for_target_init()
3389 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); in ath10k_pci_wait_for_target_init()
3391 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", in ath10k_pci_wait_for_target_init()
3405 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) in ath10k_pci_wait_for_target_init()
3407 ath10k_pci_enable_legacy_irq(ar); in ath10k_pci_wait_for_target_init()
3412 ath10k_pci_disable_and_clear_legacy_irq(ar); in ath10k_pci_wait_for_target_init()
3413 ath10k_pci_irq_msi_fw_mask(ar); in ath10k_pci_wait_for_target_init()
3416 ath10k_err(ar, "failed to read device register, device is gone\n"); in ath10k_pci_wait_for_target_init()
3417 return -EIO; in ath10k_pci_wait_for_target_init()
3421 ath10k_warn(ar, "device has crashed during init\n"); in ath10k_pci_wait_for_target_init()
3422 return -ECOMM; in ath10k_pci_wait_for_target_init()
3426 ath10k_err(ar, "failed to receive initialized event from target: %08x\n", in ath10k_pci_wait_for_target_init()
3428 return -ETIMEDOUT; in ath10k_pci_wait_for_target_init()
3431 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); in ath10k_pci_wait_for_target_init()
3435 static int ath10k_pci_cold_reset(struct ath10k *ar) in ath10k_pci_cold_reset() argument
3439 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); in ath10k_pci_cold_reset()
3441 spin_lock_bh(&ar->data_lock); in ath10k_pci_cold_reset()
3443 ar->stats.fw_cold_reset_counter++; in ath10k_pci_cold_reset()
3445 spin_unlock_bh(&ar->data_lock); in ath10k_pci_cold_reset()
3448 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); in ath10k_pci_cold_reset()
3450 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); in ath10k_pci_cold_reset()
3461 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); in ath10k_pci_cold_reset()
3465 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); in ath10k_pci_cold_reset()
3470 static int ath10k_pci_claim(struct ath10k *ar) in ath10k_pci_claim() argument
3472 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_claim()
3473 struct pci_dev *pdev = ar_pci->pdev; in ath10k_pci_claim()
3476 pci_set_drvdata(pdev, ar); in ath10k_pci_claim()
3480 ath10k_err(ar, "failed to enable pci device: %d\n", ret); in ath10k_pci_claim()
3486 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, in ath10k_pci_claim()
3492 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in ath10k_pci_claim()
3494 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); in ath10k_pci_claim()
3505 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); in ath10k_pci_claim()
3506 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); in ath10k_pci_claim()
3507 if (!ar_pci->mem) { in ath10k_pci_claim()
3508 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); in ath10k_pci_claim()
3509 ret = -EIO; in ath10k_pci_claim()
3513 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem); in ath10k_pci_claim()
3525 static void ath10k_pci_release(struct ath10k *ar) in ath10k_pci_release() argument
3527 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_release()
3528 struct pci_dev *pdev = ar_pci->pdev; in ath10k_pci_release()
3530 pci_iounmap(pdev, ar_pci->mem); in ath10k_pci_release()
3544 if (supp_chip->dev_id == dev_id && in ath10k_pci_chip_is_supported()
3545 supp_chip->rev_id == rev_id) in ath10k_pci_chip_is_supported()
3552 int ath10k_pci_setup_resource(struct ath10k *ar) in ath10k_pci_setup_resource() argument
3554 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_setup_resource()
3555 struct ath10k_ce *ce = ath10k_ce_priv(ar); in ath10k_pci_setup_resource()
3558 spin_lock_init(&ce->ce_lock); in ath10k_pci_setup_resource()
3559 spin_lock_init(&ar_pci->ps_lock); in ath10k_pci_setup_resource()
3560 mutex_init(&ar_pci->ce_diag_mutex); in ath10k_pci_setup_resource()
3562 INIT_WORK(&ar_pci->dump_work, ath10k_pci_fw_dump_work); in ath10k_pci_setup_resource()
3564 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0); in ath10k_pci_setup_resource()
3566 ar_pci->attr = kmemdup(pci_host_ce_config_wlan, in ath10k_pci_setup_resource()
3569 if (!ar_pci->attr) in ath10k_pci_setup_resource()
3570 return -ENOMEM; in ath10k_pci_setup_resource()
3572 ar_pci->pipe_config = kmemdup(pci_target_ce_config_wlan, in ath10k_pci_setup_resource()
3575 if (!ar_pci->pipe_config) { in ath10k_pci_setup_resource()
3576 ret = -ENOMEM; in ath10k_pci_setup_resource()
3580 ar_pci->serv_to_pipe = kmemdup(pci_target_service_to_ce_map_wlan, in ath10k_pci_setup_resource()
3583 if (!ar_pci->serv_to_pipe) { in ath10k_pci_setup_resource()
3584 ret = -ENOMEM; in ath10k_pci_setup_resource()
3588 if (QCA_REV_6174(ar) || QCA_REV_9377(ar)) in ath10k_pci_setup_resource()
3589 ath10k_pci_override_ce_config(ar); in ath10k_pci_setup_resource()
3591 ret = ath10k_pci_alloc_pipes(ar); in ath10k_pci_setup_resource()
3593 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", in ath10k_pci_setup_resource()
3601 kfree(ar_pci->serv_to_pipe); in ath10k_pci_setup_resource()
3603 kfree(ar_pci->pipe_config); in ath10k_pci_setup_resource()
3605 kfree(ar_pci->attr); in ath10k_pci_setup_resource()
3609 void ath10k_pci_release_resource(struct ath10k *ar) in ath10k_pci_release_resource() argument
3611 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_pci_release_resource()
3613 ath10k_pci_rx_retry_sync(ar); in ath10k_pci_release_resource()
3614 netif_napi_del(&ar->napi); in ath10k_pci_release_resource()
3615 ath10k_pci_ce_deinit(ar); in ath10k_pci_release_resource()
3616 ath10k_pci_free_pipes(ar); in ath10k_pci_release_resource()
3617 kfree(ar_pci->attr); in ath10k_pci_release_resource()
3618 kfree(ar_pci->pipe_config); in ath10k_pci_release_resource()
3619 kfree(ar_pci->serv_to_pipe); in ath10k_pci_release_resource()
3632 struct ath10k *ar; in ath10k_pci_probe() local
3637 int (*pci_soft_reset)(struct ath10k *ar); in ath10k_pci_probe()
3638 int (*pci_hard_reset)(struct ath10k *ar); in ath10k_pci_probe()
3639 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); in ath10k_pci_probe()
3641 switch (pci_dev->device) { in ath10k_pci_probe()
3696 return -ENOTSUPP; in ath10k_pci_probe()
3699 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, in ath10k_pci_probe()
3701 if (!ar) { in ath10k_pci_probe()
3702 dev_err(&pdev->dev, "failed to allocate core\n"); in ath10k_pci_probe()
3703 return -ENOMEM; in ath10k_pci_probe()
3706 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", in ath10k_pci_probe()
3707 pdev->vendor, pdev->device, in ath10k_pci_probe()
3708 pdev->subsystem_vendor, pdev->subsystem_device); in ath10k_pci_probe()
3710 ar_pci = ath10k_pci_priv(ar); in ath10k_pci_probe()
3711 ar_pci->pdev = pdev; in ath10k_pci_probe()
3712 ar_pci->dev = &pdev->dev; in ath10k_pci_probe()
3713 ar_pci->ar = ar; in ath10k_pci_probe()
3714 ar->dev_id = pci_dev->device; in ath10k_pci_probe()
3715 ar_pci->pci_ps = pci_ps; in ath10k_pci_probe()
3716 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops; in ath10k_pci_probe()
3717 ar_pci->pci_soft_reset = pci_soft_reset; in ath10k_pci_probe()
3718 ar_pci->pci_hard_reset = pci_hard_reset; in ath10k_pci_probe()
3719 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; in ath10k_pci_probe()
3720 ar->ce_priv = &ar_pci->ce; in ath10k_pci_probe()
3722 ar->id.vendor = pdev->vendor; in ath10k_pci_probe()
3723 ar->id.device = pdev->device; in ath10k_pci_probe()
3724 ar->id.subsystem_vendor = pdev->subsystem_vendor; in ath10k_pci_probe()
3725 ar->id.subsystem_device = pdev->subsystem_device; in ath10k_pci_probe()
3727 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0); in ath10k_pci_probe()
3729 ret = ath10k_pci_setup_resource(ar); in ath10k_pci_probe()
3731 ath10k_err(ar, "failed to setup resource: %d\n", ret); in ath10k_pci_probe()
3735 ret = ath10k_pci_claim(ar); in ath10k_pci_probe()
3737 ath10k_err(ar, "failed to claim device: %d\n", ret); in ath10k_pci_probe()
3741 ret = ath10k_pci_force_wake(ar); in ath10k_pci_probe()
3743 ath10k_warn(ar, "failed to wake up device : %d\n", ret); in ath10k_pci_probe()
3747 ath10k_pci_ce_deinit(ar); in ath10k_pci_probe()
3748 ath10k_pci_irq_disable(ar); in ath10k_pci_probe()
3750 ret = ath10k_pci_init_irq(ar); in ath10k_pci_probe()
3752 ath10k_err(ar, "failed to init irqs: %d\n", ret); in ath10k_pci_probe()
3756 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n", in ath10k_pci_probe()
3757 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode, in ath10k_pci_probe()
3760 ret = ath10k_pci_request_irq(ar); in ath10k_pci_probe()
3762 ath10k_warn(ar, "failed to request irqs: %d\n", ret); in ath10k_pci_probe()
3768 /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that in ath10k_pci_probe()
3774 ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); in ath10k_pci_probe()
3776 if (!ath10k_pci_chip_is_supported(pdev->device, in ath10k_pci_probe()
3778 ret = -ENODEV; in ath10k_pci_probe()
3784 ret = ath10k_pci_chip_reset(ar); in ath10k_pci_probe()
3786 ath10k_err(ar, "failed to reset chip: %d\n", ret); in ath10k_pci_probe()
3790 bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); in ath10k_pci_probe()
3792 ret = -ENODEV; in ath10k_pci_probe()
3796 if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) { in ath10k_pci_probe()
3797 ret = -ENODEV; in ath10k_pci_probe()
3801 ret = ath10k_core_register(ar, &bus_params); in ath10k_pci_probe()
3803 ath10k_err(ar, "failed to register driver core: %d\n", ret); in ath10k_pci_probe()
3810 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", in ath10k_pci_probe()
3811 pdev->device, bus_params.chip_id); in ath10k_pci_probe()
3814 ath10k_pci_free_irq(ar); in ath10k_pci_probe()
3817 ath10k_pci_release_resource(ar); in ath10k_pci_probe()
3820 ath10k_pci_sleep_sync(ar); in ath10k_pci_probe()
3821 ath10k_pci_release(ar); in ath10k_pci_probe()
3824 ath10k_pci_free_pipes(ar); in ath10k_pci_probe()
3827 ath10k_core_destroy(ar); in ath10k_pci_probe()
3834 struct ath10k *ar = pci_get_drvdata(pdev); in ath10k_pci_remove() local
3836 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); in ath10k_pci_remove()
3838 if (!ar) in ath10k_pci_remove()
3841 ath10k_core_unregister(ar); in ath10k_pci_remove()
3842 ath10k_pci_free_irq(ar); in ath10k_pci_remove()
3843 ath10k_pci_deinit_irq(ar); in ath10k_pci_remove()
3844 ath10k_pci_release_resource(ar); in ath10k_pci_remove()
3845 ath10k_pci_sleep_sync(ar); in ath10k_pci_remove()
3846 ath10k_pci_release(ar); in ath10k_pci_remove()
3847 ath10k_core_destroy(ar); in ath10k_pci_remove()
3855 struct ath10k *ar = dev_get_drvdata(dev); in ath10k_pci_pm_suspend() local
3858 ret = ath10k_pci_suspend(ar); in ath10k_pci_pm_suspend()
3860 ath10k_warn(ar, "failed to suspend hif: %d\n", ret); in ath10k_pci_pm_suspend()
3867 struct ath10k *ar = dev_get_drvdata(dev); in ath10k_pci_pm_resume() local
3870 ret = ath10k_pci_resume(ar); in ath10k_pci_pm_resume()
3872 ath10k_warn(ar, "failed to resume hif: %d\n", ret); in ath10k_pci_pm_resume()
3893 .bsd_probe_return = (BUS_PROBE_DEFAULT - 1),