3590 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_tx_lock()
3611 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_tx_unlock()
3631 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_tx_lock()
3642 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_tx_unlock()
3662 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_handle_tx_pause()
3707 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_handle_tx_pause_vdev()
3712 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_handle_tx_pause_vdev()
3750 	if (ar->htt.target_version_major < 3 &&  in ath10k_mac_tx_h_get_txmode()
3960 	return (ar->htt.target_version_major >= 3 &&  in ath10k_mac_tx_frm_has_freq()
3961 		ar->htt.target_version_minor >= 4 &&  in ath10k_mac_tx_frm_has_freq()
3996 		else if (ar->htt.target_version_major >= 3)  in ath10k_mac_tx_h_get_txpath()
4010 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_tx_submit()  local
4015 		ret = ath10k_htt_tx(htt, txmode, skb);  in ath10k_mac_tx_submit()
4018 		ret = ath10k_htt_mgmt_tx(htt, skb);  in ath10k_mac_tx_submit()
4288 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_txq_unref()
4289 	idr_for_each_entry(&ar->htt.pending_tx, msdu, msdu_id) {  in ath10k_mac_txq_unref()
4294 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_txq_unref()
4327 	if (ar->htt.tx_q_state.mode == HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_tx_can_push()
4330 	if (ar->htt.num_pending_tx < ar->htt.tx_q_state.num_push_allowed)  in ath10k_mac_tx_can_push()
4389 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_tx_push_txq()  local
4402 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4403 	ret = ath10k_htt_tx_inc_pending(htt);  in ath10k_mac_tx_push_txq()
4404 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4411 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4412 		ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4413 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4430 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4431 		ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);  in ath10k_mac_tx_push_txq()
4434 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4435 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4438 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4445 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4446 		ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4448 			ath10k_htt_tx_mgmt_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4449 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4454 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4456 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4488 	if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_tx_push_pending()
4491 	if (ar->htt.num_pending_tx >= (ar->htt.max_num_pending_tx / 2))  in ath10k_mac_tx_push_pending()
4674 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_op_tx()  local
4698 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4705 		ret = ath10k_htt_tx_inc_pending(htt);  in ath10k_mac_op_tx()
4709 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4714 		ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);  in ath10k_mac_op_tx()
4718 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_op_tx()
4719 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4723 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4730 			spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4731 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_op_tx()
4733 				ath10k_htt_tx_mgmt_dec_pending(htt);  in ath10k_mac_op_tx()
4734 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4748 	if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_op_wake_tx_queue()
5866 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_add_interface()
5869 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_add_interface()
6017 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_remove_interface()
6019 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_remove_interface()
8069 	time_left = wait_event_timeout(ar->htt.empty_tx_wq, ({  in ath10k_mac_wait_tx_complete()
8072 			spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_wait_tx_complete()
8073 			empty = (ar->htt.num_pending_tx == 0);  in ath10k_mac_wait_tx_complete()
8074 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_wait_tx_complete()
8103 			ath10k_htt_flush_tx(&ar->htt);  in ath10k_flush()
9375 	if (ar->htt.disable_tx_comp) {  in ath10k_sta_statistics()