Lines Matching +full:0 +full:x0000003c
20 .rtc_soc_base_address = 0x00004000,
21 .rtc_wmac_base_address = 0x00005000,
22 .soc_core_base_address = 0x00009000,
23 .wlan_mac_base_address = 0x00020000,
24 .ce_wrapper_base_address = 0x00057000,
25 .ce0_base_address = 0x00057400,
26 .ce1_base_address = 0x00057800,
27 .ce2_base_address = 0x00057c00,
28 .ce3_base_address = 0x00058000,
29 .ce4_base_address = 0x00058400,
30 .ce5_base_address = 0x00058800,
31 .ce6_base_address = 0x00058c00,
32 .ce7_base_address = 0x00059000,
33 .soc_reset_control_si0_rst_mask = 0x00000001,
34 .soc_reset_control_ce_rst_mask = 0x00040000,
35 .soc_chip_id_address = 0x000000ec,
36 .scratch_3_address = 0x00000030,
37 .fw_indicator_address = 0x00009030,
38 .pcie_local_base_address = 0x00080000,
39 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
40 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
41 .pcie_intr_fw_mask = 0x00000400,
42 .pcie_intr_ce_mask_all = 0x0007f800,
43 .pcie_intr_clr_address = 0x00000014,
47 .rtc_soc_base_address = 0x00000800,
48 .rtc_wmac_base_address = 0x00001000,
49 .soc_core_base_address = 0x0003a000,
50 .wlan_mac_base_address = 0x00010000,
51 .ce_wrapper_base_address = 0x00034000,
52 .ce0_base_address = 0x00034400,
53 .ce1_base_address = 0x00034800,
54 .ce2_base_address = 0x00034c00,
55 .ce3_base_address = 0x00035000,
56 .ce4_base_address = 0x00035400,
57 .ce5_base_address = 0x00035800,
58 .ce6_base_address = 0x00035c00,
59 .ce7_base_address = 0x00036000,
60 .soc_reset_control_si0_rst_mask = 0x00000000,
61 .soc_reset_control_ce_rst_mask = 0x00000001,
62 .soc_chip_id_address = 0x000000f0,
63 .scratch_3_address = 0x00000028,
64 .fw_indicator_address = 0x0003a028,
65 .pcie_local_base_address = 0x00080000,
66 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
67 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
68 .pcie_intr_fw_mask = 0x00000400,
69 .pcie_intr_ce_mask_all = 0x0007f800,
70 .pcie_intr_clr_address = 0x00000014,
71 .cpu_pll_init_address = 0x00404020,
72 .cpu_speed_address = 0x00404024,
73 .core_clk_div_address = 0x00404028,
77 .rtc_soc_base_address = 0x00080000,
78 .rtc_wmac_base_address = 0x00000000,
79 .soc_core_base_address = 0x00082000,
80 .wlan_mac_base_address = 0x00030000,
81 .ce_wrapper_base_address = 0x0004d000,
82 .ce0_base_address = 0x0004a000,
83 .ce1_base_address = 0x0004a400,
84 .ce2_base_address = 0x0004a800,
85 .ce3_base_address = 0x0004ac00,
86 .ce4_base_address = 0x0004b000,
87 .ce5_base_address = 0x0004b400,
88 .ce6_base_address = 0x0004b800,
89 .ce7_base_address = 0x0004bc00,
95 * CE8 0x0004c000
96 * CE9 0x0004c400
97 * CE10 0x0004c800
98 * CE11 0x0004cc00
100 .soc_reset_control_si0_rst_mask = 0x00000001,
101 .soc_reset_control_ce_rst_mask = 0x00000100,
102 .soc_chip_id_address = 0x000000ec,
103 .scratch_3_address = 0x00040050,
104 .fw_indicator_address = 0x00040050,
105 .pcie_local_base_address = 0x00000000,
106 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
107 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
108 .pcie_intr_fw_mask = 0x00100000,
109 .pcie_intr_ce_mask_all = 0x000fff00,
110 .pcie_intr_clr_address = 0x00000010,
114 .rtc_soc_base_address = 0x00080000,
115 .soc_core_base_address = 0x00082000,
116 .wlan_mac_base_address = 0x00030000,
117 .ce_wrapper_base_address = 0x0004d000,
118 .ce0_base_address = 0x0004a000,
119 .ce1_base_address = 0x0004a400,
120 .ce2_base_address = 0x0004a800,
121 .ce3_base_address = 0x0004ac00,
122 .ce4_base_address = 0x0004b000,
123 .ce5_base_address = 0x0004b400,
124 .ce6_base_address = 0x0004b800,
125 .ce7_base_address = 0x0004bc00,
130 * CE8 0x0004c000
131 * CE9 0x0004c400
132 * CE10 0x0004c800
133 * CE11 0x0004cc00
135 .soc_reset_control_si0_rst_mask = 0x00000001,
136 .soc_reset_control_ce_rst_mask = 0x00000100,
137 .soc_chip_id_address = 0x000000ec,
138 .fw_indicator_address = 0x0004f00c,
139 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
140 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
141 .pcie_intr_fw_mask = 0x00100000,
142 .pcie_intr_ce_mask_all = 0x000fff00,
143 .pcie_intr_clr_address = 0x00000010,
151 .ce_desc_meta_data_mask = 0xFFFC,
160 .ce_desc_meta_data_mask = 0xFFFC,
163 .rfkill_cfg = 0,
172 .ce_desc_meta_data_mask = 0xFFF0,
181 .ce_desc_meta_data_mask = 0xFFF0,
188 .ce_desc_meta_data_mask = 0xFFF0,
193 .rtc_soc_base_address = 0x00000000,
194 .rtc_wmac_base_address = 0x00000000,
195 .soc_core_base_address = 0x00000000,
196 .ce_wrapper_base_address = 0x0024C000,
197 .ce0_base_address = 0x00240000,
198 .ce1_base_address = 0x00241000,
199 .ce2_base_address = 0x00242000,
200 .ce3_base_address = 0x00243000,
201 .ce4_base_address = 0x00244000,
202 .ce5_base_address = 0x00245000,
203 .ce6_base_address = 0x00246000,
204 .ce7_base_address = 0x00247000,
205 .ce8_base_address = 0x00248000,
206 .ce9_base_address = 0x00249000,
207 .ce10_base_address = 0x0024A000,
208 .ce11_base_address = 0x0024B000,
209 .soc_chip_id_address = 0x000000f0,
210 .soc_reset_control_si0_rst_mask = 0x00000001,
211 .soc_reset_control_ce_rst_mask = 0x00000100,
212 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
213 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
214 .pcie_intr_fw_mask = 0x00100000,
218 .msb = 0x00000010,
219 .lsb = 0x00000010,
224 .msb = 0x00000012,
225 .lsb = 0x00000012,
230 .msb = 0x00000000,
231 .lsb = 0x00000000,
232 .mask = GENMASK(15, 0),
236 .addr = 0x00000018,
243 .mask = GENMASK(0, 0),
251 .dstr_lmask = 0x00000010,
252 .dstr_hmask = 0x00000008,
253 .srcr_lmask = 0x00000004,
254 .srcr_hmask = 0x00000002,
255 .cc_mask = 0x00000001,
256 .wm_mask = 0x0000001E,
257 .addr = 0x00000030,
261 .axi_err = 0x00000100,
262 .dstr_add_err = 0x00000200,
263 .srcr_len_err = 0x00000100,
264 .dstr_mlen_vio = 0x00000080,
265 .dstr_overflow = 0x00000040,
266 .srcr_overflow = 0x00000020,
267 .err_mask = 0x000003E0,
268 .addr = 0x00000038,
272 .msb = 0x00000000,
273 .lsb = 0x00000010,
278 .msb = 0x0000000f,
279 .lsb = 0x00000000,
280 .mask = GENMASK(15, 0),
284 .addr = 0x0000004c,
285 .low_rst = 0x00000000,
286 .high_rst = 0x00000000,
292 .lsb = 0x00000010,
297 .msb = 0x0000000f,
298 .lsb = 0x00000000,
299 .mask = GENMASK(15, 0),
303 .addr = 0x00000050,
304 .low_rst = 0x00000000,
305 .high_rst = 0x00000000,
312 .mask = 0x00080000,
313 .enable = 0x00000000,
317 .sr_base_addr_lo = 0x00000000,
318 .sr_base_addr_hi = 0x00000004,
319 .sr_size_addr = 0x00000008,
320 .dr_base_addr_lo = 0x0000000c,
321 .dr_base_addr_hi = 0x00000010,
322 .dr_size_addr = 0x00000014,
323 .misc_ie_addr = 0x00000034,
324 .sr_wr_index_addr = 0x0000003c,
325 .dst_wr_index_addr = 0x00000040,
326 .current_srri_addr = 0x00000044,
327 .current_drri_addr = 0x00000048,
328 .ce_rri_low = 0x0024C004,
329 .ce_rri_high = 0x0024C008,
330 .host_ie_addr = 0x0000002c,
345 .ce_desc_meta_data_mask = 0xFFF0,
350 .msb = 0x00000010,
351 .lsb = 0x00000010,
356 .msb = 0x00000011,
357 .lsb = 0x00000011,
362 .msb = 0x0000000f,
363 .lsb = 0x00000000,
364 .mask = GENMASK(15, 0),
368 .addr = 0x00000010,
369 .hw_mask = 0x0007ffff,
370 .sw_mask = 0x0007ffff,
371 .hw_wr_mask = 0x00000000,
372 .sw_wr_mask = 0x0007ffff,
373 .reset_mask = 0xffffffff,
374 .reset = 0x00000080,
381 .msb = 0x00000003,
382 .lsb = 0x00000003,
387 .msb = 0x00000000,
388 .mask = GENMASK(0, 0),
389 .status_reset = 0x00000000,
394 .msb = 0x00000000,
395 .lsb = 0x00000000,
396 .mask = GENMASK(0, 0),
400 .copy_complete_reset = 0x00000000,
405 .dstr_lmask = 0x00000010,
406 .dstr_hmask = 0x00000008,
407 .srcr_lmask = 0x00000004,
408 .srcr_hmask = 0x00000002,
409 .cc_mask = 0x00000001,
410 .wm_mask = 0x0000001E,
411 .addr = 0x00000030,
415 .axi_err = 0x00000400,
416 .dstr_add_err = 0x00000200,
417 .srcr_len_err = 0x00000100,
418 .dstr_mlen_vio = 0x00000080,
419 .dstr_overflow = 0x00000040,
420 .srcr_overflow = 0x00000020,
421 .err_mask = 0x000007E0,
422 .addr = 0x00000038,
426 .msb = 0x0000001f,
427 .lsb = 0x00000010,
432 .msb = 0x0000000f,
433 .lsb = 0x00000000,
434 .mask = GENMASK(15, 0),
438 .addr = 0x0000004c,
439 .low_rst = 0x00000000,
440 .high_rst = 0x00000000,
446 .lsb = 0x00000010,
451 .msb = 0x0000000f,
452 .lsb = 0x00000000,
453 .mask = GENMASK(15, 0),
457 .addr = 0x00000050,
458 .low_rst = 0x00000000,
459 .high_rst = 0x00000000,
465 .sr_base_addr_lo = 0x00000000,
466 .sr_size_addr = 0x00000004,
467 .dr_base_addr_lo = 0x00000008,
468 .dr_size_addr = 0x0000000c,
469 .ce_cmd_addr = 0x00000018,
470 .misc_ie_addr = 0x00000034,
471 .sr_wr_index_addr = 0x0000003c,
472 .dst_wr_index_addr = 0x00000040,
473 .current_srri_addr = 0x00000044,
474 .current_drri_addr = 0x00000048,
475 .host_ie_addr = 0x0000002c,
488 .div = 0xe,
489 .rnfrac = 0x2aaa8,
491 .refdiv = 0,
496 .div = 0x24,
497 .rnfrac = 0x2aaa8,
499 .refdiv = 0,
504 .div = 0x1d,
505 .rnfrac = 0x15551,
507 .refdiv = 0,
512 .div = 0x1b,
513 .rnfrac = 0x4ec4,
515 .refdiv = 0,
520 .div = 0x12,
521 .rnfrac = 0x34b49,
523 .refdiv = 0,
528 .div = 0x12,
529 .rnfrac = 0x15551,
531 .refdiv = 0,
536 .div = 0x12,
537 .rnfrac = 0x26665,
539 .refdiv = 0,
544 .div = 0x1b,
545 .rnfrac = 0x4ec4,
547 .refdiv = 0,
555 u32 cc_fix = 0; in ath10k_hw_fill_survey_time()
556 u32 rcc_fix = 0; in ath10k_hw_fill_survey_time()
568 cc_fix = 0x7fffffff; in ath10k_hw_fill_survey_time()
574 cc_fix = 0x7fffffff; in ath10k_hw_fill_survey_time()
577 rcc_fix = 0x7fffffff; in ath10k_hw_fill_survey_time()
630 if (value < 0) in ath10k_hw_qca988x_set_coverage_class()
703 * coverage class is larger than 0. This is important as we need to in ath10k_hw_qca988x_set_coverage_class()
710 if (value > 0) { in ath10k_hw_qca988x_set_coverage_class()
713 fw_dbglog_mask = ~0; in ath10k_hw_qca988x_set_coverage_class()
741 * Return: 0 if successfully enable the pll, otherwise EINVAL
753 if (ar->regs->core_clk_div_address == 0 || in ath10k_hw_qca6174_enable_pll_clock()
754 ar->regs->cpu_pll_init_address == 0 || in ath10k_hw_qca6174_enable_pll_clock()
755 ar->regs->cpu_speed_address == 0) in ath10k_hw_qca6174_enable_pll_clock()
849 } while (wait_limit > 0); in ath10k_hw_qca6174_enable_pll_clock()
861 reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS); in ath10k_hw_qca6174_enable_pll_clock()
880 } while (wait_limit > 0); in ath10k_hw_qca6174_enable_pll_clock()
929 return 0; in ath10k_hw_qca6174_enable_pll_clock()
943 * 2. Target address( 0 ~ 00100000 & 0x00400000~0x00500000)
972 "failed to download the first %d bytes segment to address:0x%x: %d\n", in ath10k_hw_diag_segment_msb_download()
986 "failed to download the second %d bytes segment to address:0x%x: %d\n", in ath10k_hw_diag_segment_msb_download()
996 "failed to download the only %d bytes segment to address:0x%x: %d\n", in ath10k_hw_diag_segment_msb_download()
1029 u32 base_addr = 0; in ath10k_hw_diag_fast_download()
1030 u32 base_len = 0; in ath10k_hw_diag_fast_download()
1031 u32 left = 0; in ath10k_hw_diag_fast_download()
1039 int ret = 0; in ath10k_hw_diag_fast_download()
1054 "Not a supported firmware, magic_num:0x%x\n", in ath10k_hw_diag_fast_download()
1059 if (hdr->file_flags != 0) { in ath10k_hw_diag_fast_download()
1061 "Not a supported firmware, file_flags:0x%x\n", in ath10k_hw_diag_fast_download()
1073 while (left > 0) { in ath10k_hw_diag_fast_download()
1089 base_len = 0; in ath10k_hw_diag_fast_download()
1093 base_len = 0; in ath10k_hw_diag_fast_download()
1095 ret = 0; in ath10k_hw_diag_fast_download()
1137 if (ret == 0) in ath10k_hw_diag_fast_download()
1157 int pad_bytes = 0; in ath10k_get_htt_tx_data_rssi_pad()
1161 sizeof(extd.msdus_rssi[0]); in ath10k_get_htt_tx_data_rssi_pad()
1164 pad_bytes += sizeof(extd.t_stamp) / sizeof(extd.msdus_rssi[0]); in ath10k_get_htt_tx_data_rssi_pad()