28 static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar)  in ath10k_ahb_priv()  argument
30 	return &ath10k_pci_priv(ar)->ahb[0];  in ath10k_ahb_priv()
33 static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value)  in ath10k_ahb_write32()  argument
35 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_write32()
40 static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset)  in ath10k_ahb_read32()  argument
42 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_read32()
47 static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset)  in ath10k_ahb_gcc_read32()  argument
49 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_gcc_read32()
54 static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value)  in ath10k_ahb_tcsr_write32()  argument
56 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_tcsr_write32()
61 static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset)  in ath10k_ahb_tcsr_read32()  argument
63 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_tcsr_read32()
68 static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr)  in ath10k_ahb_soc_read32()  argument
70 	return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr);  in ath10k_ahb_soc_read32()
73 static int ath10k_ahb_get_num_banks(struct ath10k *ar)  in ath10k_ahb_get_num_banks()  argument
75 	if (ar->hw_rev == ATH10K_HW_QCA4019)  in ath10k_ahb_get_num_banks()
78 	ath10k_warn(ar, "unknown number of banks, assuming 1\n");  in ath10k_ahb_get_num_banks()
82 static int ath10k_ahb_clock_init(struct ath10k *ar)  in ath10k_ahb_clock_init()  argument
84 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_clock_init()
91 		ath10k_err(ar, "failed to get cmd clk: %ld\n",  in ath10k_ahb_clock_init()
98 		ath10k_err(ar, "failed to get ref clk: %ld\n",  in ath10k_ahb_clock_init()
105 		ath10k_err(ar, "failed to get rtc clk: %ld\n",  in ath10k_ahb_clock_init()
113 static void ath10k_ahb_clock_deinit(struct ath10k *ar)  in ath10k_ahb_clock_deinit()  argument
115 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_clock_deinit()
122 static int ath10k_ahb_clock_enable(struct ath10k *ar)  in ath10k_ahb_clock_enable()  argument
124 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_clock_enable()
130 		ath10k_err(ar, "clock(s) is/are not initialized\n");  in ath10k_ahb_clock_enable()
137 		ath10k_err(ar, "failed to enable cmd clk: %d\n", ret);  in ath10k_ahb_clock_enable()
143 		ath10k_err(ar, "failed to enable ref clk: %d\n", ret);  in ath10k_ahb_clock_enable()
149 		ath10k_err(ar, "failed to enable rtc clk: %d\n", ret);  in ath10k_ahb_clock_enable()
165 static void ath10k_ahb_clock_disable(struct ath10k *ar)  in ath10k_ahb_clock_disable()  argument
167 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_clock_disable()
176 static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar)  in ath10k_ahb_rst_ctrl_init()  argument
178 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_rst_ctrl_init()
186 		ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n",  in ath10k_ahb_rst_ctrl_init()
194 		ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n",  in ath10k_ahb_rst_ctrl_init()
202 		ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n",  in ath10k_ahb_rst_ctrl_init()
210 		ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n",  in ath10k_ahb_rst_ctrl_init()
218 		ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n",  in ath10k_ahb_rst_ctrl_init()
226 static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar)  in ath10k_ahb_rst_ctrl_deinit()  argument
228 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_rst_ctrl_deinit()
237 static int ath10k_ahb_release_reset(struct ath10k *ar)  in ath10k_ahb_release_reset()  argument
239 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_release_reset()
246 		ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");  in ath10k_ahb_release_reset()
252 		ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret);  in ath10k_ahb_release_reset()
258 		ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret);  in ath10k_ahb_release_reset()
264 		ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret);  in ath10k_ahb_release_reset()
270 		ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret);  in ath10k_ahb_release_reset()
277 static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg,  in ath10k_ahb_halt_axi_bus()  argument
284 	val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);  in ath10k_ahb_halt_axi_bus()
286 	ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);  in ath10k_ahb_halt_axi_bus()
291 		val = ath10k_ahb_tcsr_read32(ar, haltack_reg);  in ath10k_ahb_halt_axi_bus()
299 		ath10k_err(ar, "failed to halt axi bus: %d\n", val);  in ath10k_ahb_halt_axi_bus()
303 	ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n");  in ath10k_ahb_halt_axi_bus()
306 static void ath10k_ahb_halt_chip(struct ath10k *ar)  in ath10k_ahb_halt_chip()  argument
308 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_halt_chip()
318 		ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");  in ath10k_ahb_halt_chip()
322 	core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG);  in ath10k_ahb_halt_chip()
336 		ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n",  in ath10k_ahb_halt_chip()
341 	ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg);  in ath10k_ahb_halt_chip()
343 	val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);  in ath10k_ahb_halt_chip()
345 	ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);  in ath10k_ahb_halt_chip()
349 		ath10k_err(ar, "failed to assert core cold rst: %d\n", ret);  in ath10k_ahb_halt_chip()
354 		ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret);  in ath10k_ahb_halt_chip()
359 		ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret);  in ath10k_ahb_halt_chip()
364 		ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret);  in ath10k_ahb_halt_chip()
369 		ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret);  in ath10k_ahb_halt_chip()
375 	val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);  in ath10k_ahb_halt_chip()
377 	ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);  in ath10k_ahb_halt_chip()
379 	val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);  in ath10k_ahb_halt_chip()
381 	ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);  in ath10k_ahb_halt_chip()
385 		ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret);  in ath10k_ahb_halt_chip()
387 	ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id);  in ath10k_ahb_halt_chip()
392 	struct ath10k *ar = arg;  in ath10k_ahb_interrupt_handler()  local
394 	if (!ath10k_pci_irq_pending(ar))  in ath10k_ahb_interrupt_handler()
397 	ath10k_pci_disable_and_clear_legacy_irq(ar);  in ath10k_ahb_interrupt_handler()
398 	ath10k_pci_irq_msi_fw_mask(ar);  in ath10k_ahb_interrupt_handler()
399 	napi_schedule(&ar->napi);  in ath10k_ahb_interrupt_handler()
404 static int ath10k_ahb_request_irq_legacy(struct ath10k *ar)  in ath10k_ahb_request_irq_legacy()  argument
406 	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);  in ath10k_ahb_request_irq_legacy()
407 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_request_irq_legacy()
412 			  IRQF_SHARED, "ath10k_ahb", ar);  in ath10k_ahb_request_irq_legacy()
414 		ath10k_warn(ar, "failed to request legacy irq %d: %d\n",  in ath10k_ahb_request_irq_legacy()
423 static void ath10k_ahb_release_irq_legacy(struct ath10k *ar)  in ath10k_ahb_release_irq_legacy()  argument
425 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_release_irq_legacy()
427 	free_irq(ar_ahb->irq, ar);  in ath10k_ahb_release_irq_legacy()
430 static void ath10k_ahb_irq_disable(struct ath10k *ar)  in ath10k_ahb_irq_disable()  argument
432 	ath10k_ce_disable_interrupts(ar);  in ath10k_ahb_irq_disable()
433 	ath10k_pci_disable_and_clear_legacy_irq(ar);  in ath10k_ahb_irq_disable()
436 static int ath10k_ahb_resource_init(struct ath10k *ar)  in ath10k_ahb_resource_init()  argument
438 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_resource_init()
447 		ath10k_err(ar, "mem ioremap error\n");  in ath10k_ahb_resource_init()
457 		ath10k_err(ar, "gcc mem ioremap error\n");  in ath10k_ahb_resource_init()
465 		ath10k_err(ar, "tcsr mem ioremap error\n");  in ath10k_ahb_resource_init()
472 		ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret);  in ath10k_ahb_resource_init()
478 		ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n",  in ath10k_ahb_resource_init()
483 	ret = ath10k_ahb_clock_init(ar);  in ath10k_ahb_resource_init()
487 	ret = ath10k_ahb_rst_ctrl_init(ar);  in ath10k_ahb_resource_init()
493 		ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq);  in ath10k_ahb_resource_init()
498 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq);  in ath10k_ahb_resource_init()
500 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n",  in ath10k_ahb_resource_init()
506 	ath10k_ahb_clock_deinit(ar);  in ath10k_ahb_resource_init()
524 static void ath10k_ahb_resource_deinit(struct ath10k *ar)  in ath10k_ahb_resource_deinit()  argument
526 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_resource_deinit()
544 	ath10k_ahb_clock_deinit(ar);  in ath10k_ahb_resource_deinit()
545 	ath10k_ahb_rst_ctrl_deinit(ar);  in ath10k_ahb_resource_deinit()
548 static int ath10k_ahb_prepare_device(struct ath10k *ar)  in ath10k_ahb_prepare_device()  argument
553 	ret = ath10k_ahb_clock_enable(ar);  in ath10k_ahb_prepare_device()
555 		ath10k_err(ar, "failed to enable clocks\n");  in ath10k_ahb_prepare_device()
566 	val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV);  in ath10k_ahb_prepare_device()
567 	ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val);  in ath10k_ahb_prepare_device()
569 	ret = ath10k_ahb_release_reset(ar);  in ath10k_ahb_prepare_device()
573 	ath10k_ahb_irq_disable(ar);  in ath10k_ahb_prepare_device()
575 	ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY);  in ath10k_ahb_prepare_device()
577 	ret = ath10k_pci_wait_for_target_init(ar);  in ath10k_ahb_prepare_device()
584 	ath10k_ahb_halt_chip(ar);  in ath10k_ahb_prepare_device()
587 	ath10k_ahb_clock_disable(ar);  in ath10k_ahb_prepare_device()
592 static int ath10k_ahb_chip_reset(struct ath10k *ar)  in ath10k_ahb_chip_reset()  argument
596 	ath10k_ahb_halt_chip(ar);  in ath10k_ahb_chip_reset()
597 	ath10k_ahb_clock_disable(ar);  in ath10k_ahb_chip_reset()
599 	ret = ath10k_ahb_prepare_device(ar);  in ath10k_ahb_chip_reset()
606 static int ath10k_ahb_wake_target_cpu(struct ath10k *ar)  in ath10k_ahb_wake_target_cpu()  argument
611 	val = ath10k_ahb_read32(ar, addr);  in ath10k_ahb_wake_target_cpu()
613 	ath10k_ahb_write32(ar, addr, val);  in ath10k_ahb_wake_target_cpu()
618 static int ath10k_ahb_hif_start(struct ath10k *ar)  in ath10k_ahb_hif_start()  argument
620 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n");  in ath10k_ahb_hif_start()
622 	ath10k_core_napi_enable(ar);  in ath10k_ahb_hif_start()
623 	ath10k_ce_enable_interrupts(ar);  in ath10k_ahb_hif_start()
624 	ath10k_pci_enable_legacy_irq(ar);  in ath10k_ahb_hif_start()
626 	ath10k_pci_rx_post(ar);  in ath10k_ahb_hif_start()
631 static void ath10k_ahb_hif_stop(struct ath10k *ar)  in ath10k_ahb_hif_stop()  argument
633 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_hif_stop()
635 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n");  in ath10k_ahb_hif_stop()
637 	ath10k_ahb_irq_disable(ar);  in ath10k_ahb_hif_stop()
640 	ath10k_core_napi_sync_disable(ar);  in ath10k_ahb_hif_stop()
642 	ath10k_pci_flush(ar);  in ath10k_ahb_hif_stop()
645 static int ath10k_ahb_hif_power_up(struct ath10k *ar,  in ath10k_ahb_hif_power_up()  argument
650 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n");  in ath10k_ahb_hif_power_up()
652 	ret = ath10k_ahb_chip_reset(ar);  in ath10k_ahb_hif_power_up()
654 		ath10k_err(ar, "failed to reset chip: %d\n", ret);  in ath10k_ahb_hif_power_up()
658 	ret = ath10k_pci_init_pipes(ar);  in ath10k_ahb_hif_power_up()
660 		ath10k_err(ar, "failed to initialize CE: %d\n", ret);  in ath10k_ahb_hif_power_up()
664 	ret = ath10k_pci_init_config(ar);  in ath10k_ahb_hif_power_up()
666 		ath10k_err(ar, "failed to setup init config: %d\n", ret);  in ath10k_ahb_hif_power_up()
670 	ret = ath10k_ahb_wake_target_cpu(ar);  in ath10k_ahb_hif_power_up()
672 		ath10k_err(ar, "could not wake up target CPU: %d\n", ret);  in ath10k_ahb_hif_power_up()
679 	ath10k_pci_ce_deinit(ar);  in ath10k_ahb_hif_power_up()
684 static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)  in ath10k_ahb_qca4019_targ_cpu_to_ce_addr()  argument
688 	val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);  in ath10k_ahb_qca4019_targ_cpu_to_ce_addr()
728 	struct ath10k *ar;  in ath10k_ahb_probe()  local
743 	ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB,  in ath10k_ahb_probe()
745 	if (!ar) {  in ath10k_ahb_probe()
750 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n");  in ath10k_ahb_probe()
752 	ar_pci = ath10k_pci_priv(ar);  in ath10k_ahb_probe()
753 	ar_ahb = ath10k_ahb_priv(ar);  in ath10k_ahb_probe()
756 	platform_set_drvdata(pdev, ar);  in ath10k_ahb_probe()
758 	ret = ath10k_ahb_resource_init(ar);  in ath10k_ahb_probe()
762 	ar->dev_id = 0;  in ath10k_ahb_probe()
765 	ar_pci->ar = ar;  in ath10k_ahb_probe()
768 	ar->ce_priv = &ar_pci->ce;  in ath10k_ahb_probe()
770 	ret = ath10k_pci_setup_resource(ar);  in ath10k_ahb_probe()
772 		ath10k_err(ar, "failed to setup resource: %d\n", ret);  in ath10k_ahb_probe()
776 	ath10k_pci_init_napi(ar);  in ath10k_ahb_probe()
778 	ret = ath10k_ahb_request_irq_legacy(ar);  in ath10k_ahb_probe()
782 	ret = ath10k_ahb_prepare_device(ar);  in ath10k_ahb_probe()
786 	ath10k_pci_ce_deinit(ar);  in ath10k_ahb_probe()
789 	bus_params.chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS);  in ath10k_ahb_probe()
791 		ath10k_err(ar, "failed to get chip id\n");  in ath10k_ahb_probe()
796 	ret = ath10k_core_register(ar, &bus_params);  in ath10k_ahb_probe()
798 		ath10k_err(ar, "failed to register driver core: %d\n", ret);  in ath10k_ahb_probe()
805 	ath10k_ahb_halt_chip(ar);  in ath10k_ahb_probe()
806 	ath10k_ahb_clock_disable(ar);  in ath10k_ahb_probe()
809 	ath10k_ahb_release_irq_legacy(ar);  in ath10k_ahb_probe()
812 	ath10k_pci_release_resource(ar);  in ath10k_ahb_probe()
815 	ath10k_ahb_resource_deinit(ar);  in ath10k_ahb_probe()
818 	ath10k_core_destroy(ar);  in ath10k_ahb_probe()
825 	struct ath10k *ar = platform_get_drvdata(pdev);  in ath10k_ahb_remove()  local
827 	ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n");  in ath10k_ahb_remove()
829 	ath10k_core_unregister(ar);  in ath10k_ahb_remove()
830 	ath10k_ahb_irq_disable(ar);  in ath10k_ahb_remove()
831 	ath10k_ahb_release_irq_legacy(ar);  in ath10k_ahb_remove()
832 	ath10k_pci_release_resource(ar);  in ath10k_ahb_remove()
833 	ath10k_ahb_halt_chip(ar);  in ath10k_ahb_remove()
834 	ath10k_ahb_clock_disable(ar);  in ath10k_ahb_remove()
835 	ath10k_ahb_resource_deinit(ar);  in ath10k_ahb_remove()
836 	ath10k_core_destroy(ar);  in ath10k_ahb_remove()