Lines Matching +full:ipq4019 +full:- +full:wifi
1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
17 { .compatible = "qcom,ipq4019-wifi",
30 return &ath10k_pci_priv(ar)->ahb[0]; in ath10k_ahb_priv()
37 iowrite32(value, ar_ahb->mem + offset); in ath10k_ahb_write32()
44 return ioread32(ar_ahb->mem + offset); in ath10k_ahb_read32()
51 return ioread32(ar_ahb->gcc_mem + offset); in ath10k_ahb_gcc_read32()
58 iowrite32(value, ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_write32()
65 return ioread32(ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_read32()
75 if (ar->hw_rev == ATH10K_HW_QCA4019) in ath10k_ahb_get_num_banks()
87 dev = &ar_ahb->pdev->dev; in ath10k_ahb_clock_init()
89 ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd"); in ath10k_ahb_clock_init()
90 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) { in ath10k_ahb_clock_init()
92 PTR_ERR(ar_ahb->cmd_clk)); in ath10k_ahb_clock_init()
93 return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV; in ath10k_ahb_clock_init()
96 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref"); in ath10k_ahb_clock_init()
97 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) { in ath10k_ahb_clock_init()
99 PTR_ERR(ar_ahb->ref_clk)); in ath10k_ahb_clock_init()
100 return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV; in ath10k_ahb_clock_init()
103 ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc"); in ath10k_ahb_clock_init()
104 if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { in ath10k_ahb_clock_init()
106 PTR_ERR(ar_ahb->rtc_clk)); in ath10k_ahb_clock_init()
107 return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV; in ath10k_ahb_clock_init()
117 ar_ahb->cmd_clk = NULL; in ath10k_ahb_clock_deinit()
118 ar_ahb->ref_clk = NULL; in ath10k_ahb_clock_deinit()
119 ar_ahb->rtc_clk = NULL; in ath10k_ahb_clock_deinit()
127 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) || in ath10k_ahb_clock_enable()
128 IS_ERR_OR_NULL(ar_ahb->ref_clk) || in ath10k_ahb_clock_enable()
129 IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { in ath10k_ahb_clock_enable()
131 ret = -EIO; in ath10k_ahb_clock_enable()
135 ret = clk_prepare_enable(ar_ahb->cmd_clk); in ath10k_ahb_clock_enable()
141 ret = clk_prepare_enable(ar_ahb->ref_clk); in ath10k_ahb_clock_enable()
147 ret = clk_prepare_enable(ar_ahb->rtc_clk); in ath10k_ahb_clock_enable()
156 clk_disable_unprepare(ar_ahb->ref_clk); in ath10k_ahb_clock_enable()
159 clk_disable_unprepare(ar_ahb->cmd_clk); in ath10k_ahb_clock_enable()
169 clk_disable_unprepare(ar_ahb->cmd_clk); in ath10k_ahb_clock_disable()
171 clk_disable_unprepare(ar_ahb->ref_clk); in ath10k_ahb_clock_disable()
173 clk_disable_unprepare(ar_ahb->rtc_clk); in ath10k_ahb_clock_disable()
181 dev = &ar_ahb->pdev->dev; in ath10k_ahb_rst_ctrl_init()
183 ar_ahb->core_cold_rst = devm_reset_control_get_exclusive(dev, in ath10k_ahb_rst_ctrl_init()
185 if (IS_ERR(ar_ahb->core_cold_rst)) { in ath10k_ahb_rst_ctrl_init()
187 PTR_ERR(ar_ahb->core_cold_rst)); in ath10k_ahb_rst_ctrl_init()
188 return PTR_ERR(ar_ahb->core_cold_rst); in ath10k_ahb_rst_ctrl_init()
191 ar_ahb->radio_cold_rst = devm_reset_control_get_exclusive(dev, in ath10k_ahb_rst_ctrl_init()
193 if (IS_ERR(ar_ahb->radio_cold_rst)) { in ath10k_ahb_rst_ctrl_init()
195 PTR_ERR(ar_ahb->radio_cold_rst)); in ath10k_ahb_rst_ctrl_init()
196 return PTR_ERR(ar_ahb->radio_cold_rst); in ath10k_ahb_rst_ctrl_init()
199 ar_ahb->radio_warm_rst = devm_reset_control_get_exclusive(dev, in ath10k_ahb_rst_ctrl_init()
201 if (IS_ERR(ar_ahb->radio_warm_rst)) { in ath10k_ahb_rst_ctrl_init()
203 PTR_ERR(ar_ahb->radio_warm_rst)); in ath10k_ahb_rst_ctrl_init()
204 return PTR_ERR(ar_ahb->radio_warm_rst); in ath10k_ahb_rst_ctrl_init()
207 ar_ahb->radio_srif_rst = devm_reset_control_get_exclusive(dev, in ath10k_ahb_rst_ctrl_init()
209 if (IS_ERR(ar_ahb->radio_srif_rst)) { in ath10k_ahb_rst_ctrl_init()
211 PTR_ERR(ar_ahb->radio_srif_rst)); in ath10k_ahb_rst_ctrl_init()
212 return PTR_ERR(ar_ahb->radio_srif_rst); in ath10k_ahb_rst_ctrl_init()
215 ar_ahb->cpu_init_rst = devm_reset_control_get_exclusive(dev, in ath10k_ahb_rst_ctrl_init()
217 if (IS_ERR(ar_ahb->cpu_init_rst)) { in ath10k_ahb_rst_ctrl_init()
219 PTR_ERR(ar_ahb->cpu_init_rst)); in ath10k_ahb_rst_ctrl_init()
220 return PTR_ERR(ar_ahb->cpu_init_rst); in ath10k_ahb_rst_ctrl_init()
230 ar_ahb->core_cold_rst = NULL; in ath10k_ahb_rst_ctrl_deinit()
231 ar_ahb->radio_cold_rst = NULL; in ath10k_ahb_rst_ctrl_deinit()
232 ar_ahb->radio_warm_rst = NULL; in ath10k_ahb_rst_ctrl_deinit()
233 ar_ahb->radio_srif_rst = NULL; in ath10k_ahb_rst_ctrl_deinit()
234 ar_ahb->cpu_init_rst = NULL; in ath10k_ahb_rst_ctrl_deinit()
242 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || in ath10k_ahb_release_reset()
243 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || in ath10k_ahb_release_reset()
244 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || in ath10k_ahb_release_reset()
245 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { in ath10k_ahb_release_reset()
247 return -EINVAL; in ath10k_ahb_release_reset()
250 ret = reset_control_deassert(ar_ahb->radio_cold_rst); in ath10k_ahb_release_reset()
256 ret = reset_control_deassert(ar_ahb->radio_warm_rst); in ath10k_ahb_release_reset()
262 ret = reset_control_deassert(ar_ahb->radio_srif_rst); in ath10k_ahb_release_reset()
268 ret = reset_control_deassert(ar_ahb->cpu_init_rst); in ath10k_ahb_release_reset()
313 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) || in ath10k_ahb_halt_chip()
314 IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || in ath10k_ahb_halt_chip()
315 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || in ath10k_ahb_halt_chip()
316 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || in ath10k_ahb_halt_chip()
317 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { in ath10k_ahb_halt_chip()
347 ret = reset_control_assert(ar_ahb->core_cold_rst); in ath10k_ahb_halt_chip()
352 ret = reset_control_assert(ar_ahb->radio_cold_rst); in ath10k_ahb_halt_chip()
357 ret = reset_control_assert(ar_ahb->radio_warm_rst); in ath10k_ahb_halt_chip()
362 ret = reset_control_assert(ar_ahb->radio_srif_rst); in ath10k_ahb_halt_chip()
367 ret = reset_control_assert(ar_ahb->cpu_init_rst); in ath10k_ahb_halt_chip()
373 * deasserting wifi core reset. in ath10k_ahb_halt_chip()
383 ret = reset_control_deassert(ar_ahb->core_cold_rst); in ath10k_ahb_halt_chip()
399 napi_schedule(&ar->napi); in ath10k_ahb_interrupt_handler()
410 ret = request_irq(ar_ahb->irq, in ath10k_ahb_request_irq_legacy()
415 ar_ahb->irq, ret); in ath10k_ahb_request_irq_legacy()
418 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; in ath10k_ahb_request_irq_legacy()
427 free_irq(ar_ahb->irq, ar); in ath10k_ahb_release_irq_legacy()
443 pdev = ar_ahb->pdev; in ath10k_ahb_resource_init()
445 ar_ahb->mem = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in ath10k_ahb_resource_init()
446 if (IS_ERR(ar_ahb->mem)) { in ath10k_ahb_resource_init()
448 ret = PTR_ERR(ar_ahb->mem); in ath10k_ahb_resource_init()
452 ar_ahb->mem_len = resource_size(res); in ath10k_ahb_resource_init()
454 ar_ahb->gcc_mem = ioremap(ATH10K_GCC_REG_BASE, in ath10k_ahb_resource_init()
456 if (!ar_ahb->gcc_mem) { in ath10k_ahb_resource_init()
458 ret = -ENOMEM; in ath10k_ahb_resource_init()
462 ar_ahb->tcsr_mem = ioremap(ATH10K_TCSR_REG_BASE, in ath10k_ahb_resource_init()
464 if (!ar_ahb->tcsr_mem) { in ath10k_ahb_resource_init()
466 ret = -ENOMEM; in ath10k_ahb_resource_init()
470 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in ath10k_ahb_resource_init()
472 ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret); in ath10k_ahb_resource_init()
476 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); in ath10k_ahb_resource_init()
478 ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n", in ath10k_ahb_resource_init()
491 ar_ahb->irq = platform_get_irq_byname(pdev, "legacy"); in ath10k_ahb_resource_init()
492 if (ar_ahb->irq < 0) { in ath10k_ahb_resource_init()
493 ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq); in ath10k_ahb_resource_init()
494 ret = ar_ahb->irq; in ath10k_ahb_resource_init()
498 ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq); in ath10k_ahb_resource_init()
501 ar_ahb->mem, ar_ahb->mem_len, in ath10k_ahb_resource_init()
502 ar_ahb->gcc_mem, ar_ahb->tcsr_mem); in ath10k_ahb_resource_init()
509 iounmap(ar_ahb->tcsr_mem); in ath10k_ahb_resource_init()
512 ar_ahb->tcsr_mem = NULL; in ath10k_ahb_resource_init()
513 iounmap(ar_ahb->gcc_mem); in ath10k_ahb_resource_init()
516 ar_ahb->gcc_mem = NULL; in ath10k_ahb_resource_init()
517 devm_iounmap(&pdev->dev, ar_ahb->mem); in ath10k_ahb_resource_init()
520 ar_ahb->mem = NULL; in ath10k_ahb_resource_init()
529 dev = &ar_ahb->pdev->dev; in ath10k_ahb_resource_deinit()
531 if (ar_ahb->mem) in ath10k_ahb_resource_deinit()
532 devm_iounmap(dev, ar_ahb->mem); in ath10k_ahb_resource_deinit()
534 if (ar_ahb->gcc_mem) in ath10k_ahb_resource_deinit()
535 iounmap(ar_ahb->gcc_mem); in ath10k_ahb_resource_deinit()
537 if (ar_ahb->tcsr_mem) in ath10k_ahb_resource_deinit()
538 iounmap(ar_ahb->tcsr_mem); in ath10k_ahb_resource_deinit()
540 ar_ahb->mem = NULL; in ath10k_ahb_resource_deinit()
541 ar_ahb->gcc_mem = NULL; in ath10k_ahb_resource_deinit()
542 ar_ahb->tcsr_mem = NULL; in ath10k_ahb_resource_deinit()
638 synchronize_irq(ar_ahb->irq); in ath10k_ahb_hif_stop()
736 hw_rev = (enum ath10k_hw_rev)of_device_get_match_data(&pdev->dev); in ath10k_ahb_probe()
738 dev_err(&pdev->dev, "OF data missing\n"); in ath10k_ahb_probe()
739 return -EINVAL; in ath10k_ahb_probe()
743 ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB, in ath10k_ahb_probe()
746 dev_err(&pdev->dev, "failed to allocate core\n"); in ath10k_ahb_probe()
747 return -ENOMEM; in ath10k_ahb_probe()
755 ar_ahb->pdev = pdev; in ath10k_ahb_probe()
762 ar->dev_id = 0; in ath10k_ahb_probe()
763 ar_pci->mem = ar_ahb->mem; in ath10k_ahb_probe()
764 ar_pci->mem_len = ar_ahb->mem_len; in ath10k_ahb_probe()
765 ar_pci->ar = ar; in ath10k_ahb_probe()
766 ar_pci->ce.bus_ops = &ath10k_ahb_bus_ops; in ath10k_ahb_probe()
767 ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr; in ath10k_ahb_probe()
768 ar->ce_priv = &ar_pci->ce; in ath10k_ahb_probe()
792 ret = -ENODEV; in ath10k_ahb_probe()