Lines Matching +full:- +full:ar
1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
17 { .compatible = "qcom,ipq4019-wifi",
28 static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar) in ath10k_ahb_priv() argument
30 return &ath10k_pci_priv(ar)->ahb[0]; in ath10k_ahb_priv()
33 static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value) in ath10k_ahb_write32() argument
35 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_write32()
37 iowrite32(value, ar_ahb->mem + offset); in ath10k_ahb_write32()
40 static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset) in ath10k_ahb_read32() argument
42 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_read32()
44 return ioread32(ar_ahb->mem + offset); in ath10k_ahb_read32()
47 static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset) in ath10k_ahb_gcc_read32() argument
49 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_gcc_read32()
51 return ioread32(ar_ahb->gcc_mem + offset); in ath10k_ahb_gcc_read32()
54 static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value) in ath10k_ahb_tcsr_write32() argument
56 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_tcsr_write32()
58 iowrite32(value, ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_write32()
61 static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset) in ath10k_ahb_tcsr_read32() argument
63 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_tcsr_read32()
65 return ioread32(ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_read32()
68 static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr) in ath10k_ahb_soc_read32() argument
70 return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr); in ath10k_ahb_soc_read32()
73 static int ath10k_ahb_get_num_banks(struct ath10k *ar) in ath10k_ahb_get_num_banks() argument
75 if (ar->hw_rev == ATH10K_HW_QCA4019) in ath10k_ahb_get_num_banks()
78 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); in ath10k_ahb_get_num_banks()
82 static int ath10k_ahb_clock_init(struct ath10k *ar) in ath10k_ahb_clock_init() argument
84 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_clock_init()
87 dev = &ar_ahb->pdev->dev; in ath10k_ahb_clock_init()
89 ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd"); in ath10k_ahb_clock_init()
90 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) { in ath10k_ahb_clock_init()
91 ath10k_err(ar, "failed to get cmd clk: %ld\n", in ath10k_ahb_clock_init()
92 PTR_ERR(ar_ahb->cmd_clk)); in ath10k_ahb_clock_init()
93 return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV; in ath10k_ahb_clock_init()
96 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref"); in ath10k_ahb_clock_init()
97 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) { in ath10k_ahb_clock_init()
98 ath10k_err(ar, "failed to get ref clk: %ld\n", in ath10k_ahb_clock_init()
99 PTR_ERR(ar_ahb->ref_clk)); in ath10k_ahb_clock_init()
100 return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV; in ath10k_ahb_clock_init()
103 ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc"); in ath10k_ahb_clock_init()
104 if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { in ath10k_ahb_clock_init()
105 ath10k_err(ar, "failed to get rtc clk: %ld\n", in ath10k_ahb_clock_init()
106 PTR_ERR(ar_ahb->rtc_clk)); in ath10k_ahb_clock_init()
107 return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV; in ath10k_ahb_clock_init()
113 static void ath10k_ahb_clock_deinit(struct ath10k *ar) in ath10k_ahb_clock_deinit() argument
115 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_clock_deinit()
117 ar_ahb->cmd_clk = NULL; in ath10k_ahb_clock_deinit()
118 ar_ahb->ref_clk = NULL; in ath10k_ahb_clock_deinit()
119 ar_ahb->rtc_clk = NULL; in ath10k_ahb_clock_deinit()
122 static int ath10k_ahb_clock_enable(struct ath10k *ar) in ath10k_ahb_clock_enable() argument
124 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_clock_enable()
127 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) || in ath10k_ahb_clock_enable()
128 IS_ERR_OR_NULL(ar_ahb->ref_clk) || in ath10k_ahb_clock_enable()
129 IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { in ath10k_ahb_clock_enable()
130 ath10k_err(ar, "clock(s) is/are not initialized\n"); in ath10k_ahb_clock_enable()
131 ret = -EIO; in ath10k_ahb_clock_enable()
135 ret = clk_prepare_enable(ar_ahb->cmd_clk); in ath10k_ahb_clock_enable()
137 ath10k_err(ar, "failed to enable cmd clk: %d\n", ret); in ath10k_ahb_clock_enable()
141 ret = clk_prepare_enable(ar_ahb->ref_clk); in ath10k_ahb_clock_enable()
143 ath10k_err(ar, "failed to enable ref clk: %d\n", ret); in ath10k_ahb_clock_enable()
147 ret = clk_prepare_enable(ar_ahb->rtc_clk); in ath10k_ahb_clock_enable()
149 ath10k_err(ar, "failed to enable rtc clk: %d\n", ret); in ath10k_ahb_clock_enable()
156 clk_disable_unprepare(ar_ahb->ref_clk); in ath10k_ahb_clock_enable()
159 clk_disable_unprepare(ar_ahb->cmd_clk); in ath10k_ahb_clock_enable()
165 static void ath10k_ahb_clock_disable(struct ath10k *ar) in ath10k_ahb_clock_disable() argument
167 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_clock_disable()
169 clk_disable_unprepare(ar_ahb->cmd_clk); in ath10k_ahb_clock_disable()
171 clk_disable_unprepare(ar_ahb->ref_clk); in ath10k_ahb_clock_disable()
173 clk_disable_unprepare(ar_ahb->rtc_clk); in ath10k_ahb_clock_disable()
176 static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar) in ath10k_ahb_rst_ctrl_init() argument
178 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_rst_ctrl_init()
181 dev = &ar_ahb->pdev->dev; in ath10k_ahb_rst_ctrl_init()
183 ar_ahb->core_cold_rst = devm_reset_control_get_exclusive(dev, in ath10k_ahb_rst_ctrl_init()
185 if (IS_ERR(ar_ahb->core_cold_rst)) { in ath10k_ahb_rst_ctrl_init()
186 ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n", in ath10k_ahb_rst_ctrl_init()
187 PTR_ERR(ar_ahb->core_cold_rst)); in ath10k_ahb_rst_ctrl_init()
188 return PTR_ERR(ar_ahb->core_cold_rst); in ath10k_ahb_rst_ctrl_init()
191 ar_ahb->radio_cold_rst = devm_reset_control_get_exclusive(dev, in ath10k_ahb_rst_ctrl_init()
193 if (IS_ERR(ar_ahb->radio_cold_rst)) { in ath10k_ahb_rst_ctrl_init()
194 ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n", in ath10k_ahb_rst_ctrl_init()
195 PTR_ERR(ar_ahb->radio_cold_rst)); in ath10k_ahb_rst_ctrl_init()
196 return PTR_ERR(ar_ahb->radio_cold_rst); in ath10k_ahb_rst_ctrl_init()
199 ar_ahb->radio_warm_rst = devm_reset_control_get_exclusive(dev, in ath10k_ahb_rst_ctrl_init()
201 if (IS_ERR(ar_ahb->radio_warm_rst)) { in ath10k_ahb_rst_ctrl_init()
202 ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n", in ath10k_ahb_rst_ctrl_init()
203 PTR_ERR(ar_ahb->radio_warm_rst)); in ath10k_ahb_rst_ctrl_init()
204 return PTR_ERR(ar_ahb->radio_warm_rst); in ath10k_ahb_rst_ctrl_init()
207 ar_ahb->radio_srif_rst = devm_reset_control_get_exclusive(dev, in ath10k_ahb_rst_ctrl_init()
209 if (IS_ERR(ar_ahb->radio_srif_rst)) { in ath10k_ahb_rst_ctrl_init()
210 ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n", in ath10k_ahb_rst_ctrl_init()
211 PTR_ERR(ar_ahb->radio_srif_rst)); in ath10k_ahb_rst_ctrl_init()
212 return PTR_ERR(ar_ahb->radio_srif_rst); in ath10k_ahb_rst_ctrl_init()
215 ar_ahb->cpu_init_rst = devm_reset_control_get_exclusive(dev, in ath10k_ahb_rst_ctrl_init()
217 if (IS_ERR(ar_ahb->cpu_init_rst)) { in ath10k_ahb_rst_ctrl_init()
218 ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n", in ath10k_ahb_rst_ctrl_init()
219 PTR_ERR(ar_ahb->cpu_init_rst)); in ath10k_ahb_rst_ctrl_init()
220 return PTR_ERR(ar_ahb->cpu_init_rst); in ath10k_ahb_rst_ctrl_init()
226 static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar) in ath10k_ahb_rst_ctrl_deinit() argument
228 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_rst_ctrl_deinit()
230 ar_ahb->core_cold_rst = NULL; in ath10k_ahb_rst_ctrl_deinit()
231 ar_ahb->radio_cold_rst = NULL; in ath10k_ahb_rst_ctrl_deinit()
232 ar_ahb->radio_warm_rst = NULL; in ath10k_ahb_rst_ctrl_deinit()
233 ar_ahb->radio_srif_rst = NULL; in ath10k_ahb_rst_ctrl_deinit()
234 ar_ahb->cpu_init_rst = NULL; in ath10k_ahb_rst_ctrl_deinit()
237 static int ath10k_ahb_release_reset(struct ath10k *ar) in ath10k_ahb_release_reset() argument
239 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_release_reset()
242 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || in ath10k_ahb_release_reset()
243 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || in ath10k_ahb_release_reset()
244 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || in ath10k_ahb_release_reset()
245 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { in ath10k_ahb_release_reset()
246 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); in ath10k_ahb_release_reset()
247 return -EINVAL; in ath10k_ahb_release_reset()
250 ret = reset_control_deassert(ar_ahb->radio_cold_rst); in ath10k_ahb_release_reset()
252 ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret); in ath10k_ahb_release_reset()
256 ret = reset_control_deassert(ar_ahb->radio_warm_rst); in ath10k_ahb_release_reset()
258 ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret); in ath10k_ahb_release_reset()
262 ret = reset_control_deassert(ar_ahb->radio_srif_rst); in ath10k_ahb_release_reset()
264 ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret); in ath10k_ahb_release_reset()
268 ret = reset_control_deassert(ar_ahb->cpu_init_rst); in ath10k_ahb_release_reset()
270 ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret); in ath10k_ahb_release_reset()
277 static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg, in ath10k_ahb_halt_axi_bus() argument
284 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); in ath10k_ahb_halt_axi_bus()
286 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); in ath10k_ahb_halt_axi_bus()
291 val = ath10k_ahb_tcsr_read32(ar, haltack_reg); in ath10k_ahb_halt_axi_bus()
299 ath10k_err(ar, "failed to halt axi bus: %d\n", val); in ath10k_ahb_halt_axi_bus()
303 ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n"); in ath10k_ahb_halt_axi_bus()
306 static void ath10k_ahb_halt_chip(struct ath10k *ar) in ath10k_ahb_halt_chip() argument
308 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_halt_chip()
313 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) || in ath10k_ahb_halt_chip()
314 IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || in ath10k_ahb_halt_chip()
315 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || in ath10k_ahb_halt_chip()
316 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || in ath10k_ahb_halt_chip()
317 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { in ath10k_ahb_halt_chip()
318 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); in ath10k_ahb_halt_chip()
322 core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG); in ath10k_ahb_halt_chip()
336 ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n", in ath10k_ahb_halt_chip()
341 ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg); in ath10k_ahb_halt_chip()
343 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); in ath10k_ahb_halt_chip()
345 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); in ath10k_ahb_halt_chip()
347 ret = reset_control_assert(ar_ahb->core_cold_rst); in ath10k_ahb_halt_chip()
349 ath10k_err(ar, "failed to assert core cold rst: %d\n", ret); in ath10k_ahb_halt_chip()
352 ret = reset_control_assert(ar_ahb->radio_cold_rst); in ath10k_ahb_halt_chip()
354 ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret); in ath10k_ahb_halt_chip()
357 ret = reset_control_assert(ar_ahb->radio_warm_rst); in ath10k_ahb_halt_chip()
359 ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret); in ath10k_ahb_halt_chip()
362 ret = reset_control_assert(ar_ahb->radio_srif_rst); in ath10k_ahb_halt_chip()
364 ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret); in ath10k_ahb_halt_chip()
367 ret = reset_control_assert(ar_ahb->cpu_init_rst); in ath10k_ahb_halt_chip()
369 ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret); in ath10k_ahb_halt_chip()
375 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); in ath10k_ahb_halt_chip()
377 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); in ath10k_ahb_halt_chip()
379 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); in ath10k_ahb_halt_chip()
381 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); in ath10k_ahb_halt_chip()
383 ret = reset_control_deassert(ar_ahb->core_cold_rst); in ath10k_ahb_halt_chip()
385 ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret); in ath10k_ahb_halt_chip()
387 ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id); in ath10k_ahb_halt_chip()
392 struct ath10k *ar = arg; in ath10k_ahb_interrupt_handler() local
394 if (!ath10k_pci_irq_pending(ar)) in ath10k_ahb_interrupt_handler()
397 ath10k_pci_disable_and_clear_legacy_irq(ar); in ath10k_ahb_interrupt_handler()
398 ath10k_pci_irq_msi_fw_mask(ar); in ath10k_ahb_interrupt_handler()
399 napi_schedule(&ar->napi); in ath10k_ahb_interrupt_handler()
404 static int ath10k_ahb_request_irq_legacy(struct ath10k *ar) in ath10k_ahb_request_irq_legacy() argument
406 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); in ath10k_ahb_request_irq_legacy()
407 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_request_irq_legacy()
410 ret = request_irq(ar_ahb->irq, in ath10k_ahb_request_irq_legacy()
412 IRQF_SHARED, "ath10k_ahb", ar); in ath10k_ahb_request_irq_legacy()
414 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", in ath10k_ahb_request_irq_legacy()
415 ar_ahb->irq, ret); in ath10k_ahb_request_irq_legacy()
418 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; in ath10k_ahb_request_irq_legacy()
423 static void ath10k_ahb_release_irq_legacy(struct ath10k *ar) in ath10k_ahb_release_irq_legacy() argument
425 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_release_irq_legacy()
427 free_irq(ar_ahb->irq, ar); in ath10k_ahb_release_irq_legacy()
430 static void ath10k_ahb_irq_disable(struct ath10k *ar) in ath10k_ahb_irq_disable() argument
432 ath10k_ce_disable_interrupts(ar); in ath10k_ahb_irq_disable()
433 ath10k_pci_disable_and_clear_legacy_irq(ar); in ath10k_ahb_irq_disable()
436 static int ath10k_ahb_resource_init(struct ath10k *ar) in ath10k_ahb_resource_init() argument
438 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_resource_init()
443 pdev = ar_ahb->pdev; in ath10k_ahb_resource_init()
445 ar_ahb->mem = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in ath10k_ahb_resource_init()
446 if (IS_ERR(ar_ahb->mem)) { in ath10k_ahb_resource_init()
447 ath10k_err(ar, "mem ioremap error\n"); in ath10k_ahb_resource_init()
448 ret = PTR_ERR(ar_ahb->mem); in ath10k_ahb_resource_init()
452 ar_ahb->mem_len = resource_size(res); in ath10k_ahb_resource_init()
454 ar_ahb->gcc_mem = ioremap(ATH10K_GCC_REG_BASE, in ath10k_ahb_resource_init()
456 if (!ar_ahb->gcc_mem) { in ath10k_ahb_resource_init()
457 ath10k_err(ar, "gcc mem ioremap error\n"); in ath10k_ahb_resource_init()
458 ret = -ENOMEM; in ath10k_ahb_resource_init()
462 ar_ahb->tcsr_mem = ioremap(ATH10K_TCSR_REG_BASE, in ath10k_ahb_resource_init()
464 if (!ar_ahb->tcsr_mem) { in ath10k_ahb_resource_init()
465 ath10k_err(ar, "tcsr mem ioremap error\n"); in ath10k_ahb_resource_init()
466 ret = -ENOMEM; in ath10k_ahb_resource_init()
470 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in ath10k_ahb_resource_init()
472 ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret); in ath10k_ahb_resource_init()
476 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); in ath10k_ahb_resource_init()
478 ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n", in ath10k_ahb_resource_init()
483 ret = ath10k_ahb_clock_init(ar); in ath10k_ahb_resource_init()
487 ret = ath10k_ahb_rst_ctrl_init(ar); in ath10k_ahb_resource_init()
491 ar_ahb->irq = platform_get_irq_byname(pdev, "legacy"); in ath10k_ahb_resource_init()
492 if (ar_ahb->irq < 0) { in ath10k_ahb_resource_init()
493 ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq); in ath10k_ahb_resource_init()
494 ret = ar_ahb->irq; in ath10k_ahb_resource_init()
498 ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq); in ath10k_ahb_resource_init()
500 ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n", in ath10k_ahb_resource_init()
501 ar_ahb->mem, ar_ahb->mem_len, in ath10k_ahb_resource_init()
502 ar_ahb->gcc_mem, ar_ahb->tcsr_mem); in ath10k_ahb_resource_init()
506 ath10k_ahb_clock_deinit(ar); in ath10k_ahb_resource_init()
509 iounmap(ar_ahb->tcsr_mem); in ath10k_ahb_resource_init()
512 ar_ahb->tcsr_mem = NULL; in ath10k_ahb_resource_init()
513 iounmap(ar_ahb->gcc_mem); in ath10k_ahb_resource_init()
516 ar_ahb->gcc_mem = NULL; in ath10k_ahb_resource_init()
517 devm_iounmap(&pdev->dev, ar_ahb->mem); in ath10k_ahb_resource_init()
520 ar_ahb->mem = NULL; in ath10k_ahb_resource_init()
524 static void ath10k_ahb_resource_deinit(struct ath10k *ar) in ath10k_ahb_resource_deinit() argument
526 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_resource_deinit()
529 dev = &ar_ahb->pdev->dev; in ath10k_ahb_resource_deinit()
531 if (ar_ahb->mem) in ath10k_ahb_resource_deinit()
532 devm_iounmap(dev, ar_ahb->mem); in ath10k_ahb_resource_deinit()
534 if (ar_ahb->gcc_mem) in ath10k_ahb_resource_deinit()
535 iounmap(ar_ahb->gcc_mem); in ath10k_ahb_resource_deinit()
537 if (ar_ahb->tcsr_mem) in ath10k_ahb_resource_deinit()
538 iounmap(ar_ahb->tcsr_mem); in ath10k_ahb_resource_deinit()
540 ar_ahb->mem = NULL; in ath10k_ahb_resource_deinit()
541 ar_ahb->gcc_mem = NULL; in ath10k_ahb_resource_deinit()
542 ar_ahb->tcsr_mem = NULL; in ath10k_ahb_resource_deinit()
544 ath10k_ahb_clock_deinit(ar); in ath10k_ahb_resource_deinit()
545 ath10k_ahb_rst_ctrl_deinit(ar); in ath10k_ahb_resource_deinit()
548 static int ath10k_ahb_prepare_device(struct ath10k *ar) in ath10k_ahb_prepare_device() argument
553 ret = ath10k_ahb_clock_enable(ar); in ath10k_ahb_prepare_device()
555 ath10k_err(ar, "failed to enable clocks\n"); in ath10k_ahb_prepare_device()
566 val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV); in ath10k_ahb_prepare_device()
567 ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val); in ath10k_ahb_prepare_device()
569 ret = ath10k_ahb_release_reset(ar); in ath10k_ahb_prepare_device()
573 ath10k_ahb_irq_disable(ar); in ath10k_ahb_prepare_device()
575 ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); in ath10k_ahb_prepare_device()
577 ret = ath10k_pci_wait_for_target_init(ar); in ath10k_ahb_prepare_device()
584 ath10k_ahb_halt_chip(ar); in ath10k_ahb_prepare_device()
587 ath10k_ahb_clock_disable(ar); in ath10k_ahb_prepare_device()
592 static int ath10k_ahb_chip_reset(struct ath10k *ar) in ath10k_ahb_chip_reset() argument
596 ath10k_ahb_halt_chip(ar); in ath10k_ahb_chip_reset()
597 ath10k_ahb_clock_disable(ar); in ath10k_ahb_chip_reset()
599 ret = ath10k_ahb_prepare_device(ar); in ath10k_ahb_chip_reset()
606 static int ath10k_ahb_wake_target_cpu(struct ath10k *ar) in ath10k_ahb_wake_target_cpu() argument
611 val = ath10k_ahb_read32(ar, addr); in ath10k_ahb_wake_target_cpu()
613 ath10k_ahb_write32(ar, addr, val); in ath10k_ahb_wake_target_cpu()
618 static int ath10k_ahb_hif_start(struct ath10k *ar) in ath10k_ahb_hif_start() argument
620 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n"); in ath10k_ahb_hif_start()
622 ath10k_core_napi_enable(ar); in ath10k_ahb_hif_start()
623 ath10k_ce_enable_interrupts(ar); in ath10k_ahb_hif_start()
624 ath10k_pci_enable_legacy_irq(ar); in ath10k_ahb_hif_start()
626 ath10k_pci_rx_post(ar); in ath10k_ahb_hif_start()
631 static void ath10k_ahb_hif_stop(struct ath10k *ar) in ath10k_ahb_hif_stop() argument
633 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_hif_stop()
635 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n"); in ath10k_ahb_hif_stop()
637 ath10k_ahb_irq_disable(ar); in ath10k_ahb_hif_stop()
638 synchronize_irq(ar_ahb->irq); in ath10k_ahb_hif_stop()
640 ath10k_core_napi_sync_disable(ar); in ath10k_ahb_hif_stop()
642 ath10k_pci_flush(ar); in ath10k_ahb_hif_stop()
645 static int ath10k_ahb_hif_power_up(struct ath10k *ar, in ath10k_ahb_hif_power_up() argument
650 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n"); in ath10k_ahb_hif_power_up()
652 ret = ath10k_ahb_chip_reset(ar); in ath10k_ahb_hif_power_up()
654 ath10k_err(ar, "failed to reset chip: %d\n", ret); in ath10k_ahb_hif_power_up()
658 ret = ath10k_pci_init_pipes(ar); in ath10k_ahb_hif_power_up()
660 ath10k_err(ar, "failed to initialize CE: %d\n", ret); in ath10k_ahb_hif_power_up()
664 ret = ath10k_pci_init_config(ar); in ath10k_ahb_hif_power_up()
666 ath10k_err(ar, "failed to setup init config: %d\n", ret); in ath10k_ahb_hif_power_up()
670 ret = ath10k_ahb_wake_target_cpu(ar); in ath10k_ahb_hif_power_up()
672 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); in ath10k_ahb_hif_power_up()
679 ath10k_pci_ce_deinit(ar); in ath10k_ahb_hif_power_up()
684 static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) in ath10k_ahb_qca4019_targ_cpu_to_ce_addr() argument
688 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); in ath10k_ahb_qca4019_targ_cpu_to_ce_addr()
728 struct ath10k *ar; in ath10k_ahb_probe() local
736 hw_rev = (enum ath10k_hw_rev)of_device_get_match_data(&pdev->dev); in ath10k_ahb_probe()
738 dev_err(&pdev->dev, "OF data missing\n"); in ath10k_ahb_probe()
739 return -EINVAL; in ath10k_ahb_probe()
743 ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB, in ath10k_ahb_probe()
745 if (!ar) { in ath10k_ahb_probe()
746 dev_err(&pdev->dev, "failed to allocate core\n"); in ath10k_ahb_probe()
747 return -ENOMEM; in ath10k_ahb_probe()
750 ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n"); in ath10k_ahb_probe()
752 ar_pci = ath10k_pci_priv(ar); in ath10k_ahb_probe()
753 ar_ahb = ath10k_ahb_priv(ar); in ath10k_ahb_probe()
755 ar_ahb->pdev = pdev; in ath10k_ahb_probe()
756 platform_set_drvdata(pdev, ar); in ath10k_ahb_probe()
758 ret = ath10k_ahb_resource_init(ar); in ath10k_ahb_probe()
762 ar->dev_id = 0; in ath10k_ahb_probe()
763 ar_pci->mem = ar_ahb->mem; in ath10k_ahb_probe()
764 ar_pci->mem_len = ar_ahb->mem_len; in ath10k_ahb_probe()
765 ar_pci->ar = ar; in ath10k_ahb_probe()
766 ar_pci->ce.bus_ops = &ath10k_ahb_bus_ops; in ath10k_ahb_probe()
767 ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr; in ath10k_ahb_probe()
768 ar->ce_priv = &ar_pci->ce; in ath10k_ahb_probe()
770 ret = ath10k_pci_setup_resource(ar); in ath10k_ahb_probe()
772 ath10k_err(ar, "failed to setup resource: %d\n", ret); in ath10k_ahb_probe()
776 ath10k_pci_init_napi(ar); in ath10k_ahb_probe()
778 ret = ath10k_ahb_request_irq_legacy(ar); in ath10k_ahb_probe()
782 ret = ath10k_ahb_prepare_device(ar); in ath10k_ahb_probe()
786 ath10k_pci_ce_deinit(ar); in ath10k_ahb_probe()
789 bus_params.chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS); in ath10k_ahb_probe()
791 ath10k_err(ar, "failed to get chip id\n"); in ath10k_ahb_probe()
792 ret = -ENODEV; in ath10k_ahb_probe()
796 ret = ath10k_core_register(ar, &bus_params); in ath10k_ahb_probe()
798 ath10k_err(ar, "failed to register driver core: %d\n", ret); in ath10k_ahb_probe()
805 ath10k_ahb_halt_chip(ar); in ath10k_ahb_probe()
806 ath10k_ahb_clock_disable(ar); in ath10k_ahb_probe()
809 ath10k_ahb_release_irq_legacy(ar); in ath10k_ahb_probe()
812 ath10k_pci_release_resource(ar); in ath10k_ahb_probe()
815 ath10k_ahb_resource_deinit(ar); in ath10k_ahb_probe()
818 ath10k_core_destroy(ar); in ath10k_ahb_probe()
825 struct ath10k *ar = platform_get_drvdata(pdev); in ath10k_ahb_remove() local
827 ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n"); in ath10k_ahb_remove()
829 ath10k_core_unregister(ar); in ath10k_ahb_remove()
830 ath10k_ahb_irq_disable(ar); in ath10k_ahb_remove()
831 ath10k_ahb_release_irq_legacy(ar); in ath10k_ahb_remove()
832 ath10k_pci_release_resource(ar); in ath10k_ahb_remove()
833 ath10k_ahb_halt_chip(ar); in ath10k_ahb_remove()
834 ath10k_ahb_clock_disable(ar); in ath10k_ahb_remove()
835 ath10k_ahb_resource_deinit(ar); in ath10k_ahb_remove()
836 ath10k_core_destroy(ar); in ath10k_ahb_remove()