Lines Matching +full:0 +full:x8030
34 #define AR_CR_LP_RXE 0x00000004 // Receive LPQ enable
35 #define AR_CR_HP_RXE 0x00000008 // Receive HPQ enable
36 #define AR_CR_RXD 0x00000020 // Receive disable
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
42 #define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words
43 #define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words
44 #define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words
45 #define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words
46 #define AR_CFG_SWRG 0x00000010 // byteswap register access data words
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
48 #define AR_CFG_PHOK 0x00000100 // PHY OK status
49 #define AR_CFG_CLK_GATE_DIS 0x00000400 // Clock gating disable
50 #define AR_CFG_EEBS 0x00000200 // EEPROM busy
51 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue…
53 #define AR_CFG_MISSING_TX_INTR_FIX_ENABLE 0x00080000 // See EV 61133 for details.
57 #define AR_RXBP_THRESH_HP 0x0000000f
58 #define AR_RXBP_THRESH_HP_S 0
59 #define AR_RXBP_THRESH_LP 0x00003f00
67 #define AR_MIRT_VAL 0x0000ffff // in uS
72 #define AR_IER_ENABLE 0x00000001 // Global interrupt enable
73 #define AR_IER_DISABLE 0x00000000 // Global interrupt disable
77 #define AR_TIMT_LAST 0x0000ffff // Last packet threshold
78 #define AR_TIMT_LAST_S 0
79 #define AR_TIMT_FIRST 0xffff0000 // First packet threshold
84 #define AR_RIMT_LAST 0x0000ffff // Last packet threshold
85 #define AR_RIMT_LAST_S 0
86 #define AR_RIMT_FIRST 0xffff0000 // First packet threshold
89 #define AR_DMASIZE_4B 0x00000000 // DMA size 4 bytes (TXCFG + RXCFG)
90 #define AR_DMASIZE_8B 0x00000001 // DMA size 8 bytes
91 #define AR_DMASIZE_16B 0x00000002 // DMA size 16 bytes
92 #define AR_DMASIZE_32B 0x00000003 // DMA size 32 bytes
93 #define AR_DMASIZE_64B 0x00000004 // DMA size 64 bytes
94 #define AR_DMASIZE_128B 0x00000005 // DMA size 128 bytes
95 #define AR_DMASIZE_256B 0x00000006 // DMA size 256 bytes
96 #define AR_DMASIZE_512B 0x00000007 // DMA size 512 bytes
100 #define AR_TXCFG_DMASZ_MASK 0x00000007
101 #define AR_TXCFG_DMASZ_4B 0
109 #define AR_FTRIG 0x000003F0 // Mask for Frame trigger level
111 #define AR_FTRIG_IMMED 0x00000000 // bytes in PCU TX FIFO before air
112 #define AR_FTRIG_64B 0x00000010 // default
113 #define AR_FTRIG_128B 0x00000020
114 #define AR_FTRIG_192B 0x00000030
115 #define AR_FTRIG_256B 0x00000040 // 5 bits total
116 #define AR_FTRIG_512B 0x00000080 // 5 bits total
117 #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800
118 #define AR_TXCFG_RTS_FAIL_EXCESSIVE_RETRIES 0x00080000
123 #define AR_RXCFG_CHIRP 0x00000008 // Only double chirps
124 #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame
125 #define AR_RXCFG_DMASZ_MASK 0x00000007
126 #define AR_RXCFG_DMASZ_4B 0
141 #define AR_MIBC_COW 0x00000001 // counter overflow warning
142 #define AR_MIBC_FMC 0x00000002 // freeze MIB counters
143 #define AR_MIBC_CMC 0x00000004 // clear MIB counters
144 #define AR_MIBC_MCS 0x00000008 // MIB counter strobe increment all
148 #define AR_TOPS_MASK 0x0000FFFF // Mask for timeout prescale
152 #define AR_RXNPTO_MASK 0x000003FF // Mask for no frame received timeout
156 #define AR_TXNPTO_MASK 0x000003FF // Mask for no frame transmitted timeout
157 #define AR_TXNPTO_QCU_MASK 0x000FFC00 // Mask indicating the set of QCUs
163 #define AR_RPGTO_MASK 0x000003FF // Mask for receive frame gap timeout
167 #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 //force msb to 10 to ahb
168 #define AR_MACMISC_DMA_OBS 0x000001E0 // Mask for DMA observation bus mux select
170 #define AR_MACMISC_DMA_OBS_LINE_0 0 // Observation DMA line 0
179 #define AR_MACMISC_MISC_OBS 0x00000E00 // Mask for MISC observation bus mux select
181 #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 // Mask for MAC observation bus mux select (lsb)
183 #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 // Mask for MAC observation bus mux select (msb)
189 #define AR_INTCFG_REQ 0x00000001 // Interrupt request flag
192 #define AR_INTCFG_MSI_RXOK 0x00000000 // Rx interrupt for MSI logic is RXOK
193 #define AR_INTCFG_MSI_RXINTM 0x00000004 // Rx interrupt for MSI logic is RXINTM
194 #define AR_INTCFG_MSI_RXMINTR 0x00000006 // Rx interrupt for MSI logic is RXMINTR
195 #define AR_INTCFG_MSI_TXOK 0x00000000 // Rx interrupt for MSI logic is TXOK
196 #define AR_INTCFG_MSI_TXINTM 0x00000010 // Rx interrupt for MSI logic is TXINTM
197 #define AR_INTCFG_MSI_TXMINTR 0x00000018 // Rx interrupt for MSI logic is TXMINTR
201 #define AR_DATABUF_MASK 0x00000FFF
205 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs)
206 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs)
211 #define AR_GTTM_USEC 0x00000001 // usec strobe
212 #define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle
213 #define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low
214 #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe
218 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs)
219 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs)
224 #define AR_RXDP_LP_SZ_MASK 0x0000007f
225 #define AR_RXDP_LP_SZ_S 0
226 #define AR_RXDP_HP_SZ_MASK 0x00001f00
238 #define AR_ISR_HP_RXOK 0x00000001 // At least one frame rx on high-priority queue sans errors
239 #define AR_ISR_LP_RXOK 0x00000002 // At least one frame rx on low-priority queue sans errors
240 #define AR_ISR_RXERR 0x00000004 // Receive error interrupt
241 #define AR_ISR_RXNOPKT 0x00000008 // No frame received within timeout clock
242 #define AR_ISR_RXEOL 0x00000010 // Received descriptor empty interrupt
243 #define AR_ISR_RXORN 0x00000020 // Receive FIFO overrun interrupt
244 #define AR_ISR_TXOK 0x00000040 // Transmit okay interrupt
245 #define AR_ISR_TXERR 0x00000100 // Transmit error interrupt
246 #define AR_ISR_TXNOPKT 0x00000200 // No frame transmitted interrupt
247 #define AR_ISR_TXEOL 0x00000400 // Transmit descriptor empty interrupt
248 #define AR_ISR_TXURN 0x00000800 // Transmit FIFO underrun interrupt
249 #define AR_ISR_MIB 0x00001000 // MIB interrupt - see MIBC
250 #define AR_ISR_SWI 0x00002000 // Software interrupt
251 #define AR_ISR_RXPHY 0x00004000 // PHY receive error interrupt
252 #define AR_ISR_RXKCM 0x00008000 // Key-cache miss interrupt
253 #define AR_ISR_SWBA 0x00010000 // Software beacon alert interrupt
254 #define AR_ISR_BRSSI 0x00020000 // Beacon threshold interrupt
255 #define AR_ISR_BMISS 0x00040000 // Beacon missed interrupt
256 #define AR_ISR_TXMINTR 0x00080000 // Maximum interrupt transmit rate
257 #define AR_ISR_BNR 0x00100000 // Beacon not ready interrupt
258 #define AR_ISR_RXCHIRP 0x00200000 // Phy received a 'chirp'
259 #define AR_ISR_HCFPOLL 0x00400000 // Received directed HCF poll
260 #define AR_ISR_BCNMISC 0x00800000 // CST, GTT, TIM, CABEND, DTIMSYNC, BCNTO, CABTO,
262 #define AR_ISR_TIM 0x00800000 // TIM interrupt
263 #define AR_ISR_RXMINTR 0x01000000 // Maximum interrupt receive rate
264 #define AR_ISR_QCBROVF 0x02000000 // QCU CBR overflow interrupt
265 #define AR_ISR_QCBRURN 0x04000000 // QCU CBR underrun interrupt
266 #define AR_ISR_QTRIG 0x08000000 // QCU scheduling trigger interrupt
267 #define AR_ISR_GENTMR 0x10000000 // OR of generic timer bits in ISR 5
268 #define AR_ISR_HCFTO 0x20000000 // HCF poll timeout
269 #define AR_ISR_TXINTM 0x40000000 // Tx interrupt after mitigation
270 #define AR_ISR_RXINTM 0x80000000 // Rx interrupt after mitigation
272 /* MAC Secondary interrupt status register 0 */
274 #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9)
275 #define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9)
279 #define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9)
280 #define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9)
281 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9)
282 #define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9)
286 #define AR_ISR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9)
287 #define AR_ISR_S2_BBPANIC 0x00010000 // Panic watchdog IRQ from BB
288 #define AR_ISR_S2_CST 0x00400000 // Carrier sense timeout
289 #define AR_ISR_S2_GTT 0x00800000 // Global transmit timeout
290 #define AR_ISR_S2_TIM 0x01000000 // TIM
291 #define AR_ISR_S2_CABEND 0x02000000 // CABEND
292 #define AR_ISR_S2_DTIMSYNC 0x04000000 // DTIMSYNC
293 #define AR_ISR_S2_BCNTO 0x08000000 // BCNTO
294 #define AR_ISR_S2_CABTO 0x10000000 // CABTO
295 #define AR_ISR_S2_DTIM 0x20000000 // DTIM
296 #define AR_ISR_S2_TSFOOR 0x40000000 // Rx TSF out of range
297 #define AR_ISR_S2_TBTT_TIME 0x80000000 // TBTT-referenced timer
301 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9)
302 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9)
306 #define AR_ISR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9)
307 #define AR_ISR_S4_RESV0 0xFFFFFC00 // Reserved
311 #define AR_ISR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7)
312 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00 // Mask for timer threshold(0-7)
313 #define AR_ISR_S5_TIM_TIMER 0x00000010 // TIM Timer ISR
314 #define AR_ISR_S5_DTIM_TIMER 0x00000020 // DTIM Timer ISR
315 #define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 // ISR for generic timer trigger 7
316 #define AR_ISR_S5_GENTIMER_TRIG_S 0
317 #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 // ISR for generic timer threshold 7
322 #define AR_IMR_RXOK_HP 0x00000001 // Receive high-priority interrupt enable mask
323 #define AR_IMR_RXOK_LP 0x00000002 // Receive low-priority interrupt enable mask
324 #define AR_IMR_RXERR 0x00000004 // Receive error interrupt
325 #define AR_IMR_RXNOPKT 0x00000008 // No frame received within timeout clock
326 #define AR_IMR_RXEOL 0x00000010 // Received descriptor empty interrupt
327 #define AR_IMR_RXORN 0x00000020 // Receive FIFO overrun interrupt
328 #define AR_IMR_TXOK 0x00000040 // Transmit okay interrupt
329 #define AR_IMR_TXERR 0x00000100 // Transmit error interrupt
330 #define AR_IMR_TXNOPKT 0x00000200 // No frame transmitted interrupt
331 #define AR_IMR_TXEOL 0x00000400 // Transmit descriptor empty interrupt
332 #define AR_IMR_TXURN 0x00000800 // Transmit FIFO underrun interrupt
333 #define AR_IMR_MIB 0x00001000 // MIB interrupt - see MIBC
334 #define AR_IMR_SWI 0x00002000 // Software interrupt
335 #define AR_IMR_RXPHY 0x00004000 // PHY receive error interrupt
336 #define AR_IMR_RXKCM 0x00008000 // Key-cache miss interrupt
337 #define AR_IMR_SWBA 0x00010000 // Software beacon alert interrupt
338 #define AR_IMR_BRSSI 0x00020000 // Beacon threshold interrupt
339 #define AR_IMR_BMISS 0x00040000 // Beacon missed interrupt
340 #define AR_IMR_TXMINTR 0x00080000 // Maximum interrupt transmit rate
341 #define AR_IMR_BNR 0x00100000 // BNR interrupt
342 #define AR_IMR_RXCHIRP 0x00200000 // RXCHIRP interrupt
343 #define AR_IMR_BCNMISC 0x00800000 // Venice: BCNMISC
344 #define AR_IMR_TIM 0x00800000 // TIM interrupt
345 #define AR_IMR_RXMINTR 0x01000000 // Maximum interrupt receive rate
346 #define AR_IMR_QCBROVF 0x02000000 // QCU CBR overflow interrupt
347 #define AR_IMR_QCBRURN 0x04000000 // QCU CBR underrun interrupt
348 #define AR_IMR_QTRIG 0x08000000 // QCU scheduling trigger interrupt
349 #define AR_IMR_GENTMR 0x10000000 // Generic timer interrupt
350 #define AR_IMR_TXINTM 0x40000000 // Tx interrupt after mitigation
351 #define AR_IMR_RXINTM 0x80000000 // Rx interrupt after mitigation
353 /* MAC Secondary interrupt mask register 0 */
355 #define AR_IMR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9)
356 #define AR_IMR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9)
360 #define AR_IMR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9)
361 #define AR_IMR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9)
362 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9)
363 #define AR_IMR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9)
367 #define AR_IMR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9)
368 #define AR_IMR_S2_QCU_TXURN_S 0 // Shift for TXURN (QCU 0-9)
369 #define AR_IMR_S2_BBPANIC 0x00010000 // Panic watchdog IRQ from BB
370 #define AR_IMR_S2_CST 0x00400000 // Carrier sense timeout
371 #define AR_IMR_S2_GTT 0x00800000 // Global transmit timeout
372 #define AR_IMR_S2_TIM 0x01000000 // TIM
373 #define AR_IMR_S2_CABEND 0x02000000 // CABEND
374 #define AR_IMR_S2_DTIMSYNC 0x04000000 // DTIMSYNC
375 #define AR_IMR_S2_BCNTO 0x08000000 // BCNTO
376 #define AR_IMR_S2_CABTO 0x10000000 // CABTO
377 #define AR_IMR_S2_DTIM 0x20000000 // DTIM
378 #define AR_IMR_S2_TSFOOR 0x40000000 // TSF out of range
382 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9)
383 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9)
384 #define AR_IMR_S3_QCU_QCBRURN_S 16 // Shift for QCBRURN (QCU 0-9)
388 #define AR_IMR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9)
389 #define AR_IMR_S4_RESV0 0xFFFFFC00 // Reserved
393 #define AR_IMR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7)
394 #define AR_IMR_S5_TIMER_THRESH 0x0000FF00 // Mask for timer threshold(0-7)
395 #define AR_IMR_S5_TIM_TIMER 0x00000010 // TIM Timer Mask
396 #define AR_IMR_S5_DTIM_TIMER 0x00000020 // DTIM Timer Mask
397 #define AR_IMR_S5_GENTIMER7 0x00000080 // Mask for timer 7 trigger
398 #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80 // Mask for generic timer trigger 7-15
399 #define AR_IMR_S5_GENTIMER_TRIG_S 0
400 #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000 // Mask for generic timer threshold 7-15
408 /* MAC Secondary interrupt status register 0 - shadow copy */
410 #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9)
411 #define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9)
415 #define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9)
416 #define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9)
417 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9)
418 #define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9)
441 #define AR_DMADBG_RX_STATE 0x00000F00 // Mask for Rx DMA State machine
449 #define AR_NUM_QCU 10 // Only use QCU 0-9 for forward QCU compatibility
450 #define AR_QCU_0 0x0001
451 #define AR_QCU_1 0x0002
452 #define AR_QCU_2 0x0004
453 #define AR_QCU_3 0x0008
454 #define AR_QCU_4 0x0010
455 #define AR_QCU_5 0x0020
456 #define AR_QCU_6 0x0040
457 #define AR_QCU_7 0x0080
458 #define AR_QCU_8 0x0100
459 #define AR_QCU_9 0x0200
474 #define AR_Q_TXE_M 0x000003FF // Mask for TXE (QCU 0-9)
478 #define AR_Q_TXD_M 0x000003FF // Mask for TXD (QCU 0-9)
483 #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF // Mask for CBR interval (us)
484 #define AR_Q_CBRCFG_INTERVAL_S 0 // Shift for CBR interval (us)
485 #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 // Mask for CBR overflow threshold
491 #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF // Mask for ready_time duration (us)
492 #define AR_Q_RDYTIMECFG_DURATION_S 0 // Shift for ready_time duration (us)
493 #define AR_Q_RDYTIMECFG_EN 0x01000000 // ready_time enable
497 #define AR_Q_ONESHOTARM_SC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_SC (QCU 0-9)
498 #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 // Reserved
502 #define AR_Q_ONESHOTARM_CC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_CC (QCU 0-9)
503 #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 // Reserved
508 #define AR_Q_MISC_FSP 0x0000000F // Mask for Frame Scheduling Policy
509 #define AR_Q_MISC_FSP_S 0
510 #define AR_Q_MISC_FSP_ASAP 0 // ASAP
516 #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 // OneShot enable
517 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 // Disable CBR expired counter incr (empty q)
518 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 // Disable CBR expired counter incr (empty bea…
519 #define AR_Q_MISC_BEACON_USE 0x00000080 // Beacon use indication
520 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 // CBR expired counter limit enable
521 #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 // Enable TXE cleared on ready_time expired or…
522 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 // Reset CBR expired counter
523 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 // DCU frame early termination request control
524 #define AR_Q_MISC_RESV0 0xFFFFF000 // Reserved
529 #define AR_Q_STS_PEND_FR_CNT 0x00000003 // Mask for Pending Frame Count
530 #define AR_Q_STS_RESV0 0x000000FC // Reserved
531 #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 // Mask for CBR expired counter
532 #define AR_Q_STS_RESV1 0xFFFF0000 // Reserved
536 #define AR_Q_RDYTIMESHDN_M 0x000003FF // Mask for ReadyTimeShutdown status (QCU 0-9)
543 #define AR_MAC_QCU_EOL_DUR_CAL_EN 0x000003FF // Adjusts EOL for frame duration (QCU 0-9)
544 #define AR_MAC_QCU_EOL_DUR_CAL_EN_S 0
553 #define AR_DCU_0 0x0001
554 #define AR_DCU_1 0x0002
555 #define AR_DCU_2 0x0004
556 #define AR_DCU_3 0x0008
557 #define AR_DCU_4 0x0010
558 #define AR_DCU_5 0x0020
559 #define AR_DCU_6 0x0040
560 #define AR_DCU_7 0x0080
561 #define AR_DCU_8 0x0100
562 #define AR_DCU_9 0x0200
567 #define AR_D_QCUMASK 0x000003FF // Mask for QCU Mask (QCU 0-9)
568 #define AR_D_QCUMASK_RESV0 0xFFFFFC00 // Reserved
577 #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF // Mask for SIFS duration (core clocks)
578 #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF // Reserved
582 #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF // Mask for Slot duration (core clocks)
583 #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 // Reserved
588 #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F // Mask for frame short retry limit
589 #define AR_D_RETRY_LIMIT_FR_SH_S 0 // Shift for frame short retry limit
590 #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 // Mask for station short retry limit
592 #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 // Mask for station short retry limit
594 #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 // Reserved
598 #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF // Mask for Slot duration (core clocks)
599 #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 // Reserved
604 #define AR_D_CHNTIME_DUR 0x000FFFFF // Mask for ChannelTime duration (us)
605 #define AR_D_CHNTIME_DUR_S 0 // Shift for ChannelTime duration (us)
606 #define AR_D_CHNTIME_EN 0x00100000 // ChannelTime enable
607 #define AR_D_CHNTIME_RESV0 0xFFE00000 // Reserved
611 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 // Mask forLFSR slice select
612 #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 // Turbo mode indication
613 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 // Mask for DCU arbiter delay
614 #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 // Random LSFR slice disable
615 #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 // Slot transmission window length mask
616 #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 // Force transmission on slot boundaries
617 #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 // Ignore backoff
622 #define AR_D_MISC_BKOFF_THRESH 0x0000003F // Mask for Backoff threshold setting
623 #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 // End of tx series station RTS/data failure count…
624 #define AR_D_MISC_CW_RESET_EN 0x00000080 // End of tx series CW reset enable
625 #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 // Fragment Starvation Policy
626 #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 // Backoff during a frag burst
627 #define AR_D_MISC_CW_BKOFF_EN 0x00001000 // Use binary exponential CW backoff
628 #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 // Mask for Virtual collision handling policy
630 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 // Normal
632 #define AR_D_MISC_BEACON_USE 0x00010000 // Beacon use indication
633 #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 // Mask for DCU arbiter lockout control
635 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 // No lockout
638 #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 // DCU arbiter lockout ignore control
639 #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 // Sequence number increment disable
640 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 // Post-frame backoff disable
641 #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 // Virtual coll. handling policy
642 #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 // Initiate Retry procedure on Blown IFS
643 #define AR_D_MISC_RESV0 0xFF000000 // Reserved
650 #define AR_D_TXPSE_CTRL 0x000003FF // Mask of DCUs to pause (DCUs 0-9)
651 #define AR_D_TXPSE_RESV0 0x0000FC00 // Reserved
652 #define AR_D_TXPSE_STATUS 0x00010000 // Transmit pause status
653 #define AR_D_TXPSE_RESV1 0xFFFE0000 // Reserved
660 #define AR_D_TXSLOTMASK_NUM 0x0000000F // slot numbers
666 #define AR_D_LCL_IFS_CWMIN 0x000003FF // Mask for CW_MIN
667 #define AR_D_LCL_IFS_CWMIN_S 0 // Shift for CW_MIN
668 #define AR_D_LCL_IFS_CWMAX 0x000FFC00 // Mask for CW_MAX
670 #define AR_D_LCL_IFS_AIFS 0x0FF00000 // Mask for AIFS
674 * maximum supported AIFS value is 0xfc. Setting the AIFS value
675 * to 0xfd 0xfe or 0xff will not work correctly and will cause
678 #define AR_D_LCL_IFS_RESV0 0xF0000000 // Reserved
681 #define AR_CFG_LED 0x1f04 /* LED control */
682 #define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */
683 #define AR_CFG_SCLK_RATE_IND_S 0
684 #define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */
685 #define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */
686 #define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */
687 #define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */
688 #define AR_CFG_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */
689 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */
690 #define AR_CFG_LED_MODE_SEL 0x00000380 /* LED mode: bits 7..9 */
692 #define AR_CFG_LED_POWER 0x00000280 /* Power LED: bit 9=1, bit 7=<LED State> */
694 #define AR_CFG_LED_NETWORK 0x00000300 /* Network LED: bit 9=1, bit 8=<LED State> */
696 #define AR_CFG_LED_MODE_PROP 0x0 /* Blink prop to filtered tx/rx */
697 #define AR_CFG_LED_MODE_RPROP 0x1 /* Blink prop to unfiltered tx/rx */
698 #define AR_CFG_LED_MODE_SPLIT 0x2 /* Blink power for tx/net for rx */
699 #define AR_CFG_LED_MODE_RAND 0x3 /* Blink randomly */
700 #define AR_CFG_LED_MODE_POWER_OFF 0x4 /* Power LED OFF */
701 #define AR_CFG_LED_MODE_POWER_ON 0x5 /* Power LED ON */
702 #define AR_CFG_LED_MODE_NETWORK_OFF 0x4 /* Network LED OFF */
703 #define AR_CFG_LED_MODE_NETWORK_ON 0x6 /* Network LED ON */
704 #define AR_CFG_LED_ASSOC_CTL 0x00000c00 /* LED control: bits 10..11 */
706 #define AR_CFG_LED_ASSOC_NONE 0x0 /* 0x00000000: STA is not associated or trying */
707 #define AR_CFG_LED_ASSOC_ACTIVE 0x1 /* 0x00000400: STA is associated */
708 #define AR_CFG_LED_ASSOC_PENDING 0x2 /* 0x00000800: STA is trying to associate */
710 #define AR_CFG_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode: bit 3 */
713 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select: bits 4..6 */
716 #define AR_MAC_SLEEP 0x1f00
717 #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 // mac is now awake
718 #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 // mac is now asleep
732 #define AR_RC_AHB 0x00000001 // ahb reset
733 #define AR_RC_APB 0x00000002 // apb reset
734 #define AR_RC_HOSTIF 0x00000100 // host interface reset
747 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 //for wow
754 #define AR_PCIE_PM_CTRL_ENA 0x00080000
755 #define AR_PMCTRL_WOW_PME_CLR 0x00200000 /* Clear WoW event */
756 #define AR_PMCTRL_HOST_PME_EN 0x00400000 /* Send OOB WAKE_L on WoW event */
757 #define AR_PMCTRL_D3COLD_VAUX 0x00800000
758 #define AR_PMCTRL_PWR_STATE_MASK 0x0F000000 /* Power State Mask */
759 #define AR_PMCTRL_PWR_STATE_D1D3 0x0F000000 /* Activate D1 and D3 */
760 #define AR_PMCTRL_PWR_STATE_D0 0x08000000 /* Activate D0 */
761 #define AR_PMCTRL_PWR_PM_CTRL_ENA 0x00008000 /* Enable power management */
762 #define AR_PMCTRL_AUX_PWR_DET 0x10000000 /* Puts Chip in L2 state */
767 #define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF
768 #define AR_HOST_TIMEOUT_APB_CNTR_S 0
769 #define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000
773 #define AR_EEPROM_ABSENT 0x00000100
774 #define AR_EEPROM_CORRUPT 0x00000200
775 #define AR_EEPROM_PROT_MASK 0x03FFFC00
779 #define EEPROM_PROTECT_RP_0_31 0x0001
780 #define EEPROM_PROTECT_WP_0_31 0x0002
781 #define EEPROM_PROTECT_RP_32_63 0x0004
782 #define EEPROM_PROTECT_WP_32_63 0x0008
783 #define EEPROM_PROTECT_RP_64_127 0x0010
784 #define EEPROM_PROTECT_WP_64_127 0x0020
785 #define EEPROM_PROTECT_RP_128_191 0x0040
786 #define EEPROM_PROTECT_WP_128_191 0x0080
787 #define EEPROM_PROTECT_RP_192_255 0x0100
788 #define EEPROM_PROTECT_WP_192_255 0x0200
789 #define EEPROM_PROTECT_RP_256_511 0x0400
790 #define EEPROM_PROTECT_WP_256_511 0x0800
791 #define EEPROM_PROTECT_RP_512_1023 0x1000
792 #define EEPROM_PROTECT_WP_512_1023 0x2000
793 #define EEPROM_PROTECT_RP_1024_2047 0x4000
794 #define EEPROM_PROTECT_WP_1024_2047 0x8000
797 #define AR_RFSILENT_FORCE 0x01
800 #define AR_SREV_ID 0x000000FF /* Mask to read SREV info */
801 #define AR_SREV_VERSION 0x000000F0 /* Mask for Chip version */
803 #define AR_SREV_REVISION 0x00000007 /* Mask for Chip revision level */
805 /* Sowl extension to SREV. AR_SREV_ID must be 0xFF */
806 #define AR_SREV_ID2 0xFFFFFFFF /* Mask to read SREV info */
807 #define AR_SREV_VERSION2 0xFFFC0000 /* Mask for Chip version */
809 #define AR_SREV_TYPE2 0x0003F000 /* Mask for Chip type */
811 #define AR_SREV_TYPE2_CHAIN 0x00001000 /* chain mode (1 = 3 chains, 0 = 2 chains)…
812 #define AR_SREV_TYPE2_HOST_MODE 0x00002000 /* host mode (1 = PCI, 0 = PCIe) */
814 #define AR_SREV_TYPE2_JUPITER_CHAIN 0x00001000 /* chain (1 = 2 chains, 0 = 1 chain) */
815 #define AR_SREV_TYPE2_JUPITER_BAND 0x00002000 /* band (1 = dual band, 0 = single band) …
816 #define AR_SREV_TYPE2_JUPITER_BT 0x00004000 /* BT (1 = shared BT, 0 = no BT) */
817 #define AR_SREV_TYPE2_JUPITER_MODE 0x00008000 /* mode (1 = premium, 0 = standard) */
818 #define AR_SREV_REVISION2 0x00000F00
821 #define AR_RADIO_SREV_MAJOR 0xf0
822 #define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */
823 #define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */
824 #define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */
825 #define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */
827 #if 0
828 #define AR_AHB_MODE 0x4024 // ahb mode for dma
829 #define AR_AHB_EXACT_WR_EN 0x00000000 // write exact bytes
830 #define AR_AHB_BUF_WR_EN 0x00000001 // buffer write upto cacheline
831 #define AR_AHB_EXACT_RD_EN 0x00000000 // read exact bytes
832 #define AR_AHB_CACHELINE_RD_EN 0x00000002 // read upto end of cacheline
833 #define AR_AHB_PREFETCH_RD_EN 0x00000004 // prefetch upto page boundary
834 #define AR_AHB_PAGE_SIZE_1K 0x00000000 // set page-size as 1k
835 #define AR_AHB_PAGE_SIZE_2K 0x00000008 // set page-size as 2k
836 #define AR_AHB_PAGE_SIZE_4K 0x00000010 // set page-size as 4k
839 #define AR_INTR_RTC_IRQ 0x00000001 // rtc in shutdown state
840 #define AR_INTR_MAC_IRQ 0x00000002 // pending mac interrupt
841 #if 0
846 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 // eeprom protected area access
847 #define AR_INTR_MAC_AWAKE 0x00020000 // mac is awake
848 #define AR_INTR_MAC_ASLEEP 0x00040000 // mac is asleep
850 #define AR_INTR_SPURIOUS 0xFFFFFFFF
857 #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31
864 AR9300_INTR_SYNC_RTC_IRQ = 0x00000001,
865 AR9300_INTR_SYNC_MAC_IRQ = 0x00000002,
866 AR9300_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004,
867 AR9300_INTR_SYNC_APB_TIMEOUT = 0x00000008,
868 AR9300_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010,
869 AR9300_INTR_SYNC_HOST1_FATAL = 0x00000020,
870 AR9300_INTR_SYNC_HOST1_PERR = 0x00000040,
871 AR9300_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080,
872 AR9300_INTR_SYNC_RADM_CPL_EP = 0x00000100,
873 AR9300_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200,
874 AR9300_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400,
875 AR9300_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800,
876 AR9300_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000,
877 AR9300_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000,
878 AR9300_INTR_SYNC_PM_ACCESS = 0x00004000,
879 AR9300_INTR_SYNC_MAC_AWAKE = 0x00008000,
880 AR9300_INTR_SYNC_MAC_ASLEEP = 0x00010000,
881 AR9300_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000,
882 AR9300_INTR_SYNC_ALL = 0x0003FFFF,
899 AR9300_INTR_SYNC_SPURIOUS = 0xFFFFFFFF,
902 AR9340_INTR_SYNC_RTC_IRQ = 0x00000001,
903 AR9340_INTR_SYNC_MAC_IRQ = 0x00000002,
904 AR9340_INTR_SYNC_HOST1_FATAL = 0x00000004,
905 AR9340_INTR_SYNC_HOST1_PERR = 0x00000008,
906 AR9340_INTR_SYNC_LOCAL_TIMEOUT = 0x00000010,
907 AR9340_INTR_SYNC_MAC_ASLEEP = 0x00000020,
908 AR9340_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00000040,
915 AR9340_INTR_SYNC_SPURIOUS = 0xFFFFFFFF,
919 #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 // asynchronous interrupt mask: bits 18..31
921 #define AR_INTR_ASYNC_MASK_MCI 0x00000080
925 #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 // synchronous interrupt mask: bits 18..31
929 #define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 // GPIO interrupts: bits 18..31
930 #define AR_INTR_ASYNC_CAUSE_MCI 0x00000080
934 #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31
936 #define AR_INTR_ASYNC_ENABLE_MCI 0x00000080
942 #define AR_PCIE_PM_CTRL_ENA 0x00080000
944 #define AR93XX_NUM_GPIO 16 // 0 to 15
947 #define AR_GPIO_OUT_VAL 0x000FFFF
948 #define AR_GPIO_OUT_VAL_S 0
951 #define AR_GPIO_IN_VAL 0x000FFFF
952 #define AR_GPIO_IN_VAL_S 0
955 #define AR_GPIO_OE_OUT_DRV 0x3 // 2 bit field mask, shifted by 2*bitpos
956 #define AR_GPIO_OE_OUT_DRV_NO 0x0 // tristate
957 #define AR_GPIO_OE_OUT_DRV_LOW 0x1 // drive if low
958 #define AR_GPIO_OE_OUT_DRV_HI 0x2 // drive if high
959 #define AR_GPIO_OE_OUT_DRV_ALL 0x3 // drive always
964 #define AR_GPIO_INTR_POL_VAL 0x0001FFFF // bits 16:0 correspond to gpio 16:0
965 #define AR_GPIO_INTR_POL_VAL_S 0 // bits 16:0 correspond to gpio 16:0
968 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 // default value for bt_priority_async
970 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 // default value for bt_frequency_async
972 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 // default value for bt_active_async
974 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 // default value for rfsilent_bb_l
976 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 // 0 == set bt_priority_async to defaul…
978 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB 0x00000800 // 0 == set bt_frequency_async to defau…
980 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 // 0 == set bt_active_async to default,…
982 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 // 0 == set rfsilent_bb_l to default, 1…
984 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
985 #define AR_GPIO_JTAG_DISABLE 0x00020000 // 1 == disable JTAG
988 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 /* bits 8..11: input mux for BT priorit…
990 #define AR_GPIO_INPUT_MUX1_BT_FREQUENCY 0x0000f000 /* bits 12..15: input mux for BT freque…
992 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 /* bits 16..19: input mux for BT active…
996 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f // bits 0..3: input mux for clk25 input
997 #define AR_GPIO_INPUT_MUX2_CLK25_S 0 // bits 0..3: input mux for clk25 input
998 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 // bits 4..7: input mux for rfsilent_bb…
1000 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 // bits 8..11: input mux for RTC Reset …
1007 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
1014 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
1015 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
1016 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
1017 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
1018 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
1019 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
1022 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
1023 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
1025 #define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0 0x1d
1026 #define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1 0x1e
1027 #define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 0x1b
1032 #define AR_GPIO_OUTPUT_MUX_AS_SWCOM3 0x26
1034 #define AR_ENABLE_SMARTANTENNA 0x00000001
1046 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
1047 #define AR_EEPROM_STATUS_DATA_VAL_S 0
1048 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
1049 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000
1050 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
1051 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
1058 #define AR_GPIO_PDPU_OPTION 0x03
1059 #define AR_GPIO_PULL_DOWN 0x02
1066 #define AR_PCIE_MSI_ENABLE 0x00000001
1067 #define AR_PCIE_MSI_HW_DBI_WR_EN 0x02000000
1068 #define AR_PCIE_MSI_HW_INT_PENDING_ADDR 0xFFA0C1FF // bits 8..11: value must be 0x5060
1069 #define AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64 0xFFA0C9FF // bits 8..11: value must be 0x5064
1072 #define AR_INTR_PRIO_TX 0x00000001
1073 #define AR_INTR_PRIO_RXLP 0x00000002
1074 #define AR_INTR_PRIO_RXHP 0x00000004
1079 #define AR_ENT_OTP_DUAL_BAND_DISABLE 0x00010000
1080 #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
1081 #define AR_ENT_OTP_5MHZ_DISABLE 0x00040000
1082 #define AR_ENT_OTP_10MHZ_DISABLE 0x00080000
1083 #define AR_ENT_OTP_49GHZ_DISABLE 0x00100000
1084 #define AR_ENT_OTP_LOOPBACK_DISABLE 0x00200000
1085 #define AR_ENT_OTP_TPC_PERF_DISABLE 0x00400000
1086 #define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x00800000
1087 #define AR_ENT_OTP_SPECTRAL_PRECISION 0x03000000
1104 #define AR_RTC_RC_M 0x00000003
1105 #define AR_RTC_RC_MAC_WARM 0x00000001
1106 #define AR_RTC_RC_MAC_COLD 0x00000002
1111 /* Reg Control 0 */
1116 #define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001
1129 #define AR_RTC_PLL_DIV 0x000003ff
1130 #define AR_RTC_PLL_DIV_S 0
1131 #define AR_RTC_PLL_REFDIV 0x00003C00
1133 #define AR_RTC_PLL_CLKSEL 0x0000C000
1135 #define AR_RTC_PLL_BYPASS 0x00010000
1175 #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */
1179 #define AR_RTC_STATUS_M 0x0000003f
1180 #define AR_RTC_STATUS_SHUTDOWN 0x00000001
1181 #define AR_RTC_STATUS_ON 0x00000002
1182 #define AR_RTC_STATUS_SLEEP 0x00000004
1183 #define AR_RTC_STATUS_WAKEUP 0x00000008
1184 #define AR_RTC_STATUS_SLEEP_ACCESS 0x00000010
1185 #define AR_RTC_STATUS_PLL_CHANGING 0x00000020
1189 #define AR_RTC_FORCE_DERIVED_CLK 0x00000002
1190 #define AR_RTC_FORCE_SWREG_PRD 0x00000004
1191 #define AR_RTC_PCIE_RST_PWDN_EN 0x00000008
1195 #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */
1196 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */
1216 #define AR_AN_RF2G1_CH0 0x7810
1217 #define AR_AN_RF2G1_CH0_OB 0x03800000
1219 #define AR_AN_RF2G1_CH0_DB 0x1C000000
1222 #define AR_AN_RF5G1_CH0 0x7818
1223 #define AR_AN_RF5G1_CH0_OB5 0x00070000
1225 #define AR_AN_RF5G1_CH0_DB5 0x00380000
1228 #define AR_AN_RF2G1_CH1 0x7834
1229 #define AR_AN_RF2G1_CH1_OB 0x03800000
1231 #define AR_AN_RF2G1_CH1_DB 0x1C000000
1234 #define AR_AN_RF5G1_CH1 0x783C
1235 #define AR_AN_RF5G1_CH1_OB5 0x00070000
1237 #define AR_AN_RF5G1_CH1_DB5 0x00380000
1240 #define AR_AN_TOP2 0x7894
1241 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000
1243 #define AR_AN_TOP2_LOCALBIAS 0x00200000
1245 #define AR_AN_TOP2_PWDCLKIND 0x00400000
1248 #define AR_AN_SYNTH9 0x7868
1249 #define AR_AN_SYNTH9_REFDIVA 0xf8000000
1253 #define AR9285_AN_RF2G1 0x7820
1254 #define AR9285_AN_RF2G2 0x7824
1256 #define AR9285_AN_RF2G3 0x7828
1257 #define AR9285_AN_RF2G3_OB_0 0x00E00000
1259 #define AR9285_AN_RF2G3_OB_1 0x001C0000
1261 #define AR9285_AN_RF2G3_OB_2 0x00038000
1263 #define AR9285_AN_RF2G3_OB_3 0x00007000
1265 #define AR9285_AN_RF2G3_OB_4 0x00000E00
1268 #define AR9285_AN_RF2G3_DB1_0 0x000001C0
1270 #define AR9285_AN_RF2G3_DB1_1 0x00000038
1272 #define AR9285_AN_RF2G3_DB1_2 0x00000007
1273 #define AR9285_AN_RF2G3_DB1_2_S 0
1274 #define AR9285_AN_RF2G4 0x782C
1275 #define AR9285_AN_RF2G4_DB1_3 0xE0000000
1277 #define AR9285_AN_RF2G4_DB1_4 0x1C000000
1280 #define AR9285_AN_RF2G4_DB2_0 0x03800000
1282 #define AR9285_AN_RF2G4_DB2_1 0x00700000
1284 #define AR9285_AN_RF2G4_DB2_2 0x000E0000
1286 #define AR9285_AN_RF2G4_DB2_3 0x0001C000
1288 #define AR9285_AN_RF2G4_DB2_4 0x00003800
1291 #define AR9285_AN_RF2G6 0x7834
1292 #define AR9285_AN_RF2G7 0x7838
1293 #define AR9285_AN_RF2G9 0x7840
1294 #define AR9285_AN_RXTXBB1 0x7854
1295 #define AR9285_AN_TOP2 0x7868
1297 #define AR9285_AN_TOP3 0x786c
1298 #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C
1301 #define AR9285_AN_TOP4 0x7870
1302 #define AR9285_AN_TOP4_DEFAULT 0x10142c00
1316 #define AR_STA_ID1_SADH_MASK 0x0000FFFF // Mask for 16 msb of MAC addr
1317 #define AR_STA_ID1_STA_AP 0x00010000 // Device is AP
1318 #define AR_STA_ID1_ADHOC 0x00020000 // Device is ad-hoc
1319 #define AR_STA_ID1_PWR_SAV 0x00040000 // Power save in generated frames
1320 #define AR_STA_ID1_KSRCHDIS 0x00080000 // Key search disable
1321 #define AR_STA_ID1_PCF 0x00100000 // Observe PCF
1322 #define AR_STA_ID1_USE_DEFANT 0x00200000 // Use default antenna
1323 #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 // Update default ant w/TX antenna
1324 #define AR_STA_ID1_RTS_USE_DEF 0x00800000 // Use default antenna to send RTS
1325 #define AR_STA_ID1_ACKCTS_6MB 0x01000000 // Use 6Mb/s rate for ACK & CTS
1326 #define AR_STA_ID1_BASE_RATE_11B 0x02000000 // Use 11b base rate for ACK & CTS
1327 #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 // default ant for generated frames
1328 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 // Enable Michael
1329 #define AR_STA_ID1_KSRCH_MODE 0x10000000 // Look-up unique key when !keyID
1330 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 // Don't replace seq num
1331 #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 // IV endian-ness in CBC nonce
1332 #define AR_STA_ID1_MCAST_KSRCH 0x80000000 // Adhoc key search enable
1338 #define AR_BSS_ID1_U16 0x0000FFFF // Mask for upper 16 bits of BSSID
1339 #define AR_BSS_ID1_AID 0x07FF0000 // Mask for association ID
1361 #define AR_BCN_RSSI_AVE_VAL 0x00000FFF // Beacon RSSI value
1362 #define AR_BCN_RSSI_AVE_VAL_S 0
1366 #define AR_TIME_OUT_ACK 0x00003FFF // Mask for ACK time-out
1367 #define AR_TIME_OUT_ACK_S 0
1368 #define AR_TIME_OUT_CTS 0x3FFF0000 // Mask for CTS time-out
1373 #define AR_RSSI_THR_VAL 0x000000FF // Beacon RSSI warning threshold
1374 #define AR_RSSI_THR_VAL_S 0
1375 #define AR_RSSI_THR_BM_THR 0x0000FF00 // Mask for Missed beacon threshold
1377 #define AR_RSSI_BCN_WEIGHT 0x1F000000 // RSSI average weight
1379 #define AR_RSSI_BCN_RSSI_RST 0x20000000 // Reset RSSI value
1383 #define AR_USEC_USEC 0x000000FF // Mask for clock cycles in 1 usec
1384 #define AR_USEC_USEC_S 0 // Shift for clock cycles in 1 usec
1385 #define AR_USEC_TX_LAT 0x007FC000 // tx latency to start of SIGNAL (usec)
1387 #define AR_USEC_RX_LAT 0x1F800000 // rx latency to start of SIGNAL (usec)
1393 #define AR_USEC_RX_LATENCY 0x1f800000
1402 #define AR_USEC_TX_LATENCY 0x007fc000
1420 #define AR_RESET_TSF_ONCE 0x01000000 // reset tsf once ; self-clears bit
1421 #define AR_RESET_TSF2_ONCE 0x02000000 // reset tsf2 once ; self-clears bit
1424 #define AR_CFP_PERIOD 0x8024 /* MAC CFP Interval (TU/msec) */
1425 #define AR_TIMER0 0x8028 /* MAC Next beacon time (TU/msec) */
1426 #define AR_TIMER1 0x802c /* MAC DMA beacon alert time (1/8 TU) */
1427 #define AR_TIMER2 0x8030 /* MAC Software beacon alert (1/8 TU) */
1428 #define AR_TIMER3 0x8034 /* MAC ATIM window time */
1432 #define AR_CFP_VAL 0x0000FFFF // CFP value in uS
1436 #define AR_RX_FILTER_ALL 0x00000000 // Disallow all frames
1437 #define AR_RX_UCAST 0x00000001 // Allow unicast frames
1438 #define AR_RX_MCAST 0x00000002 // Allow multicast frames
1439 #define AR_RX_BCAST 0x00000004 // Allow broadcast frames
1440 #define AR_RX_CONTROL 0x00000008 // Allow control frames
1441 #define AR_RX_BEACON 0x00000010 // Allow beacon frames
1442 #define AR_RX_PROM 0x00000020 // Promiscuous mode all packets
1443 #define AR_RX_PROBE_REQ 0x00000080 // Any probe request frameA
1444 #define AR_RX_MY_BEACON 0x00000200 // Any beacon frame with matching BSSID
1445 #define AR_RX_COMPR_BAR 0x00000400 // Compressed directed block ack request
1446 #define AR_RX_COMPR_BA 0x00000800 // Compressed directed block ack
1447 #define AR_RX_UNCOM_BA_BAR 0x00001000 // Uncompressed directed BA or BAR
1448 #define AR_RX_HWBCNPROC_EN 0x00020000 // Enable hw beacon processing (see AR_HWBCNPROC1)
1449 #define AR_RX_CONTROL_WRAPPER 0x00080000 // Control wrapper. Jupiter only.
1450 #define AR_RX_4ADDRESS 0x00100000 // 4-Address frames
1462 #define AR_DIAG_CACHE_ACK 0x00000001 // disable ACK when no valid key
1463 #define AR_DIAG_ACK_DIS 0x00000002 // disable ACK generation
1464 #define AR_DIAG_CTS_DIS 0x00000004 // disable CTS generation
1465 #define AR_DIAG_ENCRYPT_DIS 0x00000008 // disable encryption
1466 #define AR_DIAG_DECRYPT_DIS 0x00000010 // disable decryption
1467 #define AR_DIAG_RX_DIS 0x00000020 // disable receive
1468 #define AR_DIAG_LOOP_BACK 0x00000040 // enable loopback
1469 #define AR_DIAG_CORR_FCS 0x00000080 // corrupt FCS
1470 #define AR_DIAG_CHAN_INFO 0x00000100 // dump channel info
1471 #define AR_DIAG_FRAME_NV0 0x00020000 // accept w/protocol version !0
1472 #define AR_DIAG_OBS_PT_SEL1 0x000C0000 // observation point select
1474 #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 // force rx_clear high
1475 #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 // ignore virtual carrier sense
1476 #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 // force channel idle high
1477 #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 // use framed and ~wait_wep if 0
1478 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 // dual chain channel info
1479 #define AR_DIAG_RX_ABORT 0x02000000 // abort rx
1480 #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 // saturate cycle cnts (no shift)
1481 #define AR_DIAG_OBS_PT_SEL2 0x08000000 // Mask for observation point sel
1483 #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 // force rx_clear (ctl) low (i.e. busy)
1484 #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 // force rx_clear (ext) low (i.e. busy)
1504 #define AR_TST_ADDAC_TST_MODE 0x1
1505 #define AR_TST_ADDAC_TST_MODE_S 0
1506 #define AR_TST_ADDAC_TST_LOOP_ENA 0x2
1508 #define AR_TST_ADDAC_BEGIN_CAPTURE 0x80000
1516 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF // frame ctrl mask bits
1517 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 // qos ctrl mask bits
1522 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF // seq + frag mask bits
1523 #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 // frame ctrl mask for mgmt frames…
1528 #define AR_GATED_CLKS_TX 0x00000002
1529 #define AR_GATED_CLKS_RX 0x00000004
1530 #define AR_GATED_CLKS_REG 0x00000008
1534 #define AR_OBS_BUS_SEL_1 0x00040000
1535 #define AR_OBS_BUS_SEL_2 0x00080000
1536 #define AR_OBS_BUS_SEL_3 0x000C0000
1537 #define AR_OBS_BUS_SEL_4 0x08040000
1538 #define AR_OBS_BUS_SEL_5 0x08080000
1542 #define AR_OBS_BUS_1_PCU 0x00000001
1543 #define AR_OBS_BUS_1_RX_END 0x00000002
1544 #define AR_OBS_BUS_1_RX_WEP 0x00000004
1545 #define AR_OBS_BUS_1_RX_BEACON 0x00000008
1546 #define AR_OBS_BUS_1_RX_FILTER 0x00000010
1547 #define AR_OBS_BUS_1_TX_HCF 0x00000020
1548 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040
1549 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080
1550 #define AR_OBS_BUS_1_TX_HOLD 0x00000100
1551 #define AR_OBS_BUS_1_TX_FRAME 0x00000200
1552 #define AR_OBS_BUS_1_RX_FRAME 0x00000400
1553 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800
1554 #define AR_OBS_BUS_1_WEP_STATE 0x0003F000
1556 #define AR_OBS_BUS_1_RX_STATE 0x01F00000
1558 #define AR_OBS_BUS_1_TX_STATE 0x7E000000
1563 #define AR_PCU_SMPS_MAC_CHAINMASK 0x00000001 // Use the Rx Chainmask of MAC's setting
1564 #define AR_PCU_SMPS_HW_CTRL_EN 0x00000002 // Enable hardware control of dynamic MIMO PS
1565 #define AR_PCU_SMPS_SW_CTRL_HPWR 0x00000004 // Software controlled High power chainmask set…
1566 #define AR_PCU_SMPS_LPWR_CHNMSK 0x00000070 // Low power setting of Rx Chainmask
1568 #define AR_PCU_SMPS_HPWR_CHNMSK 0x00000700 // High power setting of Rx Chainmask
1570 #define AR_PCU_SMPS_LPWR_CHNMSK_VAL 0x1
1594 /* MAC PCU Basic MCS set for MCS 0 to 31 */
1596 #define ALL_RATE 0xff
1600 #define AR_MGMT_SEQ_MIN 0xFFF /* sequence minimum value*/
1601 #define AR_MGMT_SEQ_MIN_S 0
1602 #define AR_MIN_HW_SEQ 0
1603 #define AR_MGMT_SEQ_MAX 0xFFF0000 /* sequence maximum value*/
1605 #define AR_MAX_HW_SEQ 0xFF
1630 #define AR_SLEEP1_ASSUME_DTIM 0x00080000 // Assume DTIM on missed beacon
1631 #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 // Cab timeout(TU) mask
1636 #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 // Beacon timeout(TU) mask
1641 #define AR_MMSS 0x00000007
1642 #define AR_MMSS_S 0
1643 #define AR_SELFGEN_MMSS_NO RESTRICTION 0
1652 #define AR_CEC 0x00000018
1654 /* Although in original standard 0 is for 1 stream and 1 is for 2 stream */
1666 #define AR_TPC_ACK 0x0000003f // ack frames mask
1667 #define AR_TPC_ACK_S 0x00 // ack frames shift
1668 #define AR_TPC_CTS 0x00003f00 // cts frames mask
1669 #define AR_TPC_CTS_S 0x08 // cts frames shift
1670 #define AR_TPC_CHIRP 0x003f0000 // chirp frames mask
1672 #define AR_TPC_RPT 0x3f000000 // rpt frames mask
1686 #define AR_QUIET1_NEXT_QUIET_S 0 // TSF of next quiet period (TU)
1687 #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff
1688 #define AR_QUIET1_QUIET_ENABLE 0x00010000 // Enable Quiet time operation
1689 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 // ack/cts in quiet period
1692 #define AR_QUIET2_QUIET_PERIOD_S 0 // Periodicity of quiet period (TU)
1693 #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff
1695 #define AR_QUIET2_QUIET_DUR 0xffff0000
1699 #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f // 2 bit sentinel for no-ack
1700 #define AR_QOS_NO_ACK_TWO_BIT_S 0
1701 #define AR_QOS_NO_ACK_BIT_OFF 0x00000070 // offset for no-ack
1703 #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 // from end of header
1709 #define AR_PHY_ERR_DCHIRP 0x00000008 // Bit 3 enables double chirp
1710 #define AR_PHY_ERR_RADAR 0x00000020 // Bit 5 is Radar signal
1711 #define AR_PHY_ERR_OFDM_TIMING 0x00020000 // Bit 17 is AH_FALSE detect for OFDM
1712 #define AR_PHY_ERR_CCK_TIMING 0x02000000 // Bit 25 is AH_FALSE detect for CCK
1720 #define AR_RXFIFO_CFG_REG_RD_ENA (0x1 << AR_RXFIFO_CFG_REG_RD_ENA_S)
1729 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 // force bssid to match
1730 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 // tx/rx mic key are together
1731 #define AR_PCU_TX_ADD_TSF 0x00000008 // add tx_tsf + int_tsf
1732 #define AR_PCU_CCK_SIFS_MODE 0x00000010 // assume 11b sifs programmed
1733 #define AR_PCU_RX_ANT_UPDT 0x00000800 // KC_RX_ANT_UPDATE
1734 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 // enforce txop / tbtt
1735 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 // count bmiss's when sleeping
1736 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 // use rx_clear to count sifs
1737 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 // kill xmit for channel change
1738 #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000
1740 #define AR_PCU_TBTT_PROTECT 0x00200000 // no xmit upto tbtt + 20 uS
1741 #define AR_PCU_CLEAR_VMF 0x01000000 // clear vmf mode (fast cc)
1742 #define AR_PCU_CLEAR_BA_VALID 0x04000000 // clear ba state
1743 #define AR_PCU_SEL_EVM 0x08000000 // select EVM data or PLCP header
1744 #define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000 /* always perform key search */
1747 #define AR_FILT_OFDM_COUNT 0x00FFFFFF // count of filtered ofdm
1751 #define AR_FILT_CCK_COUNT 0x00FFFFFF // count of filtered cck
1755 #define AR_PHY_ERR_1_COUNT 0x00FFFFFF // phy errs that pass mask_1
1761 #define AR_PHY_ERR_2_COUNT 0x00FFFFFF // phy errs that pass mask_2
1770 #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF // field width
1774 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF // phy errs that pass mask_3
1780 #define AR_BT_TIME_EXTEND 0x000000ff
1781 #define AR_BT_TIME_EXTEND_S 0
1782 #define AR_BT_TXSTATE_EXTEND 0x00000100
1784 #define AR_BT_TX_FRAME_EXTEND 0x00000200
1786 #define AR_BT_MODE 0x00000c00
1788 #define AR_BT_QUIET 0x00001000
1790 #define AR_BT_QCU_THRESH 0x0001e000
1792 #define AR_BT_RX_CLEAR_POLARITY 0x00020000
1794 #define AR_BT_PRIORITY_TIME 0x00fc0000
1796 #define AR_BT_FIRST_SLOT_TIME 0xff000000
1801 #define AR_BT_BT_WGHT 0x0000ffff
1802 #define AR_BT_BT_WGHT_S 0
1803 #define AR_BT_WL_WGHT 0xffff0000
1811 #define AR_BT_BCN_MISS_THRESH 0x000000ff
1812 #define AR_BT_BCN_MISS_THRESH_S 0
1813 #define AR_BT_BCN_MISS_CNT 0x0000ff00
1815 #define AR_BT_HOLD_RX_CLEAR 0x00010000
1817 #define AR_BT_SLEEP_ALLOW_BT 0x00020000
1819 #define AR_BT_PROTECT_AFTER_WAKE 0x00080000
1821 #define AR_BT_DISABLE_BT_ANT 0x00100000
1823 #define AR_BT_QUIET_2_WIRE 0x00200000
1825 #define AR_BT_WL_ACTIVE_MODE 0x00c00000
1827 #define AR_BT_WL_TXRX_SEPARATE 0x01000000
1829 #define AR_BT_RS_DISCARD_EXTEND 0x02000000
1831 #define AR_BT_TSF_BT_ACTIVE_CTRL 0x0c000000
1833 #define AR_BT_TSF_BT_PRIORITY_CTRL 0x30000000
1835 #define AR_BT_INTERRUPT_ENABLE 0x40000000
1837 #define AR_BT_PHY_ERR_BT_COLL_ENABLE 0x80000000
1845 #define AR_GEN_TIMERS2_0_NEXT AR_GEN_TIMERS2_NEXT(0)
1853 #define AR_GEN_TIMERS2_0_PERIOD AR_GEN_TIMERS2_PERIOD(0)
1881 #define AR_TXSIFS_TIME 0x000000FF // uS in SIFS
1882 #define AR_TXSIFS_TX_LATENCY 0x00000F00 // uS for transmission thru bb
1884 #define AR_TXSIFS_ACK_SHIFT 0x00007000 // chan width for ack
1893 #define AR_TXOP_X_VAL 0x000000FF
1895 /* TXOP for TID 0 to 3 */
1909 #define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0)
1928 #define AR_TBTT_TIMER_EN 0x00000001
1929 #define AR_DBA_TIMER_EN 0x00000002
1930 #define AR_SWBA_TIMER_EN 0x00000004
1931 #define AR_HCF_TIMER_EN 0x00000008
1932 #define AR_TIM_TIMER_EN 0x00000010
1933 #define AR_DTIM_TIMER_EN 0x00000020
1934 #define AR_QUIET_TIMER_EN 0x00000040
1935 #define AR_NDP_TIMER_EN 0x00000080
1936 #define AR_TIMER_OVERFLOW_INDEX 0x00000700
1938 #define AR_TIMER_THRESH 0xFFFFF000
1942 #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF // rising <-> falling edge
1943 #define AR_SLP32_ENA 0x00100000
1944 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 // tsf update in progress
1947 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF // time to wake crystal
1950 #define AR_SLP32_TST_INC 0x000FFFFF
1954 #define AR_SLP_CYCLE_CNT 0x8254 // absolute number of 32kHz cycles
1961 #define AR_SLP_MIB_CLEAR 0x00000001 // clear pending
1962 #define AR_SLP_MIB_PENDING 0x00000002 // clear counters
1967 #define AR_MAC_PCU_LOGIC_ANALYZER_CTL 0x0000000F
1968 #define AR_MAC_PCU_LOGIC_ANALYZER_HOLD 0x00000001
1969 #define AR_MAC_PCU_LOGIC_ANALYZER_CLEAR 0x00000002
1970 #define AR_MAC_PCU_LOGIC_ANALYZER_STATE 0x00000004
1971 #define AR_MAC_PCU_LOGIC_ANALYZER_ENABLE 0x00000008
1972 #define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL 0x000000F0
1974 #define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR 0x0003FF00
1977 #define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE 0xFFFC0000
1979 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20614 0x00040000
1980 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000
1981 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20803 0x40000000
1982 #define AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996 0x9d500010
1983 #define AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE 0x9d400010
1988 #define AR_MAC_PCU_TRACE_REG_START 0xE000
1989 #define AR_MAC_PCU_TRACE_REG_END 0xFFFC
1995 #define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca
1999 #define AR_EXBF_IMMDIATE_RESP 0x00000040
2000 #define AR_EXBF_NOACK_NO_RPT 0x00000100
2001 #define AR_H_XFER_TIMEOUT_COUNT 0xf
2002 #define AR_H_XFER_TIMEOUT_COUNT_S 0
2029 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF
2030 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700
2037 #define AR_PCU_MISC_MODE2_BUG_21532_ENABLE 0x00000001
2038 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 /* Decrypt MGT frames using MFP…
2039 #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 /* Don't decrypt MGT frames at …
2041 #define AR_BUG_58603_FIX_ENABLE 0x00000008 /* Enable fix for bug 58603. Th…
2045 #define AR_PCU_MISC_MODE2_PROM_VC_MODE 0xa148103b /* Enable promiscous in azimuth…
2047 #define AR_PCU_MISC_MODE2_RESERVED 0x00000038
2049 #define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multica…
2051 … * If bit is 0, then Multicast search is
2056 #define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080
2057 #define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00
2059 #define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000
2060 #define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP f…
2065 #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000
2066 #define AR_PCU_MISC_MODE2_PROXY_STA 0x01000000 /* see EV 75996 */
2067 #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000
2068 #define AR_DECOUPLE_DECRYPTION 0x08000000
2070 #define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000
2088 #define AR_HPQ_ENABLE 0x00000001
2089 #define AR_HPQ_MASK_BE 0x00000002
2090 #define AR_HPQ_MASK_BK 0x00000004
2091 #define AR_HPQ_MASK_VI 0x00000008
2092 #define AR_HPQ_MASK_VO 0x00000010
2093 #define AR_HPQ_UAPSD 0x00000020
2094 #define AR_HPQ_FRAME_FILTER_0 0x00000040
2095 #define AR_HPQ_FRAME_BSSID_MATCH_0 0x00000080
2096 #define AR_HPQ_UAPSD_TRIGGER_EN 0x00100000
2109 #define AR_HWBCNPROC1_CRC_ENABLE 0x00000001 /* Enable hw beacon processing */
2110 #define AR_HWBCNPROC1_RESET_CRC 0x00000002 /* Reset the last beacon CRC calculated */
2111 #define AR_HWBCNPROC1_EXCLUDE_BCN_INTVL 0x00000004 /* Exclude Beacon interval in CRC calculation */
2112 #define AR_HWBCNPROC1_EXCLUDE_CAP_INFO 0x00000008 /* Exclude Beacon capability information in CRC…
2113 #define AR_HWBCNPROC1_EXCLUDE_TIM_ELM 0x00000010 /* Exclude Beacon TIM element in CRC calculatio…
2114 #define AR_HWBCNPROC1_EXCLUDE_ELM0 0x00000020 /* Exclude element ID ELM0 in CRC calculation */
2115 #define AR_HWBCNPROC1_EXCLUDE_ELM1 0x00000040 /* Exclude element ID ELM1 in CRC calculation */
2116 #define AR_HWBCNPROC1_EXCLUDE_ELM2 0x00000080 /* Exclude element ID ELM2 in CRC calculation */
2117 #define AR_HWBCNPROC1_ELM0_ID 0x0000FF00 /* Element ID 0 */
2119 #define AR_HWBCNPROC1_ELM1_ID 0x00FF0000 /* Element ID 1 */
2121 #define AR_HWBCNPROC1_ELM2_ID 0xFF000000 /* Element ID 2 */
2125 #define AR_HWBCNPROC2_FILTER_INTERVAL_ENABLE 0x00000001 /* Enable filtering beacons based on fi…
2126 #define AR_HWBCNPROC2_RESET_INTERVAL 0x00000002 /* Reset internal interval counter inte…
2127 #define AR_HWBCNPROC2_EXCLUDE_ELM3 0x00000004 /* Exclude element ID ELM3 in CRC calcu…
2128 #define AR_HWBCNPROC2_RSVD 0x000000F8 /* reserved */
2129 #define AR_HWBCNPROC2_FILTER_INTERVAL 0x0000FF00 /* Filter interval for beacons */
2131 #define AR_HWBCNPROC2_ELM3_ID 0x00FF0000 /* Element ID 3 */
2133 #define AR_HWBCNPROC2_RSVD2 0xFF000000 /* reserved */
2136 #define AR_BUG_61936_FIX_ENABLE 0x00000040 /* EV61936 - rx descriptor corruption */
2137 #define AR_TIME_BASED_DISCARD_EN 0x80000000
2143 #define AR_MAC_PCU_USE_WBTIMER_TX_TS 0x00000001
2144 #define AR_MAC_PCU_USE_WBTIMER_TX_TS_S 0
2145 #define AR_MAC_PCU_USE_WBTIMER_RX_TS 0x00000002
2156 #define AR_KEY_TYPE 0x00000007 // MAC Key Type Mask
2157 #define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */
2158 #define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */
2159 #define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */
2160 #define AR_KEYTABLE_TYPE_TKIP 0x00000004 /* TKIP and Michael */
2161 #define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES/OCB 128 bit key */
2162 #define AR_KEYTABLE_TYPE_CCM 0x00000006 /* AES/CCM 128 bit key */
2163 #define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */
2164 #define AR_KEYTABLE_ANT 0x00000008 /* previous transmit antenna */
2165 #define AR_KEYTABLE_UAPSD 0x000001E0 /* UAPSD AC mask */
2167 #define AR_KEYTABLE_PWRMGT 0x00000200 /* hw managed PowerMgt bit */
2169 #define AR_KEYTABLE_MMSS 0x00001c00 /* remote's MMSS*/
2171 #define AR_KEYTABLE_CEC 0x00006000 /* remote's CEC*/
2173 #define AR_KEYTABLE_STAGGED 0x00010000 /* remote's stagged sounding*/
2176 #define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */
2177 #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */
2185 #define AR_KEYTABLE_DIR_ACK_BIT 0x00000010 /* Directed ACK bit */
2193 #define AR_WOW_PAT_BACKOFF 0x00000004
2194 #define AR_WOW_BACK_OFF_SHIFT(x) ((x & 0xf) << 27) /* in usecs */
2195 #define AR_WOW_MAC_INTR_EN 0x00040000
2196 #define AR_WOW_MAGIC_EN 0x00010000
2197 #define AR_WOW_PATTERN_EN(x) ((x & 0xff) << 0)
2199 #define AR_WOW_PATTERN_FOUND(x) (x & (0xff << AR_WOW_PATTERN_FOUND_SHIFT))
2200 #define AR_WOW_PATTERN_FOUND_MASK ((0xff) << AR_WOW_PATTERN_FOUND_SHIFT)
2201 #define AR_WOW_MAGIC_PAT_FOUND 0x00020000
2202 #define AR_WOW_MAC_INTR 0x00080000
2203 #define AR_WOW_KEEP_ALIVE_FAIL 0x00100000
2204 #define AR_WOW_BEACON_FAIL 0x00200000
2208 #define AR_WOW_AIFS_CNT(x) ((x & 0xff) << 0)
2209 #define AR_WOW_SLOT_CNT(x) ((x & 0xff) << 8)
2210 #define AR_WOW_KEEP_ALIVE_CNT(x) ((x & 0xff) << 16)
2215 #define AR_WOW_CNT_AIFS_CNT 0x00000022 // AR_WOW_COUNT_REG
2216 #define AR_WOW_CNT_SLOT_CNT 0x00000009 // AR_WOW_COUNT_REG
2220 #define AR_WOW_CNT_KA_CNT 0x00000008 // AR_WOW_COUNT_REG
2224 #define AR_WOW_BEACON_FAIL_EN 0x00000001
2227 #define AR_WOW_BEACON_TIMO 0x40000000 /* Valid if BCN_EN is set */
2228 #define AR_WOW_BEACON_TIMO_MAX 0xFFFFFFFF /* Max. value for Beacon Timeout */
2231 #define AR_WOW_KEEP_ALIVE_TIMO 0x00007A12
2232 #define AR_WOW_KEEP_ALIVE_NEVER 0xFFFFFFFF
2235 #define AR_WOW_KEEP_ALIVE_AUTO_DIS 0x00000001
2236 #define AR_WOW_KEEP_ALIVE_FAIL_DIS 0x00000002
2241 #define AR_WOW_KEEP_ALIVE_DELAY 0x000003E8 // 1 msec
2244 #define AR_WOW_PAT_END_OF_PKT(x) ((x & 0xf) << 0)
2245 #define AR_WOW_PAT_OFF_MATCH(x) ((x & 0xf) << 8)
2248 #define AR_WOW_PATTERN_OFF1_REG AR_MAC_PCU_OFFSET(PCU_WOW4) /* Pattern bytes 0 -> 3 */
2267 #define AR_AZIMUTH_KEY_SEARCH_AD1 0x00000002
2268 #define AR_AZIMUTH_CTS_MATCH_TX_AD2 0x00000040
2269 #define AR_AZIMUTH_BA_USES_AD1 0x00000080
2270 #define AR_AZIMUTH_FILTER_PASS_HOLD 0x00000200
2280 #define AR_LOC_CTL_REG_FS 0x1
2288 #define AR_WOW_CLEAR_EVENTS(x) (x & ~(AR_WOW_PATTERN_EN(0xff) | \
2296 #define AR_WOW_BMISSTHRESHOLD 0x20
2303 #define AR_WOW_KA_DESC_WORD2 AR_WOW_TXBUF(0)
2325 #define AR_WOW_SW_NULL_LONG_PERIOD_MASK 0x0000FFFF
2326 #define AR_WOW_SW_NULL_LONG_PERIOD_MASK_S 0
2327 #define AR_WOW_SW_NULL_SHORT_PERIOD_MASK 0xFFFF0000
2331 #define AR_WOW_OFFLOAD_ENA_GTK 0x80000000
2332 #define AR_WOW_OFFLOAD_ENA_ACER_MAGIC 0x40000000
2333 #define AR_WOW_OFFLOAD_ENA_STD_MAGIC 0x20000000
2334 #define AR_WOW_OFFLOAD_ENA_SWKA 0x10000000
2335 #define AR_WOW_OFFLOAD_ENA_ARP_OFFLOAD 0x08000000
2336 #define AR_WOW_OFFLOAD_ENA_NS_OFFLOAD 0x04000000
2337 #define AR_WOW_OFFLOAD_ENA_4WAY_WAKE 0x02000000
2338 #define AR_WOW_OFFLOAD_ENA_GTK_ERROR_WAKE 0x01000000
2339 #define AR_WOW_OFFLOAD_ENA_AP_LOSS_WAKE 0x00800000
2340 #define AR_WOW_OFFLOAD_ENA_BT_SLEEP 0x00080000
2341 #define AR_WOW_OFFLOAD_ENA_SW_NULL 0x00040000
2342 #define AR_WOW_OFFLOAD_ENA_HWKA_FAIL 0x00020000
2343 #define AR_WOW_OFFLOAD_ENA_DEVID_SWAR 0x00010000
2432 /* Currently Pattern 0-7 are supported - so bit 0-7 are set */
2433 #define AR_WOW_PATTERN_SUPPORTED 0xFF
2434 #define AR_WOW_LENGTH_MAX 0xFF
2435 #define AR_WOW_LENGTH1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3)
2437 #define AR_WOW_LENGTH2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3)
2466 #define AR_DC_AP_STA_EN 0x00000001
2467 #define AR_DC_AP_STA_EN_S 0
2477 #define AR_TXBF_CB_TX 0x00000003
2478 #define AR_TXBF_CB_TX_S 0
2479 #define AR_TXBF_PSI_1_PHI_3 0
2484 #define AR_TXBF_NB_TX 0x0000000C
2486 #define AR_TXBF_NUMBEROFBIT_4 0
2491 #define AR_TXBF_NG_RPT_TX 0x00000030
2493 #define AR_TXBF_No_GROUP 0
2497 #define AR_TXBF_NG_CVCACHE 0x000000C0
2499 #define AR_TXBF_FOUR_CLIENTS 0
2503 #define AR_TXBF_TXCV_BFWEIGHT_METHOD 0x00000600
2505 #define AR_TXBF_NO_WEIGHTING 0
2509 #define AR_TXBF_RLR_EN 0x00000800
2510 #define AR_TXBF_RC_20_U_DONE 0x00001000
2511 #define AR_TXBF_RC_20_L_DONE 0x00002000
2512 #define AR_TXBF_RC_40_DONE 0x00004000
2513 #define AR_TXBF_FORCE_UPDATE_V2BB 0x00008000
2516 #define AR_TXBF_TIMER_TIMEOUT 0x000000FF
2517 #define AR_TXBF_TIMER_TIMEOUT_S 0
2518 #define AR_TXBF_TIMER_ATIMEOU 0x0000FF00
2523 #define AR_LRU_ACK 0x00000001
2524 #define AR_LRU_ADDR 0x000003FE
2526 #define AR_LRU_EN 0x00000800
2528 #define AR_DEST_IDX 0x0007f000
2530 #define AR_LRU_WR_ACK 0x00080000
2532 #define AR_LRU_RD_ACK 0x00100000
2543 #define AR_CVCACHE_Ng_IDX 0x0000C000
2545 #define AR_CVCACHE_BW40 0x00010000
2547 #define AR_CVCACHE_IMPLICIT 0x00020000
2549 #define AR_CVCACHE_DEST_IDX 0x01FC0000
2551 #define AR_CVCACHE_Nc_IDX 0x06000000
2553 #define AR_CVCACHE_Nr_IDX 0x18000000
2555 #define AR_CVCACHE_EXPIRED 0x20000000
2557 #define AR_CVCACHE_WRITE 0x80000000
2559 #define AR_CVCACHE_RD_EN 0x40000000
2560 #define AR_CVCACHE_DATA 0x3fffffff
2564 #define ANT_DIV_CONTROL_ALL (0x7e000000)
2566 #define ANT_DIV_ENABLE (0x1000000)
2568 #define FAST_DIV_ENABLE (0x2000)
2575 #define AR_MBOX_INT_EMB_CPU 0x0001
2576 #define AR_MBOX_INT_WLAN 0x0002
2577 #define AR_MBOX_RESET 0x0004
2578 #define AR_MBOX_RAM_REQ_MASK 0x0018
2579 #define AR_MBOX_RAM_REQ_NO_RAM 0x0000
2580 #define AR_MBOX_RAM_REQ_USB 0x0008
2581 #define AR_MBOX_RAM_REQ_WLAN_BUF 0x0010
2582 #define AR_MBOX_RAM_REQ_PATCH_REAPPY 0x0018
2583 #define AR_MBOX_RAM_CONF 0x0020
2584 #define AR_MBOX_WLAN_BUF 0x0040
2585 #define AR_MBOX_WOW_REQ 0x0080
2586 #define AR_MBOX_WOW_CONF 0x0100
2587 #define AR_MBOX_WOW_ERROR_MASK 0x1e00
2588 #define AR_MBOX_WOW_ERROR_NONE 0x0000
2589 #define AR_MBOX_WOW_ERROR_INVALID_MSG 0x0200
2590 #define AR_MBOX_WOW_ERROR_MALFORMED_MSG 0x0400
2591 #define AR_MBOX_WOW_ERROR_INVALID_RAM_IMAGE 0x0600
2598 #define AR_EMB_CPU_WOW_STATUS_KEEP_ALIVE_FAIL 0x1
2599 #define AR_EMB_CPU_WOW_STATUS_BEACON_MISS 0x2
2600 #define AR_EMB_CPU_WOW_STATUS_PATTERN_MATCH 0x4
2601 #define AR_EMB_CPU_WOW_STATUS_MAGIC_PATTERN 0x8
2604 #define AR_EMB_CPU_WOW_ENABLE_KEEP_ALIVE_FAIL 0x1
2605 #define AR_EMB_CPU_WOW_ENABLE_BEACON_MISS 0x2
2606 #define AR_EMB_CPU_WOW_ENABLE_PATTERN_MATCH 0x4
2607 #define AR_EMB_CPU_WOW_ENABLE_MAGIC_PATTERN 0x8
2610 #define AR_SW_WOW_ENABLE 0x1
2611 #define AR_SWITCH_TO_REFCLK 0x2
2612 #define AR_RESET_CONTROL 0x4
2613 #define AR_RESET_VALUE_MASK 0x8
2614 #define AR_HW_WOW_DISABLE 0x10
2615 #define AR_CLR_MAC_INTERRUPT 0x20
2616 #define AR_CLR_KA_INTERRUPT 0x40
2624 #define AR_MCI_COMMAND0_HEADER 0xFF
2625 #define AR_MCI_COMMAND0_HEADER_S 0
2626 #define AR_MCI_COMMAND0_LEN 0x1f00
2628 #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000
2634 #define AR_MCI_COMMAND2_RESET_TX 0x01
2635 #define AR_MCI_COMMAND2_RESET_TX_S 0
2636 #define AR_MCI_COMMAND2_RESET_RX 0x02
2638 #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC
2640 #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400
2646 /* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */
2647 #define AR_MCI_TX_CTRL_CLK_DIV 0x03
2648 #define AR_MCI_TX_CTRL_CLK_DIV_S 0
2649 #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04
2651 #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8
2653 #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000
2657 #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF
2658 #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0
2659 #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000
2666 #define AR_MCI_GPM_WRITE_PTR 0xFFFF0000
2668 #define AR_MCI_GPM_BUF_LEN 0x0000FFFF
2669 #define AR_MCI_GPM_BUF_LEN_S 0
2673 #define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001
2674 #define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0
2675 #define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002
2677 #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004
2679 #define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008
2681 #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010
2683 #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020
2685 #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080
2687 #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100
2689 #define AR_MCI_INTERRUPT_RX_MSG 0x00000200
2691 #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400
2693 #define AR_MCI_INTERRUPT_BT_PRI 0x07fff800
2695 #define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000
2697 #define AR_MCI_INTERRUPT_BT_FREQ 0x10000000
2699 #define AR_MCI_INTERRUPT_BT_STOMP 0x20000000
2701 #define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000
2703 #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000
2726 #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001
2727 #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0
2728 #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002
2730 #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004
2732 #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008
2734 #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010
2736 #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020
2738 #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040
2740 #define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100
2742 #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200
2744 #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400
2746 #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800
2748 #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000
2779 #define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00
2781 #define AR_MCI_RX_REMOTE_SLEEP 0x00001000
2783 #define AR_MCI_RX_MCI_CLK_REQ 0x00002000
2787 #define AR_MCI_CONT_RSSI_POWER 0x000000FF
2788 #define AR_MCI_CONT_RSSI_POWER_S 0
2789 #define AR_MCI_CONT_RRIORITY 0x0000FF00
2791 #define AR_MCI_CONT_TXRX 0x00010000
2820 #define AR_BTCOEX_CTRL_JUPITER_MODE 0x00000001
2821 #define AR_BTCOEX_CTRL_JUPITER_MODE_S 0
2822 #define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002
2824 #define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004
2826 #define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008
2828 #define AR_BTCOEX_CTRL_PA_SHARED 0x00000010
2830 #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020
2832 #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040
2834 #define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180
2836 #define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00
2838 #define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000
2840 #define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000
2842 #define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000
2844 #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000
2846 #define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000
2848 #define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000
2850 #define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000
2859 #define AR_BTCOEX_WL_LNA_TIMEOUT 0x003FFFFF
2860 #define AR_BTCOEX_WL_LNA_TIMEOUT_S 0
2865 #define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800
2867 #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000
2869 #define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000
2871 #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000
2873 #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000
2875 #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000
2885 #define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001
2886 #define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0
2887 #define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002
2891 #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000FFF
2892 #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0
2896 #define AR_BTCOEX_WL_LNADIV 0x1a64
2897 #define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD 0x00003FFF
2898 #define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD_S 0
2899 #define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY 0x00004000
2901 #define AR_BTCOEX_WL_LNADIV_FORCE_ON 0x00008000
2903 #define AR_BTCOEX_WL_LNADIV_MODE_OPTION 0x00030000
2905 #define AR_BTCOEX_WL_LNADIV_MODE 0x007c0000
2907 #define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ 0x00800000
2909 #define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE 0x01000000
2911 #define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT 0x02000000
2913 #define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD 0xFC000000
2916 #define AR_MCI_MISC 0x1a74
2917 #define AR_MCI_MISC_HW_FIX_EN 0x00000001
2918 #define AR_MCI_MISC_HW_FIX_EN_S 0
2954 #define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001
2955 #define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0
2956 #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002
2958 #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004
2960 #define AR_GLB_WLAN_UART_INTF_EN 0x00020000
2962 #define AR_GLB_DS_JTAG_DISABLE 0x00040000
2971 #define AR_SREV_VERSION_OSPREY 0x1C0
2972 #define AR_SREV_VERSION_AR9580 0x1C0
2973 #define AR_SREV_VERSION_JUPITER 0x280
2974 #define AR_SREV_VERSION_HORNET 0x200
2975 #define AR_SREV_VERSION_WASP 0x300 /* XXX: Check Wasp version number */
2976 #define AR_SREV_VERSION_SCORPION 0x400
2977 #define AR_SREV_VERSION_POSEIDON 0x240
2978 #define AR_SREV_VERSION_HONEYBEE 0x500
2979 #define AR_SREV_VERSION_APHRODITE 0x2C0
2981 #define AR_SREV_REVISION_OSPREY_10 0 /* Osprey 1.0 */
2986 #define AR_SREV_REVISION_HORNET_10 0 /* Hornet 1.0 */
2989 #define AR_SREV_REVISION_HORNET_11_MASK 0xf /* Hornet 1.1 revision mask */
2991 #define AR_SREV_REVISION_POSEIDON_10 0 /* Poseidon 1.0 */
2994 #define AR_SREV_REVISION_WASP_10 0 /* Wasp 1.0 */
2998 #define AR_SREV_REVISION_WASP_MASK 0xf /* Wasp revision mask */
2999 #define AR_SREV_REVISION_WASP_MINOR_MINOR_MASK 0x10000 /* Wasp minor minor revision mask */
3002 #define AR_SREV_REVISION_JUPITER_10 0 /* Jupiter 1.0 */
3006 #define AR_SREV_REVISION_HONEYBEE_10 0 /* Honeybee 1.0 */
3008 #define AR_SREV_REVISION_HONEYBEE_MASK 0xf /* Honeybee revision mask */
3010 #define AR_SREV_REVISION_APHRODITE_10 0 /* Aphrodite 1.0 */
3020 #define AR_SREV_OSPREY(_ah) 0
3021 #define AR_SREV_OSPREY_10(_ah) 0
3022 #define AR_SREV_OSPREY_20(_ah) 0
3023 #define AR_SREV_OSPREY_22(_ah) 0
3024 #define AR_SREV_OSPREY_20_OR_LATER(_ah) 0
3025 #define AR_SREV_OSPREY_22_OR_LATER(_ah) 0
3086 #define AR_SREV_HORNET_10(_ah) 0
3087 #define AR_SREV_HORNET_11(_ah) 0
3088 #define AR_SREV_HORNET_12(_ah) 0
3089 #define AR_SREV_HORNET(_ah) 0
3096 #define AR_SREV_WASP(_ah) 0
3109 #define AR_SREV_HONEYBEE(_ah) 0
3110 #define AR_SREV_HONEYBEE_10(_ah) 0
3111 #define AR_SREV_HONEYBEE_11(_ah) 0
3130 #define AR_SREV_SCORPION(_ah) 0
3145 #define AR_SREV_POSEIDON(_ah) 0
3146 #define AR_SREV_POSEIDON_10(_ah) 0
3147 #define AR_SREV_POSEIDON_11(_ah) 0
3159 * Cisco spec defined bits 0-3 as mask
3162 #define AR_MFP_QOS_MASK_IEEE 0x10
3163 #define AR_MFP_QOS_MASK_CISCO 0xf
3167 * 0 0 0 0 0 0 0 0
3177 #define AR_AES_MUTE_MASK1_FC_MGMT_MFP 0xC7FF