Lines Matching defs:ospreyModalEepHeader
297 typedef struct ospreyModalEepHeader { struct
298 u_int32_t ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting)
299 u_int32_t ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12
300 … u_int16_t ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each)
301 …u_int8_t xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
302 …8_t xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
303 int8_t temp_slope;
304 int8_t voltSlope;
305 u_int8_t spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format
306 int8_t noise_floor_thresh_ch[OSPREY_MAX_CHAINS];// 3 //Check if the register is per chain
307 u_int8_t reserved[MAX_MODAL_RESERVED];
308 int8_t quick_drop;
309 u_int8_t xpa_bias_lvl; // 1
310 u_int8_t tx_frame_to_data_start; // 1
311 u_int8_t tx_frame_to_pa_on; // 1
312 u_int8_t txClip; // 4 bits tx_clip, 4 bits dac_scale_cck
313 int8_t antenna_gain; // 1
314 u_int8_t switchSettling; // 1
315 int8_t adcDesiredSize; // 1
316 u_int8_t tx_end_to_xpa_off; // 1
317 u_int8_t txEndToRxOn; // 1
318 u_int8_t tx_frame_to_xpa_on; // 1
319 u_int8_t thresh62; // 1
320 u_int32_t paprd_rate_mask_ht20;
321 u_int32_t paprd_rate_mask_ht40;
322 u_int16_t switchcomspdt;
323 u_int8_t xLNA_bias_strength; // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
324 u_int8_t rf_gain_cap;
325 … // bit0:4 txgain cap, txgain index for max_txgain + 20 (10dBm higher than max txgain)
326 u_int8_t futureModal[MAX_MODAL_FUTURE];