Lines Matching +full:msi +full:- +full:base +full:- +full:spi
3 * Module Name: dmtbinfo2 - Table info for non-AML tables
11 * Some or all of this work - Copyright (c) 1999 - 2025, Intel Corp.
24 * base code distributed originally by Intel ("Original Intel Code") to copy,
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
157 /* This module used for application-level code only */
165 * - Add the C table definition to the actbl1.h or actbl2.h header.
166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below.
167 * - Define the table in this file (for the disassembler). If any
169 * - Add an external declaration for the new table definition (AcpiDmTableInfo*)
171 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData)
175 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h
176 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c
177 * - Create a template for the new table
178 * - Add data table compiler support
182 * - Add new type at the end of the ACPI_DMT list in acdisasm.h
183 * - Add length and implementation cases in dmtable.c (disassembler)
184 * - Add type and length cases in dtutils.c (DT compiler)
193 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface
213 * APMT - ARM Performance Monitoring Unit Table
227 {ACPI_DMT_FLAG2, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "64-bit Atomic Support", 0},
232 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress0), "Page 0 Base Address", 0},
233 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress1), "Page 1 Base Address", 0},
247 * IORT - IO Remapping Table
280 /* Common Subtable header (one per Subtable)- Revision 3 */
295 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (InputBase), "Input base", DT_OPTIONAL},
297 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputBase), "Output Base", 0},
370 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (BaseAddress), "Base Address", 0},
411 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (BaseAddress), "Base Address", 0},
433 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page0BaseAddress), "Page 0 Base Address", 0},
436 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page1BaseAddress), "Page 1 Base Address", 0},
456 …{ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (BaseAddress), "Base Address of RMR", DT_OPTIONAL…
464 * IVRS - I/O Virtualization Reporting Structure
494 {ACPI_DMT_UINT64, ACPI_IVRS0_OFFSET (BaseAddress), "Base Address", 0},
518 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (BaseAddress), "Base Address", 0},
560 /* 4-byte device entry (Types 1,2,3,4) */
568 /* 8-byte device entry (Type Alias Select, Alias Start of Range) */
579 /* 8-byte device entry (Type Extended Select, Extended Start of Range) */
588 /* 8-byte device entry (Type Special Device) */
599 /* Variable-length Device Entry Type 0xF0 */
649 * LPIT - Low Power Idle Table
671 /* 0: Native C-state */
684 * MADT - Multiple APIC Description Table and subtables
692 {ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility", 0},
781 {ACPI_DMT_UINT32, ACPI_MADT6_OFFSET (GlobalIrqBase), "Interrupt Base", 0},
857 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0},
858 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0},
859 … {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0},
861 … {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0},
870 /* 11: Generic Interrupt Controller (ACPI 5.0) - MADT revision 6 */
885 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0},
886 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0},
887 … {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0},
889 … {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0},
898 /* 11: Generic Interrupt Controller (ACPI 5.0) - MADT revision 7 */
910 {ACPI_DMT_FLAG4, ACPI_MADT11_FLAG_OFFSET (Flags,0), "GICR non-coherent", 0},
914 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0},
915 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0},
916 … {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0},
918 … {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0},
933 {ACPI_DMT_UINT64, ACPI_MADT12_OFFSET (BaseAddress), "Base Address", 0},
934 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GlobalIrqBase), "Interrupt Base", 0},
940 /* 13: Generic MSI Frame (ACPI 5.1) */
945 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (MsiFrameId), "MSI Frame ID", 0},
946 {ACPI_DMT_UINT64, ACPI_MADT13_OFFSET (BaseAddress), "Base Address", 0},
948 {ACPI_DMT_FLAG0, ACPI_MADT13_FLAG_OFFSET (Flags,0), "Select SPI", 0},
949 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiCount), "SPI Count", 0},
950 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiBase), "SPI Base", 0},
959 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0},
969 {ACPI_DMT_FLAG0, ACPI_MADT14_FLAG_OFFSET (Flags,0), "GICR non-coherent", 0},
971 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0},
982 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0},
990 {ACPI_DMT_FLAG0, ACPI_MADT15_FLAG_OFFSET (Flags,0), "GIC ITS non-coherent", 0},
993 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0},
1053 /* 21: MSI controller */
1102 /* 25: RISC-V IMSIC interrupt controller */
1118 /* 26: RISC-V APLIC interrupt controller */
1134 /* 27: RISC-V PLIC interrupt controller */
1160 * MCFG - PCI Memory Mapped Configuration table and Subtable
1172 {ACPI_DMT_UINT64, ACPI_MCFG0_OFFSET (Address), "Base Address", 0},
1183 * MCHI - Management Controller Host Interface table
1206 * MPAM - Memory System Resource Partitioning and Monitoring Tables
1212 /* 0: MPAM Resource Node Structure - A root MSC table.
1221 {ACPI_DMT_UINT64, ACPI_MPAM0_OFFSET (BaseAddress), "Base address", 0},
1239 /* 1: MPAM Resource (RIS) Node Structure - A subtable of MSC Nodes.
1288 /* 1D: MPAM Memory-side cache locator descriptor. A subtable of RIS.
1342 * MPST - Memory Power State Table
1376 /* 0A: Sub-subtable - Memory Power State Structure (follows Memory Power Node above) */
1385 /* 0B: Sub-subtable - Physical Component ID Structure (follows Memory Power State(s) above) */
1423 * MRRM - Memory Range and Region Mapping Table
1444 {ACPI_DMT_UINT64, ACPI_MRRM0_OFFSET (AddrBase), "System Address Base", 0},
1456 * MSCT - Maximum System Characteristics Table (ACPI 4.0)
1469 /* Subtable - Maximum Proximity Domain Information. Version 1 */
1485 * NFIT - NVDIMM Firmware Interface Table and Subtables - (ACPI 6.0)
1516 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Address), "Address Range Base", 0},
1534 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (Address), "Address Region Base", 0},
1653 * PCCT - Platform Communications Channel Table (ACPI 5.0)
1679 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (BaseAddress), "Base Address", 0},
1690 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */
1699 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (BaseAddress), "Base Address", 0},
1710 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */
1719 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (BaseAddress), "Base Address", 0},
1742 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (BaseAddress), "Base Address", 0},
1773 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (BaseAddress), "Base Address", 0},
1800 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (BaseAddress), "Base Address", 0},
1817 * PDTT - Platform Debug Trigger Table (ACPI 6.2)
1842 * PHAT - Platform Health Assessment Table (ACPI 6.4)
1880 {ACPI_DMT_UINT32, ACPI_PHAT1_OFFSET (DeviceSpecificOffset), "Device-Specific Offset", 0},
1892 …{ACPI_DMT_RAW_BUFFER, 0, "Device-Specific Data", DT_OPTIONA…
1899 * PMTT - Platform Memory Topology Table
1916 {ACPI_DMT_FLAG0, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Top-level Device", 0}, \
1966 * PPTT - Processor Properties Topology Table (ACPI 6.2)
1970 /* Main table consists of only the standard ACPI header - subtables follow */
2055 * PRMT - Platform Runtime Mechanism Table
2101 * RASF - RAS Feature table
2114 * RAS2 - RAS2 Feature table (ACPI 6.5)
2139 * RGRT - Regulatory Graphics Resource Table
2164 * RHCT - RISC-V Hart Capabilities Table
2171 {ACPI_DMT_UINT64, ACPI_RHCT_OFFSET (TimeBaseFreq), "Timer Base Frequency", 0},
2245 * RIMT - RISC-V IO Mapping Table
2247 * https://github.com/riscv-non-isa/riscv-acpi-rimt
2277 {ACPI_DMT_UINT64, ACPI_RIMTI_OFFSET (BaseAddress), "Base Address", 0},
2309 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (SourceIdBase), "Source ID Base", 0},
2311 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (DestIdBase), "Destination Device ID Base", 0},
2336 * S3PT - S3 Performance Table
2379 * SBST - Smart Battery Specification Table
2394 * SDEI - Software Delegated Exception Interface Descriptor Table
2406 * SDEV - Secure Devices Table (ACPI 6.2)
2476 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciBaseClass), "PCI Base Class", 0},
2487 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryBaseAddress), "Memory Base Address", 0},