Lines Matching full:adapter
385 static void al_eth_epe_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_epe_entry_set() argument
389 al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_data, reg_entry->data); in al_eth_epe_entry_set()
390 al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_mask, reg_entry->mask); in al_eth_epe_entry_set()
391 al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_ctrl, reg_entry->ctrl); in al_eth_epe_entry_set()
393 al_reg_write32(&adapter->ec_regs_base->msp_c[idx].p_comp_data, reg_entry->data); in al_eth_epe_entry_set()
394 al_reg_write32(&adapter->ec_regs_base->msp_c[idx].p_comp_mask, reg_entry->mask); in al_eth_epe_entry_set()
395 al_reg_write32(&adapter->ec_regs_base->msp_c[idx].p_comp_ctrl, reg_entry->ctrl); in al_eth_epe_entry_set()
398 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_addr, idx); in al_eth_epe_entry_set()
399 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_6, in al_eth_epe_entry_set()
401 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_2, in al_eth_epe_entry_set()
403 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_3, in al_eth_epe_entry_set()
405 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_4, in al_eth_epe_entry_set()
407 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_5, in al_eth_epe_entry_set()
409 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_1, in al_eth_epe_entry_set()
413 al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_addr, idx); in al_eth_epe_entry_set()
414 al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_6, in al_eth_epe_entry_set()
416 al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_2, in al_eth_epe_entry_set()
418 al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_3, in al_eth_epe_entry_set()
420 al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_4, in al_eth_epe_entry_set()
422 al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_5, in al_eth_epe_entry_set()
424 al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_1, in al_eth_epe_entry_set()
428 static void al_eth_epe_init(struct al_hal_eth_adapter *adapter) in al_eth_epe_init() argument
432 if (adapter->enable_rx_parser == 0) { in al_eth_epe_init()
433 al_dbg("eth [%s]: disable rx parser\n", adapter->name); in al_eth_epe_init()
435 al_reg_write32(&adapter->ec_regs_base->epe[0].res_def, 0x08000000); in al_eth_epe_init()
436 al_reg_write32(&adapter->ec_regs_base->epe[0].res_in, 0x7); in al_eth_epe_init()
438 al_reg_write32(&adapter->ec_regs_base->epe[1].res_def, 0x08000000); in al_eth_epe_init()
439 al_reg_write32(&adapter->ec_regs_base->epe[1].res_in, 0x7); in al_eth_epe_init()
443 al_dbg("eth [%s]: enable rx parser\n", adapter->name); in al_eth_epe_init()
445 al_eth_epe_entry_set(adapter, idx, &al_eth_epe_p_regs[idx], &al_eth_epe_control_table[idx]); in al_eth_epe_init()
447 al_reg_write32(&adapter->ec_regs_base->epe[0].res_def, 0x08000080); in al_eth_epe_init()
448 al_reg_write32(&adapter->ec_regs_base->epe[0].res_in, 0x7); in al_eth_epe_init()
450 al_reg_write32(&adapter->ec_regs_base->epe[1].res_def, 0x08000080); in al_eth_epe_init()
451 al_reg_write32(&adapter->ec_regs_base->epe[1].res_in, 0); in al_eth_epe_init()
454 al_reg_write32(&adapter->ec_regs_base->epe_h[8].hdr_len, (4 << 16) | 4); in al_eth_epe_init()
457 al_reg_write32(&adapter->ec_regs_base->rfw.meta, EC_RFW_META_L3_LEN_CALC); in al_eth_epe_init()
459 al_reg_write32(&adapter->ec_regs_base->rfw.checksum, EC_RFW_CHECKSUM_HDR_SEL); in al_eth_epe_init()
465 * @param adapter pointer to the private structure
471 struct al_hal_eth_adapter *adapter, in al_eth_40g_mac_reg_read() argument
477 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, reg_addr); in al_eth_40g_mac_reg_read()
478 val = al_reg_read32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data); in al_eth_40g_mac_reg_read()
481 adapter->name, __func__, reg_addr, val); in al_eth_40g_mac_reg_read()
489 * @param adapter pointer to the private structure
495 struct al_hal_eth_adapter *adapter, in al_eth_40g_mac_reg_write() argument
500 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, reg_addr); in al_eth_40g_mac_reg_write()
501 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, reg_data); in al_eth_40g_mac_reg_write()
504 adapter->name, __func__, reg_addr, reg_data); in al_eth_40g_mac_reg_write()
510 * @param adapter pointer to the private structure
516 struct al_hal_eth_adapter *adapter, in al_eth_40g_pcs_reg_read() argument
522 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, reg_addr); in al_eth_40g_pcs_reg_read()
523 val = al_reg_read32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data); in al_eth_40g_pcs_reg_read()
526 adapter->name, __func__, reg_addr, val); in al_eth_40g_pcs_reg_read()
534 * @param adapter pointer to the private structure
540 struct al_hal_eth_adapter *adapter, in al_eth_40g_pcs_reg_write() argument
545 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, reg_addr); in al_eth_40g_pcs_reg_write()
546 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, reg_data); in al_eth_40g_pcs_reg_write()
549 adapter->name, __func__, reg_addr, reg_data); in al_eth_40g_pcs_reg_write()
553 /*adapter management */
555 * initialize the ethernet adapter's DMA
557 int al_eth_adapter_init(struct al_hal_eth_adapter *adapter, struct al_eth_adapter_params *params) in al_eth_adapter_init() argument
571 adapter->name = params->name; in al_eth_adapter_init()
572 adapter->rev_id = params->rev_id; in al_eth_adapter_init()
573 adapter->udma_id = params->udma_id; in al_eth_adapter_init()
574 adapter->udma_regs_base = params->udma_regs_base; in al_eth_adapter_init()
575 adapter->ec_regs_base = (struct al_ec_regs __iomem*)params->ec_regs_base; in al_eth_adapter_init()
576 adapter->mac_regs_base = (struct al_eth_mac_regs __iomem*)params->mac_regs_base; in al_eth_adapter_init()
577 adapter->unit_regs = (struct unit_regs __iomem *)params->udma_regs_base; in al_eth_adapter_init()
578 adapter->enable_rx_parser = params->enable_rx_parser; in al_eth_adapter_init()
579 adapter->serdes_lane = params->serdes_lane; in al_eth_adapter_init()
580 adapter->ec_ints_base = (uint8_t __iomem *)adapter->ec_regs_base + 0x1c00; in al_eth_adapter_init()
581 adapter->mac_ints_base = (struct interrupt_controller_ctrl __iomem *) in al_eth_adapter_init()
582 ((uint8_t __iomem *)adapter->mac_regs_base + 0x800); in al_eth_adapter_init()
585 udma_params.udma_regs_base = adapter->unit_regs; in al_eth_adapter_init()
589 rc = al_udma_init(&adapter->tx_udma, &udma_params); in al_eth_adapter_init()
596 rc = al_udma_state_set_wait(&adapter->tx_udma, UDMA_NORMAL); in al_eth_adapter_init()
603 udma_params.udma_regs_base = adapter->unit_regs; in al_eth_adapter_init()
607 rc = al_udma_init(&adapter->rx_udma, &udma_params); in al_eth_adapter_init()
615 rc = al_udma_state_set_wait(&adapter->rx_udma, UDMA_NORMAL); in al_eth_adapter_init()
627 al_udma_m2s_packet_size_cfg_set(&adapter->tx_udma, &conf); in al_eth_adapter_init()
632 al_udma_m2s_max_descs_set(&adapter->tx_udma, AL_ETH_PKT_MAX_BUFS + 1); in al_eth_adapter_init()
635 al_udma_s2m_max_descs_set(&adapter->rx_udma, AL_ETH_PKT_MAX_BUFS); in al_eth_adapter_init()
639 al_udma_s2m_compl_desc_burst_config(&adapter->rx_udma, 64); in al_eth_adapter_init()
642 if (adapter->ec_regs_base != NULL) { in al_eth_adapter_init()
645 al_reg_write32(&adapter->ec_regs_base->tso.cache_table_addr, i + (adapter->udma_id * 4)); in al_eth_adapter_init()
646 al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_1, 0x00000000); in al_eth_adapter_init()
647 al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_2, 0x00000000); in al_eth_adapter_init()
648 al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_3, 0x00000000); in al_eth_adapter_init()
649 al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_4, 0x00000000); in al_eth_adapter_init()
653 if (adapter->udma_id != 0) { in al_eth_adapter_init()
658 al_reg_write32(&adapter->ec_regs_base->gen.en, 0xffffffff); in al_eth_adapter_init()
659 al_reg_write32(&adapter->ec_regs_base->gen.fifo_en, 0xffffffff); in al_eth_adapter_init()
661 if (adapter->rev_id > AL_ETH_REV_ID_0) { in al_eth_adapter_init()
663 al_reg_write32_masked(&adapter->ec_regs_base->gen.en_ext, in al_eth_adapter_init()
668 al_reg_write32(&adapter->ec_regs_base->tso.cfg_add_0, in al_eth_adapter_init()
672 al_reg_write32(&adapter->ec_regs_base->tso.cfg_tunnel, in al_eth_adapter_init()
683 al_reg_write32(&adapter->ec_regs_base->mac.gen, 0x00000001); in al_eth_adapter_init()
685 …al_reg_write32(&adapter->ec_regs_base->tmi.tx_cfg, EC_TMI_TX_CFG_EN_FWD_TO_RX|EC_TMI_TX_CFG_SWAP_B… in al_eth_adapter_init()
688 al_reg_write32(&adapter->ec_regs_base->tfw_udma[0].fwd_dec, 0x000003fb); in al_eth_adapter_init()
691 al_reg_write32(&adapter->ec_regs_base->rfw_default[0].opt_1, 0x00000001); in al_eth_adapter_init()
694 al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_addr, 0x00000000); in al_eth_adapter_init()
696 al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_data, 0x00000000); in al_eth_adapter_init()
699 al_reg_write32(&adapter->ec_regs_base->rfw.thash_cfg_1, in al_eth_adapter_init()
703 al_eth_epe_init(adapter); in al_eth_adapter_init()
706 reg = al_reg_read32(&adapter->ec_regs_base->tso.in_cfg); in al_eth_adapter_init()
708 al_reg_write32(&adapter->ec_regs_base->tso.in_cfg, reg); in al_eth_adapter_init()
714 /*adapter management */
718 int al_eth_ec_mac_ints_config(struct al_hal_eth_adapter *adapter) in al_eth_ec_mac_ints_config() argument
721 al_dbg("eth [%s]: enable ethernet and mac interrupts\n", adapter->name); in al_eth_ec_mac_ints_config()
724 if (adapter->udma_id != 0) in al_eth_ec_mac_ints_config()
728 al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_A, in al_eth_ec_mac_ints_config()
730 al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_B, in al_eth_ec_mac_ints_config()
732 al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_C, in al_eth_ec_mac_ints_config()
734 al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_D, in al_eth_ec_mac_ints_config()
738 al_iofic_unmask(adapter->ec_ints_base, AL_INT_GROUP_A, 8); in al_eth_ec_mac_ints_config()
741 al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_A, in al_eth_ec_mac_ints_config()
743 al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_B, in al_eth_ec_mac_ints_config()
745 al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_C, in al_eth_ec_mac_ints_config()
747 al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_D, in al_eth_ec_mac_ints_config()
751 al_iofic_unmask(adapter->mac_ints_base, AL_INT_GROUP_B, AL_BIT(14)); in al_eth_ec_mac_ints_config()
753 al_iofic_unmask(adapter->unit_regs, AL_INT_GROUP_D, AL_BIT(11)); in al_eth_ec_mac_ints_config()
761 * @param adapter pointer to the private structure
765 int al_eth_ec_mac_isr(struct al_hal_eth_adapter *adapter) in al_eth_ec_mac_isr() argument
768 al_dbg("[%s]: ethernet interrupts handler\n", adapter->name); in al_eth_ec_mac_isr()
771 if (adapter->udma_id != 0) in al_eth_ec_mac_isr()
775 cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_A); in al_eth_ec_mac_isr()
776 al_dbg("[%s]: ethernet group A cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
779 cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_A); in al_eth_ec_mac_isr()
780 al_dbg("[%s]: mac group A cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
782 cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_B); in al_eth_ec_mac_isr()
783 al_dbg("[%s]: mac group B cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
785 cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_C); in al_eth_ec_mac_isr()
786 al_dbg("[%s]: mac group C cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
788 cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_D); in al_eth_ec_mac_isr()
789 al_dbg("[%s]: mac group D cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
791 cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_B); in al_eth_ec_mac_isr()
792 al_dbg("[%s]: ethernet group B cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
793 cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_C); in al_eth_ec_mac_isr()
794 al_dbg("[%s]: ethernet group C cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
795 cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_D); in al_eth_ec_mac_isr()
796 al_dbg("[%s]: ethernet group D cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
802 * stop the DMA of the ethernet adapter
804 int al_eth_adapter_stop(struct al_hal_eth_adapter *adapter) in al_eth_adapter_stop() argument
808 al_dbg("eth [%s]: stop controller's UDMA\n", adapter->name); in al_eth_adapter_stop()
811 rc = al_udma_state_set_wait(&adapter->tx_udma, UDMA_DISABLE); in al_eth_adapter_stop()
814 adapter->tx_udma.name, rc); in al_eth_adapter_stop()
819 adapter->name); in al_eth_adapter_stop()
821 rc = al_udma_state_set_wait(&adapter->rx_udma, UDMA_DISABLE); in al_eth_adapter_stop()
824 adapter->rx_udma.name, rc); in al_eth_adapter_stop()
829 adapter->name); in al_eth_adapter_stop()
833 int al_eth_adapter_reset(struct al_hal_eth_adapter *adapter) in al_eth_adapter_reset() argument
835 al_dbg("eth [%s]: reset controller's UDMA\n", adapter->name); in al_eth_adapter_reset()
844 int al_eth_queue_config(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid, in al_eth_queue_config() argument
850 al_dbg("eth [%s]: config UDMA %s queue %d\n", adapter->name, in al_eth_queue_config()
854 udma = &adapter->tx_udma; in al_eth_queue_config()
856 udma = &adapter->rx_udma; in al_eth_queue_config()
859 q_params->adapter_rev_id = adapter->rev_id; in al_eth_queue_config()
873 al_reg_write32_masked(&adapter->ec_regs_base->rfw.out_cfg, in al_eth_queue_config()
879 int al_eth_queue_enable(struct al_hal_eth_adapter *adapter __attribute__((__unused__)), in al_eth_queue_enable() argument
885 int al_eth_queue_disable(struct al_hal_eth_adapter *adapter __attribute__((__unused__)), in al_eth_queue_disable() argument
893 int al_eth_rx_pkt_limit_config(struct al_hal_eth_adapter *adapter, uint32_t min_rx_len, uint32_t ma… in al_eth_rx_pkt_limit_config() argument
898 al_reg_write32(&adapter->ec_regs_base->mac.min_pkt, min_rx_len); in al_eth_rx_pkt_limit_config()
900 al_reg_write32(&adapter->ec_regs_base->mac.max_pkt, max_rx_len); in al_eth_rx_pkt_limit_config()
902 if (adapter->rev_id > AL_ETH_REV_ID_2) { in al_eth_rx_pkt_limit_config()
903 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, min_rx_len); in al_eth_rx_pkt_limit_config()
904 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, max_rx_len); in al_eth_rx_pkt_limit_config()
910 if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) in al_eth_rx_pkt_limit_config()
911 al_reg_write32(&adapter->mac_regs_base->mac_1g.frm_len, max_rx_len + 16); in al_eth_rx_pkt_limit_config()
912 else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) in al_eth_rx_pkt_limit_config()
914 al_reg_write32(&adapter->mac_regs_base->mac_10g.frm_len, (max_rx_len + 16)); in al_eth_rx_pkt_limit_config()
916 al_eth_40g_mac_reg_write(adapter, ETH_MAC_GEN_V3_MAC_40G_FRM_LENGTH_ADDR, (max_rx_len + 16)); in al_eth_rx_pkt_limit_config()
922 int al_eth_mac_config(struct al_hal_eth_adapter *adapter, enum al_eth_mac_mode mode) in al_eth_mac_config() argument
926 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210); in al_eth_mac_config()
936 al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, 0x01800010); in al_eth_mac_config()
939 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_empty, 0x00000000); in al_eth_mac_config()
941 …al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_full, 0x0000000c); /* must be larger tha… in al_eth_mac_config()
943 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_empty, 0x00000008); in al_eth_mac_config()
945 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_full, 0x00000008); in al_eth_mac_config()
949 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_empty, 0x00000008); /* 8 ? */ in al_eth_mac_config()
951 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_full, 0x0000000c); in al_eth_mac_config()
953 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_empty, 0x00000008); in al_eth_mac_config()
955 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_full, 0x00000008); in al_eth_mac_config()
958 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000000); in al_eth_mac_config()
963 al_reg_write32(&adapter->mac_regs_base->gen.mac_1g_cfg, 0x00000002); in al_eth_mac_config()
965 …al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x000… in al_eth_mac_config()
966 al_reg_write32(&adapter->mac_regs_base->gen.rgmii_sel, 0xF); in al_eth_mac_config()
969 if (adapter->rev_id > AL_ETH_REV_ID_2) { in al_eth_mac_config()
972 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
974 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
976 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
978 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020); in al_eth_mac_config()
980 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000121); in al_eth_mac_config()
982 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
984 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
986 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020); in al_eth_mac_config()
988 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
990 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000212); in al_eth_mac_config()
992 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000); in al_eth_mac_config()
993 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000001); in al_eth_mac_config()
994 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
995 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
997 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
999 al_reg_write32(&adapter->mac_regs_base->gen_v3.spare, in al_eth_mac_config()
1003 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40053210); in al_eth_mac_config()
1013 al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, 0x01800010); in al_eth_mac_config()
1016 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_empty, 0x00000000); in al_eth_mac_config()
1018 …al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_full, 0x0000000c); /* must be larger tha… in al_eth_mac_config()
1020 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_empty, 0x00000008); in al_eth_mac_config()
1022 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_full, 0x00000008); in al_eth_mac_config()
1026 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_empty, 0x00000008); /* 8 ? */ in al_eth_mac_config()
1028 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_full, 0x0000000c); in al_eth_mac_config()
1030 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_empty, 0x00000008); in al_eth_mac_config()
1032 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_full, 0x00000008); in al_eth_mac_config()
1035 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x000000c0); in al_eth_mac_config()
1040 al_reg_write32(&adapter->mac_regs_base->gen.mac_1g_cfg, 0x00000002); in al_eth_mac_config()
1042 …al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x000… in al_eth_mac_config()
1043 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); in al_eth_mac_config()
1044 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); in al_eth_mac_config()
1048 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000012); in al_eth_mac_config()
1049 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x00000040); in al_eth_mac_config()
1050 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000013); in al_eth_mac_config()
1051 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x00000000); in al_eth_mac_config()
1055 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000014); in al_eth_mac_config()
1056 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x0000000b); in al_eth_mac_config()
1058 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000004); in al_eth_mac_config()
1059 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x000009A0); in al_eth_mac_config()
1060 al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg, in al_eth_mac_config()
1066 if (adapter->rev_id > AL_ETH_REV_ID_2) { in al_eth_mac_config()
1069 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1071 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1073 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1075 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020); in al_eth_mac_config()
1077 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1079 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020); in al_eth_mac_config()
1081 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1083 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012); in al_eth_mac_config()
1085 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000); in al_eth_mac_config()
1086 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1087 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1088 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000050); in al_eth_mac_config()
1090 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1094 al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022830); in al_eth_mac_config()
1096 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000001); in al_eth_mac_config()
1097 al_reg_write32(&adapter->mac_regs_base->mac_10g.if_mode, 0x00000028); in al_eth_mac_config()
1098 al_reg_write32(&adapter->mac_regs_base->mac_10g.control, 0x00001140); in al_eth_mac_config()
1100 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1101 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1102 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1103 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1104 al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, in al_eth_mac_config()
1106 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210); in al_eth_mac_config()
1107 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); in al_eth_mac_config()
1108 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); in al_eth_mac_config()
1110 al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg, in al_eth_mac_config()
1116 if (adapter->rev_id > AL_ETH_REV_ID_2) { in al_eth_mac_config()
1119 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1121 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1123 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1125 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020); in al_eth_mac_config()
1127 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1129 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
1131 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
1133 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020); in al_eth_mac_config()
1135 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1137 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012); in al_eth_mac_config()
1139 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000); in al_eth_mac_config()
1140 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1141 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1142 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000050); in al_eth_mac_config()
1144 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1148 al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); in al_eth_mac_config()
1150 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005); in al_eth_mac_config()
1152 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1153 al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1); in al_eth_mac_config()
1154 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1155 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1156 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1157 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1158 al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, in al_eth_mac_config()
1160 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210); in al_eth_mac_config()
1161 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); in al_eth_mac_config()
1162 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); in al_eth_mac_config()
1164 al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg, in al_eth_mac_config()
1171 al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, 0x0002110f); in al_eth_mac_config()
1173 if (adapter->rev_id > AL_ETH_REV_ID_2) { in al_eth_mac_config()
1176 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1178 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1180 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1182 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020); in al_eth_mac_config()
1184 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1186 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
1188 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
1190 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020); in al_eth_mac_config()
1192 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1194 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012); in al_eth_mac_config()
1196 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000); in al_eth_mac_config()
1197 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1198 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1199 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x000000a0); in al_eth_mac_config()
1201 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1205 al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); in al_eth_mac_config()
1207 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005); in al_eth_mac_config()
1209 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1210 al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1); in al_eth_mac_config()
1211 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1212 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1213 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1214 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1216 if (adapter->serdes_lane == 0) in al_eth_mac_config()
1217 al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, in al_eth_mac_config()
1220 al_reg_write32(&adapter->mac_regs_base->gen.mux_sel, 0x00077910); in al_eth_mac_config()
1222 if (adapter->serdes_lane == 0) in al_eth_mac_config()
1223 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210); in al_eth_mac_config()
1225 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10000101); in al_eth_mac_config()
1227 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); in al_eth_mac_config()
1228 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); in al_eth_mac_config()
1230 al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg, in al_eth_mac_config()
1234 if (adapter->serdes_lane == 1) in al_eth_mac_config()
1235 al_reg_write32(&adapter->mac_regs_base->gen.los_sel, 0x101); in al_eth_mac_config()
1242 al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); in al_eth_mac_config()
1245 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000001); in al_eth_mac_config()
1247 al_reg_write32(&adapter->mac_regs_base->mac_10g.if_mode, 0x0000002b); in al_eth_mac_config()
1248 al_reg_write32(&adapter->mac_regs_base->mac_10g.control, 0x00009140); in al_eth_mac_config()
1251 al_reg_write32(&adapter->mac_regs_base->mac_10g.link_timer_lo, 0x00000040); in al_eth_mac_config()
1252 al_reg_write32(&adapter->mac_regs_base->mac_10g.link_timer_hi, 0x00000000); in al_eth_mac_config()
1256 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1257 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1258 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1259 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1260 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1261 al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, in al_eth_mac_config()
1263 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210); in al_eth_mac_config()
1264 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); in al_eth_mac_config()
1266 al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg, in al_eth_mac_config()
1274 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1276 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1278 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1280 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00010040); in al_eth_mac_config()
1282 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1284 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
1286 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
1288 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00010040); in al_eth_mac_config()
1290 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1292 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000112); in al_eth_mac_config()
1294 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000010); in al_eth_mac_config()
1295 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1296 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1297 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1299 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1302 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x00000008); in al_eth_mac_config()
1303 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x01022810); in al_eth_mac_config()
1305 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0x00000008); */ in al_eth_mac_config()
1307 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0x00000002); */ in al_eth_mac_config()
1310 al_eth_40g_pcs_reg_write(adapter, 0x00010004, 1023); in al_eth_mac_config()
1311 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0xA04c); in al_eth_mac_config()
1312 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0x204c); in al_eth_mac_config()
1317 al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, in al_eth_mac_config()
1319 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x0000040f); in al_eth_mac_config()
1322 /* al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); */ in al_eth_mac_config()
1324 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005); in al_eth_mac_config()
1326 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1327 al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1); in al_eth_mac_config()
1328 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1329 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1330 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1331 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1332 /* al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x… in al_eth_mac_config()
1333 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210); in al_eth_mac_config()
1334 /* al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); *//* XLG_LL_40G change */ in al_eth_mac_config()
1335 /* al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); *//* XLG_LL_40G change */ in al_eth_mac_config()
1337 al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg, in al_eth_mac_config()
1344 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x0080); in al_eth_mac_config()
1345 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x00000001); in al_eth_mac_config()
1349 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1351 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1353 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1355 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00010040); in al_eth_mac_config()
1357 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1359 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
1361 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
1363 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00010040); in al_eth_mac_config()
1365 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1367 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000112); in al_eth_mac_config()
1369 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000010); in al_eth_mac_config()
1370 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1371 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1372 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1374 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1377 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x00000008); in al_eth_mac_config()
1378 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x01022810); in al_eth_mac_config()
1380 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0x00000008); */ in al_eth_mac_config()
1382 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0x00000002); */ in al_eth_mac_config()
1385 al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, 0x0002110f); in al_eth_mac_config()
1389 al_eth_40g_pcs_reg_write(adapter, 0x00010008, 0x0d80); in al_eth_mac_config()
1391 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_cfg, 0x00440000); in al_eth_mac_config()
1394 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0xE); in al_eth_mac_config()
1395 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0); in al_eth_mac_config()
1398 al_eth_40g_pcs_reg_write(adapter, 0x00010004, 1023); in al_eth_mac_config()
1399 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0xA04c); in al_eth_mac_config()
1400 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0x204c); in al_eth_mac_config()
1404 if (adapter->serdes_lane == 0) in al_eth_mac_config()
1405 al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, in al_eth_mac_config()
1408 al_reg_write32(&adapter->mac_regs_base->gen.mux_sel, 0x06803950); in al_eth_mac_config()
1410 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x0000040f); in al_eth_mac_config()
1413 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005); in al_eth_mac_config()
1415 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1416 al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1); in al_eth_mac_config()
1417 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1418 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1419 if (adapter->serdes_lane == 0) in al_eth_mac_config()
1420 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210); in al_eth_mac_config()
1422 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10000101); in al_eth_mac_config()
1424 al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg, in al_eth_mac_config()
1428 if (adapter->serdes_lane == 1) in al_eth_mac_config()
1429 al_reg_write32(&adapter->mac_regs_base->gen.los_sel, 0x101); in al_eth_mac_config()
1437 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1439 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1441 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1443 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00010040); in al_eth_mac_config()
1445 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1447 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
1449 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
1451 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00010040); in al_eth_mac_config()
1453 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1455 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000112); in al_eth_mac_config()
1457 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000010); in al_eth_mac_config()
1458 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1459 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1460 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1462 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1465 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x00000008); in al_eth_mac_config()
1466 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x01022810); in al_eth_mac_config()
1468 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0x00000008); */ in al_eth_mac_config()
1470 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0x00000002); */ in al_eth_mac_config()
1473 al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, 0x0382110F); in al_eth_mac_config()
1477 al_eth_40g_pcs_reg_write(adapter, 0x00010008, 0x0d81); in al_eth_mac_config()
1479 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_cfg, 0x00440000); in al_eth_mac_config()
1483 al_eth_40g_pcs_reg_write(adapter, 0x00010004, 1023); in al_eth_mac_config()
1484 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0xA04c); in al_eth_mac_config()
1485 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0x204c); in al_eth_mac_config()
1489 …al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x068… in al_eth_mac_config()
1490 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x0000040f); in al_eth_mac_config()
1493 /* al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); */ in al_eth_mac_config()
1495 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005); in al_eth_mac_config()
1497 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1498 al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1); in al_eth_mac_config()
1499 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1500 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1501 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1502 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1503 /* al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x… in al_eth_mac_config()
1504 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210); in al_eth_mac_config()
1505 /* al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); *//* XLG_LL_40G change */ in al_eth_mac_config()
1506 /* al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); *//* XLG_LL_40G change */ in al_eth_mac_config()
1508 al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg, in al_eth_mac_config()
1518 adapter->mac_mode = mode; in al_eth_mac_config()
1525 int al_eth_mac_start(struct al_hal_eth_adapter *adapter) in al_eth_mac_start() argument
1527 if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) { in al_eth_mac_start()
1529 al_reg_write32_masked(&adapter->mac_regs_base->mac_1g.cmd_cfg, in al_eth_mac_start()
1532 } else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) { in al_eth_mac_start()
1534 al_reg_write32_masked(&adapter->mac_regs_base->mac_10g.cmd_cfg, in al_eth_mac_start()
1540 cmd_cfg = al_eth_40g_mac_reg_read(adapter, in al_eth_mac_start()
1546 al_eth_40g_mac_reg_write(adapter, in al_eth_mac_start()
1555 int al_eth_mac_stop(struct al_hal_eth_adapter *adapter) in al_eth_mac_stop() argument
1557 if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) in al_eth_mac_stop()
1559 al_reg_write32_masked(&adapter->mac_regs_base->mac_1g.cmd_cfg, in al_eth_mac_stop()
1562 else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) in al_eth_mac_stop()
1564 al_reg_write32_masked(&adapter->mac_regs_base->mac_10g.cmd_cfg, in al_eth_mac_stop()
1570 cmd_cfg = al_eth_40g_mac_reg_read(adapter, in al_eth_mac_stop()
1576 al_eth_40g_mac_reg_write(adapter, in al_eth_mac_stop()
1584 void al_eth_gearbox_reset(struct al_hal_eth_adapter *adapter, al_bool tx_reset, al_bool rx_reset) in al_eth_gearbox_reset() argument
1589 al_assert(adapter->rev_id > AL_ETH_REV_ID_2); in al_eth_gearbox_reset()
1591 orig_val = al_reg_read32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl); in al_eth_gearbox_reset()
1605 al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, reg); in al_eth_gearbox_reset()
1609 al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, orig_val); in al_eth_gearbox_reset()
1612 int al_eth_fec_enable(struct al_hal_eth_adapter *adapter, al_bool enable) in al_eth_fec_enable() argument
1614 if (adapter->rev_id <= AL_ETH_REV_ID_2) in al_eth_fec_enable()
1618 al_reg_write32_masked(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, in al_eth_fec_enable()
1624 al_reg_write32_masked(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, in al_eth_fec_enable()
1631 int al_eth_fec_stats_get(struct al_hal_eth_adapter *adapter, in al_eth_fec_stats_get() argument
1634 if (adapter->rev_id <= AL_ETH_REV_ID_2) in al_eth_fec_stats_get()
1637 *corrected = al_reg_read32(&adapter->mac_regs_base->stat.v3_pcs_10g_ll_cerr); in al_eth_fec_stats_get()
1638 *uncorrectable = al_reg_read32(&adapter->mac_regs_base->stat.v3_pcs_10g_ll_ncerr); in al_eth_fec_stats_get()
1644 int al_eth_capabilities_get(struct al_hal_eth_adapter *adapter, struct al_eth_capabilities *caps) in al_eth_capabilities_get() argument
1659 switch (adapter->mac_mode) { in al_eth_capabilities_get()
1674 al_err("Eth: unsupported MAC mode %d", adapter->mac_mode); in al_eth_capabilities_get()
1681 struct al_hal_eth_adapter *adapter, in al_eth_mac_link_config_1g_mac() argument
1692 mac_ctrl = al_reg_read32(&adapter->mac_regs_base->mac_1g.cmd_cfg); in al_eth_mac_link_config_1g_mac()
1694 if (adapter->mac_mode == AL_ETH_MAC_MODE_SGMII) { in al_eth_mac_link_config_1g_mac()
1695 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, in al_eth_mac_link_config_1g_mac()
1697 sgmii_ctrl = al_reg_read32(&adapter->mac_regs_base->sgmii.reg_data); in al_eth_mac_link_config_1g_mac()
1713 if (adapter->mac_mode == AL_ETH_MAC_MODE_RGMII) { in al_eth_mac_link_config_1g_mac()
1717 rgmii_ctrl = al_reg_read32(&adapter->mac_regs_base->gen.rgmii_cfg); in al_eth_mac_link_config_1g_mac()
1723 al_reg_write32(&adapter->mac_regs_base->gen.rgmii_cfg, rgmii_ctrl); in al_eth_mac_link_config_1g_mac()
1746 if (adapter->mac_mode == AL_ETH_MAC_MODE_SGMII) { in al_eth_mac_link_config_1g_mac()
1747 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, in al_eth_mac_link_config_1g_mac()
1749 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, in al_eth_mac_link_config_1g_mac()
1752 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, in al_eth_mac_link_config_1g_mac()
1754 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, in al_eth_mac_link_config_1g_mac()
1758 al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, mac_ctrl); in al_eth_mac_link_config_1g_mac()
1762 struct al_hal_eth_adapter *adapter, in al_eth_mac_link_config_10g_mac() argument
1771 if_mode = al_reg_read32(&adapter->mac_regs_base->mac_10g.if_mode); in al_eth_mac_link_config_10g_mac()
1778 control = al_reg_read32(&adapter->mac_regs_base->mac_10g.control); in al_eth_mac_link_config_10g_mac()
1785 al_reg_write32(&adapter->mac_regs_base->mac_10g.control, control); in al_eth_mac_link_config_10g_mac()
1815 al_reg_write32(&adapter->mac_regs_base->mac_10g.if_mode, if_mode); in al_eth_mac_link_config_10g_mac()
1819 int al_eth_mac_link_config(struct al_hal_eth_adapter *adapter, in al_eth_mac_link_config() argument
1825 if ((!AL_ETH_IS_1G_MAC(adapter->mac_mode)) && in al_eth_mac_link_config()
1826 (adapter->mac_mode != AL_ETH_MAC_MODE_SGMII_2_5G)) { in al_eth_mac_link_config()
1828 adapter->name); in al_eth_mac_link_config()
1832 if ((adapter->mac_mode != AL_ETH_MAC_MODE_RGMII) && (an_enable)) { in al_eth_mac_link_config()
1837 al_info("eth [%s]: set auto negotiation to enable\n", adapter->name); in al_eth_mac_link_config()
1839 al_info("eth [%s]: set link speed to %dMbps. %s duplex.\n", adapter->name, in al_eth_mac_link_config()
1844 adapter->name, speed); in al_eth_mac_link_config()
1849 adapter->name); in al_eth_mac_link_config()
1854 if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) in al_eth_mac_link_config()
1855 al_eth_mac_link_config_1g_mac(adapter, in al_eth_mac_link_config()
1861 al_eth_mac_link_config_10g_mac(adapter, in al_eth_mac_link_config()
1870 int al_eth_mac_loopback_config(struct al_hal_eth_adapter *adapter, int enable) in al_eth_mac_loopback_config() argument
1874 al_dbg("eth [%s]: loopback %s\n", adapter->name, state); in al_eth_mac_loopback_config()
1875 if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) { in al_eth_mac_loopback_config()
1877 reg = al_reg_read32(&adapter->mac_regs_base->mac_1g.cmd_cfg); in al_eth_mac_loopback_config()
1882 al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, reg); in al_eth_mac_loopback_config()
1883 } else if ((AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) in al_eth_mac_loopback_config()
1884 && (adapter->rev_id == AL_ETH_REV_ID_3)) { in al_eth_mac_loopback_config()
1887 (uint16_t *)&adapter->mac_regs_base->kr.pcs_addr, ETH_MAC_KR_PCS_CONTROL_1_ADDR); in al_eth_mac_loopback_config()
1889 (uint16_t *)&adapter->mac_regs_base->kr.pcs_data); in al_eth_mac_loopback_config()
1895 (uint16_t *)&adapter->mac_regs_base->kr.pcs_addr, ETH_MAC_KR_PCS_CONTROL_1_ADDR); in al_eth_mac_loopback_config()
1897 (uint16_t *)&adapter->mac_regs_base->kr.pcs_data, reg); in al_eth_mac_loopback_config()
1898 } else if (adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_40G || in al_eth_mac_loopback_config()
1899 (adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_50G)) { in al_eth_mac_loopback_config()
1901 reg = al_eth_40g_pcs_reg_read(adapter, ETH_MAC_GEN_V3_PCS_40G_CONTROL_STATUS_ADDR); in al_eth_mac_loopback_config()
1906 al_eth_40g_pcs_reg_write(adapter, ETH_MAC_GEN_V3_PCS_40G_CONTROL_STATUS_ADDR, reg); in al_eth_mac_loopback_config()
1908 al_err("Eth: mac loopback not supported in this mode %d", adapter->mac_mode); in al_eth_mac_loopback_config()
1916 struct al_hal_eth_adapter *adapter, in al_eth_mdio_config() argument
1930 …al_dbg("eth [%s]: mdio config: interface %s. type %s. shared: %s\n", adapter->name, if_name, type_… in al_eth_mdio_config()
1931 adapter->shared_mdio_if = shared_mdio_if; in al_eth_mdio_config()
1933 val = al_reg_read32(&adapter->mac_regs_base->gen.cfg); in al_eth_mdio_config()
1934 al_dbg("eth [%s]: mdio config: 10G mac \n", adapter->name); in al_eth_mdio_config()
1945 al_reg_write32(&adapter->mac_regs_base->gen.cfg, val); in al_eth_mdio_config()
1946 adapter->mdio_if = mdio_if; in al_eth_mdio_config()
1951 val = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status); in al_eth_mdio_config()
1967 adapter->name, __func__, ref_clk_freq); in al_eth_mdio_config()
1990 al_reg_write32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status, val); in al_eth_mdio_config()
1994 adapter->name); in al_eth_mdio_config()
1998 adapter->mdio_type = mdio_type; in al_eth_mdio_config()
2003 static int al_eth_mdio_1g_mac_read(struct al_hal_eth_adapter *adapter, in al_eth_mdio_1g_mac_read() argument
2008 &adapter->mac_regs_base->mac_1g.phy_regs_base + reg); in al_eth_mdio_1g_mac_read()
2012 static int al_eth_mdio_1g_mac_write(struct al_hal_eth_adapter *adapter, in al_eth_mdio_1g_mac_write() argument
2017 &adapter->mac_regs_base->mac_1g.phy_regs_base + reg, val); in al_eth_mdio_1g_mac_write()
2021 static int al_eth_mdio_10g_mac_wait_busy(struct al_hal_eth_adapter *adapter) in al_eth_mdio_10g_mac_wait_busy() argument
2027 mdio_cfg_status = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status); in al_eth_mdio_10g_mac_wait_busy()
2036 al_dbg("eth [%s] mdio: still busy!\n", adapter->name); in al_eth_mdio_10g_mac_wait_busy()
2047 struct al_hal_eth_adapter *adapter, in al_eth_mdio_10g_mac_type22() argument
2056 rc = al_eth_mdio_10g_mac_wait_busy(adapter); in al_eth_mdio_10g_mac_type22()
2058 al_err(" eth [%s] mdio %s failed. HW is busy\n", adapter->name, op); in al_eth_mdio_10g_mac_type22()
2068 al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_cmd, in al_eth_mdio_10g_mac_type22()
2071 al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_data, in al_eth_mdio_10g_mac_type22()
2075 rc = al_eth_mdio_10g_mac_wait_busy(adapter); in al_eth_mdio_10g_mac_type22()
2077 al_err(" %s mdio %s failed on timeout\n", adapter->name, op); in al_eth_mdio_10g_mac_type22()
2081 mdio_cfg_status = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status); in al_eth_mdio_10g_mac_type22()
2085 adapter->name, op, phy_addr, reg); in al_eth_mdio_10g_mac_type22()
2090 (uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_data); in al_eth_mdio_10g_mac_type22()
2095 struct al_hal_eth_adapter *adapter, in al_eth_mdio_10g_mac_type45() argument
2104 rc = al_eth_mdio_10g_mac_wait_busy(adapter); in al_eth_mdio_10g_mac_type45()
2106 al_err(" %s mdio %s failed. HW is busy\n", adapter->name, op); in al_eth_mdio_10g_mac_type45()
2112 al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_cmd, in al_eth_mdio_10g_mac_type45()
2116 al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_regaddr, reg); in al_eth_mdio_10g_mac_type45()
2118 rc = al_eth_mdio_10g_mac_wait_busy(adapter); in al_eth_mdio_10g_mac_type45()
2120 al_err(" %s mdio %s (address frame) failed on timeout\n", adapter->name, op); in al_eth_mdio_10g_mac_type45()
2128 (uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_cmd, in al_eth_mdio_10g_mac_type45()
2132 (uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_data, in al_eth_mdio_10g_mac_type45()
2136 rc = al_eth_mdio_10g_mac_wait_busy(adapter); in al_eth_mdio_10g_mac_type45()
2138 al_err(" %s mdio %s failed on timeout\n", adapter->name, op); in al_eth_mdio_10g_mac_type45()
2142 mdio_cfg_status = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status); in al_eth_mdio_10g_mac_type45()
2146 adapter->name, op, port_addr, device, reg); in al_eth_mdio_10g_mac_type45()
2151 (uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_data); in al_eth_mdio_10g_mac_type45()
2160 * @param adapter
2163 static int al_eth_mdio_lock(struct al_hal_eth_adapter *adapter) in al_eth_mdio_lock() argument
2168 if (adapter->shared_mdio_if == AL_FALSE) in al_eth_mdio_lock()
2172 mdio_ctrl_1 = al_reg_read32(&adapter->mac_regs_base->gen.mdio_ctrl_1); in al_eth_mdio_lock()
2181 al_dbg("eth %s mdio interface still busy!\n", adapter->name); in al_eth_mdio_lock()
2188 adapter->name, al_reg_read32(&adapter->mac_regs_base->gen.mdio_1)); in al_eth_mdio_lock()
2198 * @param adapter
2201 static int al_eth_mdio_free(struct al_hal_eth_adapter *adapter) in al_eth_mdio_free() argument
2203 if (adapter->shared_mdio_if == AL_FALSE) in al_eth_mdio_free()
2206 al_reg_write32(&adapter->mac_regs_base->gen.mdio_ctrl_1, 0); in al_eth_mdio_free()
2225 int al_eth_mdio_read(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, uint32_t device, uint32… in al_eth_mdio_read() argument
2228 rc = al_eth_mdio_lock(adapter); in al_eth_mdio_read()
2234 if (adapter->mdio_if == AL_ETH_MDIO_IF_1G_MAC) in al_eth_mdio_read()
2235 rc = al_eth_mdio_1g_mac_read(adapter, phy_addr, reg, val); in al_eth_mdio_read()
2237 if (adapter->mdio_type == AL_ETH_MDIO_TYPE_CLAUSE_22) in al_eth_mdio_read()
2238 rc = al_eth_mdio_10g_mac_type22(adapter, 1, phy_addr, reg, val); in al_eth_mdio_read()
2240 rc = al_eth_mdio_10g_mac_type45(adapter, 1, phy_addr, device, reg, val); in al_eth_mdio_read()
2242 al_eth_mdio_free(adapter); in al_eth_mdio_read()
2247 int al_eth_mdio_write(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, uint32_t device, uint3… in al_eth_mdio_write() argument
2251 rc = al_eth_mdio_lock(adapter); in al_eth_mdio_write()
2256 if (adapter->mdio_if == AL_ETH_MDIO_IF_1G_MAC) in al_eth_mdio_write()
2257 rc = al_eth_mdio_1g_mac_write(adapter, phy_addr, reg, val); in al_eth_mdio_write()
2259 if (adapter->mdio_type == AL_ETH_MDIO_TYPE_CLAUSE_22) in al_eth_mdio_write()
2260 rc = al_eth_mdio_10g_mac_type22(adapter, 0, phy_addr, reg, &val); in al_eth_mdio_write()
2262 rc = al_eth_mdio_10g_mac_type45(adapter, 0, phy_addr, device, reg, &val); in al_eth_mdio_write()
2264 al_eth_mdio_free(adapter); in al_eth_mdio_write()
2596 int al_eth_tso_mss_config(struct al_hal_eth_adapter *adapter, uint8_t idx, uint32_t mss_val) in al_eth_tso_mss_config() argument
2603 al_reg_write32(&adapter->ec_regs_base->tso_sel[idx].mss, mss_val); in al_eth_tso_mss_config()
2613 struct al_hal_eth_adapter *adapter, in al_eth_rx_desc_config() argument
2633 al_reg_write32(&adapter->ec_regs_base->rfw.cfg_a_0, reg_val); in al_eth_rx_desc_config()
2635 reg_val = al_reg_read32(&adapter->ec_regs_base->rfw.meta); in al_eth_rx_desc_config()
2662 al_reg_write32(&adapter->ec_regs_base->rfw.meta, reg_val); in al_eth_rx_desc_config()
2668 int al_eth_rx_header_split_config(struct al_hal_eth_adapter *adapter, al_bool enable, uint32_t head… in al_eth_rx_header_split_config() argument
2672 reg = al_reg_read32(&adapter->ec_regs_base->rfw.hdr_split); in al_eth_rx_header_split_config()
2679 al_reg_write32(&adapter->ec_regs_base->rfw.hdr_split, reg); in al_eth_rx_header_split_config()
2688 int al_eth_rx_header_split_force_len_config(struct al_hal_eth_adapter *adapter, in al_eth_rx_header_split_force_len_config() argument
2693 al_udma_s2m_q_compl_hdr_split_config(&(adapter->rx_udma.udma_q[qid]), enable, in al_eth_rx_header_split_force_len_config()
2815 int al_eth_rx_parser_entry_update(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_rx_parser_entry_update() argument
2819 al_eth_epe_entry_set(adapter, idx, reg_entry, control_entry); in al_eth_rx_parser_entry_update()
2829 int al_eth_thash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma, uint32_t… in al_eth_thash_table_set() argument
2837 al_reg_write32(&adapter->ec_regs_base->rfw.thash_table_addr, idx); in al_eth_thash_table_set()
2838 al_reg_write32(&adapter->ec_regs_base->rfw.thash_table_data, entry); in al_eth_thash_table_set()
2842 int al_eth_fsm_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry) in al_eth_fsm_table_set() argument
2848 al_reg_write32(&adapter->ec_regs_base->rfw.fsm_table_addr, idx); in al_eth_fsm_table_set()
2849 al_reg_write32(&adapter->ec_regs_base->rfw.fsm_table_data, entry); in al_eth_fsm_table_set()
2890 int al_eth_ctrl_table_set(struct al_hal_eth_adapter *adapter, in al_eth_ctrl_table_set() argument
2899 al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_addr, i); in al_eth_ctrl_table_set()
2900 al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_data, val); in al_eth_ctrl_table_set()
2906 int al_eth_ctrl_table_def_set(struct al_hal_eth_adapter *adapter, in al_eth_ctrl_table_def_set() argument
2915 al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_def, val); in al_eth_ctrl_table_def_set()
2920 int al_eth_ctrl_table_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry) in al_eth_ctrl_table_raw_set() argument
2926 al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_addr, idx); in al_eth_ctrl_table_raw_set()
2927 al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_data, entry); in al_eth_ctrl_table_raw_set()
2931 int al_eth_ctrl_table_def_raw_set(struct al_hal_eth_adapter *adapter, uint32_t val) in al_eth_ctrl_table_def_raw_set() argument
2933 al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_def, val); in al_eth_ctrl_table_def_raw_set()
2938 int al_eth_hash_key_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t val) in al_eth_hash_key_set() argument
2943 al_reg_write32(&adapter->ec_regs_base->rfw_hash[idx].key, val); in al_eth_hash_key_set()
2969 int al_eth_fwd_mac_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_fwd_mac_table_set() argument
2978 al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_l, val); in al_eth_fwd_mac_table_set()
2980 al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_h, val); in al_eth_fwd_mac_table_set()
2983 al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_l, val); in al_eth_fwd_mac_table_set()
2985 al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_h, val); in al_eth_fwd_mac_table_set()
2988 al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].ctrl, val); in al_eth_fwd_mac_table_set()
2994 int al_eth_fwd_mac_addr_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t addr_lo,… in al_eth_fwd_mac_addr_raw_set() argument
2998 al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_l, addr_lo); in al_eth_fwd_mac_addr_raw_set()
2999 al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_h, addr_hi); in al_eth_fwd_mac_addr_raw_set()
3000 al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_l, mask_lo); in al_eth_fwd_mac_addr_raw_set()
3001 al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_h, mask_hi); in al_eth_fwd_mac_addr_raw_set()
3006 int al_eth_fwd_mac_ctrl_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t ctrl) in al_eth_fwd_mac_ctrl_raw_set() argument
3010 al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].ctrl, ctrl); in al_eth_fwd_mac_ctrl_raw_set()
3044 int al_eth_fwd_mhash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask,… in al_eth_fwd_mhash_table_set() argument
3052 al_reg_write32(&adapter->ec_regs_base->rfw.mhash_table_addr, idx); in al_eth_fwd_mhash_table_set()
3053 al_reg_write32(&adapter->ec_regs_base->rfw.mhash_table_data, val); in al_eth_fwd_mhash_table_set()
3066 int al_eth_fwd_vid_config_set(struct al_hal_eth_adapter *adapter, al_bool use_table, in al_eth_fwd_vid_config_set() argument
3077 al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_def, reg); in al_eth_fwd_vid_config_set()
3078 al_reg_write32(&adapter->ec_regs_base->rfw.default_vlan, default_vlan); in al_eth_fwd_vid_config_set()
3083 int al_eth_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_fwd_vid_table_set() argument
3090 al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_addr, idx); in al_eth_fwd_vid_table_set()
3091 al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_data, val); in al_eth_fwd_vid_table_set()
3095 int al_eth_fwd_pbits_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio) in al_eth_fwd_pbits_table_set() argument
3100 al_reg_write32(&adapter->ec_regs_base->rfw.pbits_table_addr, idx); in al_eth_fwd_pbits_table_set()
3101 al_reg_write32(&adapter->ec_regs_base->rfw.pbits_table_data, prio); in al_eth_fwd_pbits_table_set()
3105 int al_eth_fwd_priority_table_set(struct al_hal_eth_adapter *adapter, uint8_t prio, uint8_t qid) in al_eth_fwd_priority_table_set() argument
3109 al_reg_write32(&adapter->ec_regs_base->rfw_priority[prio].queue, qid); in al_eth_fwd_priority_table_set()
3114 int al_eth_fwd_dscp_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio) in al_eth_fwd_dscp_table_set() argument
3120 al_reg_write32(&adapter->ec_regs_base->rfw.dscp_table_addr, idx); in al_eth_fwd_dscp_table_set()
3121 al_reg_write32(&adapter->ec_regs_base->rfw.dscp_table_data, prio); in al_eth_fwd_dscp_table_set()
3125 int al_eth_fwd_tc_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio) in al_eth_fwd_tc_table_set() argument
3131 al_reg_write32(&adapter->ec_regs_base->rfw.tc_table_addr, idx); in al_eth_fwd_tc_table_set()
3132 al_reg_write32(&adapter->ec_regs_base->rfw.tc_table_data, prio); in al_eth_fwd_tc_table_set()
3137 int al_eth_fwd_default_udma_config(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_fwd_default_udma_config() argument
3140 al_reg_write32_masked(&adapter->ec_regs_base->rfw_default[idx].opt_1, in al_eth_fwd_default_udma_config()
3147 int al_eth_fwd_default_queue_config(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_fwd_default_queue_config() argument
3150 al_reg_write32_masked(&adapter->ec_regs_base->rfw_default[idx].opt_1, in al_eth_fwd_default_queue_config()
3157 int al_eth_fwd_default_priority_config(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_fwd_default_priority_config() argument
3160 al_reg_write32_masked(&adapter->ec_regs_base->rfw_default[idx].opt_1, in al_eth_fwd_default_priority_config()
3166 int al_eth_switching_config_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t forwar… in al_eth_switching_config_set() argument
3175 reg = al_reg_read32(&adapter->ec_regs_base->tfw.tx_gen); in al_eth_switching_config_set()
3180 al_reg_write32(&adapter->ec_regs_base->tfw.tx_gen, reg); in al_eth_switching_config_set()
3188 al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].fwd_dec, reg); in al_eth_switching_config_set()
3207 int al_eth_filter_config(struct al_hal_eth_adapter *adapter, struct al_eth_filter_params *params) in al_eth_filter_config() argument
3213 if (params->filters & ~(AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id))) { in al_eth_filter_config()
3214 al_err("[%s]: unsupported filter options (0x%08x)\n", adapter->name, params->filters); in al_eth_filter_config()
3218 reg = al_reg_read32(&adapter->ec_regs_base->rfw.out_cfg); in al_eth_filter_config()
3223 al_reg_write32(&adapter->ec_regs_base->rfw.out_cfg, reg); in al_eth_filter_config()
3226 &adapter->ec_regs_base->rfw.filter, in al_eth_filter_config()
3227 AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id), in al_eth_filter_config()
3232 reg = al_reg_read32(&adapter->ec_regs_base->epe_a[i].prot_act); in al_eth_filter_config()
3237 al_reg_write32(&adapter->ec_regs_base->epe_a[i].prot_act, reg); in al_eth_filter_config()
3244 int al_eth_filter_override_config(struct al_hal_eth_adapter *adapter, in al_eth_filter_override_config() argument
3251 if (params->filters & ~(AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id))) { in al_eth_filter_override_config()
3252 al_err("[%s]: unsupported override filter options (0x%08x)\n", adapter->name, params->filters); in al_eth_filter_override_config()
3257 &adapter->ec_regs_base->rfw.filter, in al_eth_filter_override_config()
3258 AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id) << 16, in al_eth_filter_override_config()
3261 reg = al_reg_read32(&adapter->ec_regs_base->rfw.default_or); in al_eth_filter_override_config()
3264 al_reg_write32(&adapter->ec_regs_base->rfw.default_or, reg); in al_eth_filter_override_config()
3270 int al_eth_switching_default_bitmap_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_… in al_eth_switching_default_bitmap_set() argument
3273 al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].uc_udma, udma_uc_bitmask); in al_eth_switching_default_bitmap_set()
3274 al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].mc_udma, udma_mc_bitmask); in al_eth_switching_default_bitmap_set()
3275 al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].bc_udma, udma_bc_bitmask); in al_eth_switching_default_bitmap_set()
3280 int al_eth_flow_control_config(struct al_hal_eth_adapter *adapter, struct al_eth_flow_control_param… in al_eth_flow_control_config() argument
3288 al_dbg("[%s]: config flow control to link pause mode.\n", adapter->name); in al_eth_flow_control_config()
3291 if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) { in al_eth_flow_control_config()
3294 &adapter->mac_regs_base->mac_1g.pause_quant, in al_eth_flow_control_config()
3297 &adapter->ec_regs_base->efc.xoff_timer_1g, in al_eth_flow_control_config()
3300 } else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) { in al_eth_flow_control_config()
3303 &adapter->mac_regs_base->mac_10g.cl01_pause_quanta, in al_eth_flow_control_config()
3307 &adapter->mac_regs_base->mac_10g.cl01_quanta_thresh, in al_eth_flow_control_config()
3311 al_eth_40g_mac_reg_write(adapter, in al_eth_flow_control_config()
3315 al_eth_40g_mac_reg_write(adapter, in al_eth_flow_control_config()
3322 al_reg_write32(&adapter->ec_regs_base->efc.ec_pause, 1); in al_eth_flow_control_config()
3324 al_reg_write32(&adapter->ec_regs_base->efc.ec_pause, 0); in al_eth_flow_control_config()
3330 al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 1 << EC_EFC_EC_XOFF_MASK_2_SHIFT); in al_eth_flow_control_config()
3332 al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0); in al_eth_flow_control_config()
3334 if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) in al_eth_flow_control_config()
3336 al_reg_write32(&adapter->ec_regs_base->efc.xon, EC_EFC_XON_MASK_2 | EC_EFC_XON_MASK_1); in al_eth_flow_control_config()
3339 …al_reg_write32(&adapter->ec_regs_base->efc.rx_fifo_hyst, params->rx_fifo_th_low | (params->rx_fifo… in al_eth_flow_control_config()
3344 al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0, in al_eth_flow_control_config()
3347 al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0, 0); in al_eth_flow_control_config()
3351 al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0, params->prio_q_map[i][0]); in al_eth_flow_control_config()
3353 al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0, 0); in al_eth_flow_control_config()
3357 al_dbg("[%s]: config flow control to PFC mode.\n", adapter->name); in al_eth_flow_control_config()
3358 al_assert(!AL_ETH_IS_1G_MAC(adapter->mac_mode)); /* pfc not available for RGMII mode */; in al_eth_flow_control_config()
3365 al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0 + prio, in al_eth_flow_control_config()
3368 al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0 + prio, in al_eth_flow_control_config()
3372 al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0 + prio, in al_eth_flow_control_config()
3375 al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0 + prio, in al_eth_flow_control_config()
3383 al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0xFF << EC_EFC_EC_XOFF_MASK_2_SHIFT); in al_eth_flow_control_config()
3385 al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0); in al_eth_flow_control_config()
3388 …al_reg_write32(&adapter->ec_regs_base->efc.rx_fifo_hyst, params->rx_fifo_th_low | (params->rx_fifo… in al_eth_flow_control_config()
3390 if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) { in al_eth_flow_control_config()
3395 &adapter->mac_regs_base->mac_10g.cl01_pause_quanta, reg); in al_eth_flow_control_config()
3397 &adapter->mac_regs_base->mac_10g.cl23_pause_quanta, reg); in al_eth_flow_control_config()
3399 &adapter->mac_regs_base->mac_10g.cl45_pause_quanta, reg); in al_eth_flow_control_config()
3401 &adapter->mac_regs_base->mac_10g.cl67_pause_quanta, reg); in al_eth_flow_control_config()
3405 &adapter->mac_regs_base->mac_10g.cl01_quanta_thresh, reg); in al_eth_flow_control_config()
3407 &adapter->mac_regs_base->mac_10g.cl23_quanta_thresh, reg); in al_eth_flow_control_config()
3409 &adapter->mac_regs_base->mac_10g.cl45_quanta_thresh, reg); in al_eth_flow_control_config()
3411 &adapter->mac_regs_base->mac_10g.cl67_quanta_thresh, reg); in al_eth_flow_control_config()
3414 reg = al_reg_read32(&adapter->mac_regs_base->mac_10g.cmd_cfg); in al_eth_flow_control_config()
3416 al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, reg); in al_eth_flow_control_config()
3421 al_eth_40g_mac_reg_write(adapter, in al_eth_flow_control_config()
3423 al_eth_40g_mac_reg_write(adapter, in al_eth_flow_control_config()
3425 al_eth_40g_mac_reg_write(adapter, in al_eth_flow_control_config()
3427 al_eth_40g_mac_reg_write(adapter, in al_eth_flow_control_config()
3431 al_eth_40g_mac_reg_write(adapter, in al_eth_flow_control_config()
3433 al_eth_40g_mac_reg_write(adapter, in al_eth_flow_control_config()
3435 al_eth_40g_mac_reg_write(adapter, in al_eth_flow_control_config()
3437 al_eth_40g_mac_reg_write(adapter, in al_eth_flow_control_config()
3441 reg = al_reg_read32(&adapter->mac_regs_base->mac_10g.cmd_cfg); in al_eth_flow_control_config()
3443 al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, reg); in al_eth_flow_control_config()
3444 reg = al_eth_40g_mac_reg_read(adapter, ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR); in al_eth_flow_control_config()
3448 al_eth_40g_mac_reg_write(adapter, ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR, reg); in al_eth_flow_control_config()
3453 al_err("[%s]: unsupported flow control type %d\n", adapter->name, params->type); in al_eth_flow_control_config()
3460 int al_eth_vlan_mod_config(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint16_t udma_etype… in al_eth_vlan_mod_config() argument
3462 al_dbg("[%s]: config vlan modification registers. udma id %d.\n", adapter->name, udma_id); in al_eth_vlan_mod_config()
3464 al_reg_write32(&adapter->ec_regs_base->tpm_sel[udma_id].etype, udma_etype); in al_eth_vlan_mod_config()
3465 …al_reg_write32(&adapter->ec_regs_base->tpm_udma[udma_id].vlan_data, vlan1_data | (vlan2_data << 16… in al_eth_vlan_mod_config()
3470 int al_eth_eee_get(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params) in al_eth_eee_get() argument
3474 al_dbg("[%s]: getting eee.\n", adapter->name); in al_eth_eee_get()
3476 reg = al_reg_read32(&adapter->ec_regs_base->eee.cfg_e); in al_eth_eee_get()
3479 params->tx_eee_timer = al_reg_read32(&adapter->ec_regs_base->eee.pre_cnt); in al_eth_eee_get()
3480 params->min_interval = al_reg_read32(&adapter->ec_regs_base->eee.post_cnt); in al_eth_eee_get()
3481 params->stop_cnt = al_reg_read32(&adapter->ec_regs_base->eee.stop_cnt); in al_eth_eee_get()
3487 int al_eth_eee_config(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params) in al_eth_eee_config() argument
3490 al_dbg("[%s]: config eee.\n", adapter->name); in al_eth_eee_config()
3493 al_dbg("[%s]: disable eee.\n", adapter->name); in al_eth_eee_config()
3494 al_reg_write32(&adapter->ec_regs_base->eee.cfg_e, 0); in al_eth_eee_config()
3497 if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) { in al_eth_eee_config()
3499 &adapter->mac_regs_base->kr.pcs_cfg, in al_eth_eee_config()
3501 ((AL_ETH_IS_10G_MAC(adapter->mac_mode)) ? in al_eth_eee_config()
3506 if ((adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_40G) || in al_eth_eee_config()
3507 (adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_50G)) { in al_eth_eee_config()
3509 &adapter->mac_regs_base->gen_v3.pcs_40g_ll_eee_cfg, in al_eth_eee_config()
3511 ((adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_40G) ? in al_eth_eee_config()
3516 al_eth_40g_pcs_reg_write(adapter, ETH_MAC_GEN_V3_PCS_40G_EEE_CONTROL_ADDR, in al_eth_eee_config()
3520 al_reg_write32(&adapter->ec_regs_base->eee.pre_cnt, params->tx_eee_timer); in al_eth_eee_config()
3521 al_reg_write32(&adapter->ec_regs_base->eee.post_cnt, params->min_interval); in al_eth_eee_config()
3522 al_reg_write32(&adapter->ec_regs_base->eee.stop_cnt, params->stop_cnt); in al_eth_eee_config()
3544 al_reg_write32(&adapter->ec_regs_base->eee.cfg_e, reg); in al_eth_eee_config()
3550 /* prepare the adapter for doing Timestamps for Rx packets. */
3551 int al_eth_ts_init(struct al_hal_eth_adapter *adapter) in al_eth_ts_init() argument
3560 reg = al_reg_read32(&adapter->ec_regs_base->gen.en_ext); in al_eth_ts_init()
3561 if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) in al_eth_ts_init()
3570 al_reg_write32(&adapter->ec_regs_base->gen.en_ext, reg); in al_eth_ts_init()
3581 int al_eth_tx_ts_val_get(struct al_hal_eth_adapter *adapter, uint8_t ts_index, in al_eth_tx_ts_val_get() argument
3587 if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) { in al_eth_tx_ts_val_get()
3593 *timestamp = al_reg_read32(&adapter->ec_regs_base->pth_db[ts_index].ts); in al_eth_tx_ts_val_get()
3598 int al_eth_pth_systime_read(struct al_hal_eth_adapter *adapter, in al_eth_pth_systime_read() argument
3606 reg = al_reg_read32(&adapter->ec_regs_base->pth.system_time_subseconds_msb); in al_eth_pth_systime_read()
3608 reg = al_reg_read32(&adapter->ec_regs_base->pth.system_time_seconds); in al_eth_pth_systime_read()
3615 int al_eth_pth_clk_period_write(struct al_hal_eth_adapter *adapter, in al_eth_pth_clk_period_write() argument
3624 al_reg_write32(&adapter->ec_regs_base->pth.clock_period_lsb, reg); in al_eth_pth_clk_period_write()
3626 al_reg_write32(&adapter->ec_regs_base->pth.clock_period_msb, reg); in al_eth_pth_clk_period_write()
3632 int al_eth_pth_int_update_config(struct al_hal_eth_adapter *adapter, in al_eth_pth_int_update_config() argument
3637 reg = al_reg_read32(&adapter->ec_regs_base->pth.int_update_ctrl); in al_eth_pth_int_update_config()
3650 al_reg_write32(&adapter->ec_regs_base->pth.int_update_ctrl, reg); in al_eth_pth_int_update_config()
3654 int al_eth_pth_int_update_time_set(struct al_hal_eth_adapter *adapter, in al_eth_pth_int_update_time_set() argument
3659 al_reg_write32(&adapter->ec_regs_base->pth.int_update_seconds, in al_eth_pth_int_update_time_set()
3663 al_reg_write32(&adapter->ec_regs_base->pth.int_update_subseconds_lsb, in al_eth_pth_int_update_time_set()
3666 al_reg_write32(&adapter->ec_regs_base->pth.int_update_subseconds_msb, in al_eth_pth_int_update_time_set()
3673 int al_eth_pth_ext_update_config(struct al_hal_eth_adapter *adapter, in al_eth_pth_ext_update_config() argument
3678 reg = al_reg_read32(&adapter->ec_regs_base->pth.int_update_ctrl); in al_eth_pth_ext_update_config()
3686 al_reg_write32(&adapter->ec_regs_base->pth.int_update_ctrl, reg); in al_eth_pth_ext_update_config()
3691 int al_eth_pth_ext_update_time_set(struct al_hal_eth_adapter *adapter, in al_eth_pth_ext_update_time_set() argument
3696 al_reg_write32(&adapter->ec_regs_base->pth.ext_update_seconds, in al_eth_pth_ext_update_time_set()
3700 al_reg_write32(&adapter->ec_regs_base->pth.ext_update_subseconds_lsb, in al_eth_pth_ext_update_time_set()
3703 al_reg_write32(&adapter->ec_regs_base->pth.ext_update_subseconds_msb, in al_eth_pth_ext_update_time_set()
3710 int al_eth_pth_read_compensation_set(struct al_hal_eth_adapter *adapter, in al_eth_pth_read_compensation_set() argument
3717 al_reg_write32(&adapter->ec_regs_base->pth.read_compensation_subseconds_lsb, reg); in al_eth_pth_read_compensation_set()
3720 al_reg_write32(&adapter->ec_regs_base->pth.read_compensation_subseconds_msb, reg); in al_eth_pth_read_compensation_set()
3725 int al_eth_pth_int_write_compensation_set(struct al_hal_eth_adapter *adapter, in al_eth_pth_int_write_compensation_set() argument
3732 al_reg_write32(&adapter->ec_regs_base->pth.int_write_compensation_subseconds_lsb, reg); in al_eth_pth_int_write_compensation_set()
3735 al_reg_write32(&adapter->ec_regs_base->pth.int_write_compensation_subseconds_msb, reg); in al_eth_pth_int_write_compensation_set()
3740 int al_eth_pth_ext_write_compensation_set(struct al_hal_eth_adapter *adapter, in al_eth_pth_ext_write_compensation_set() argument
3747 al_reg_write32(&adapter->ec_regs_base->pth.ext_write_compensation_subseconds_lsb, reg); in al_eth_pth_ext_write_compensation_set()
3750 al_reg_write32(&adapter->ec_regs_base->pth.ext_write_compensation_subseconds_msb, reg); in al_eth_pth_ext_write_compensation_set()
3755 int al_eth_pth_sync_compensation_set(struct al_hal_eth_adapter *adapter, in al_eth_pth_sync_compensation_set() argument
3762 al_reg_write32(&adapter->ec_regs_base->pth.sync_compensation_subseconds_lsb, reg); in al_eth_pth_sync_compensation_set()
3765 al_reg_write32(&adapter->ec_regs_base->pth.sync_compensation_subseconds_msb, reg); in al_eth_pth_sync_compensation_set()
3770 int al_eth_pth_pulse_out_config(struct al_hal_eth_adapter *adapter, in al_eth_pth_pulse_out_config() argument
3777 adapter->name); in al_eth_pth_pulse_out_config()
3780 reg = al_reg_read32(&adapter->ec_regs_base->pth_egress[params->index].trigger_ctrl); in al_eth_pth_pulse_out_config()
3797 al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_ctrl, reg); in al_eth_pth_pulse_out_config()
3800 al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_seconds, in al_eth_pth_pulse_out_config()
3804 al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_subseconds_lsb, in al_eth_pth_pulse_out_config()
3807 al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_subseconds_msb, in al_eth_pth_pulse_out_config()
3813 al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].pulse_width_subseconds_lsb, reg); in al_eth_pth_pulse_out_config()
3816 al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].pulse_width_subseconds_msb, reg); in al_eth_pth_pulse_out_config()
3822 int al_eth_link_status_get(struct al_hal_eth_adapter *adapter, in al_eth_link_status_get() argument
3827 if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) { in al_eth_link_status_get()
3832 al_reg_write32(&adapter->mac_regs_base->kr.pcs_addr, ETH_MAC_KR_PCS_BASE_R_STATUS2); in al_eth_link_status_get()
3833 reg = al_reg_read32(&adapter->mac_regs_base->kr.pcs_data); in al_eth_link_status_get()
3836 reg = al_reg_read32(&adapter->mac_regs_base->mac_10g.status); in al_eth_link_status_get()
3847 } else if (adapter->mac_mode == AL_ETH_MAC_MODE_SGMII) { in al_eth_link_status_get()
3848 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 1); in al_eth_link_status_get()
3853 reg = al_reg_read32(&adapter->mac_regs_base->sgmii.reg_data); in al_eth_link_status_get()
3854 reg = al_reg_read32(&adapter->mac_regs_base->sgmii.reg_data); in al_eth_link_status_get()
3861 reg = al_reg_read32(&adapter->mac_regs_base->sgmii.link_stat); in al_eth_link_status_get()
3866 } else if (adapter->mac_mode == AL_ETH_MAC_MODE_RGMII) { in al_eth_link_status_get()
3867 reg = al_reg_read32(&adapter->mac_regs_base->gen.rgmii_stat); in al_eth_link_status_get()
3874 } else if (adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_25G) { in al_eth_link_status_get()
3879 reg = al_reg_read32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_status); in al_eth_link_status_get()
3884 reg = al_reg_read32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_status); in al_eth_link_status_get()
3895 } else if ((adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_40G) || in al_eth_link_status_get()
3896 (adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_50G)) { in al_eth_link_status_get()
3897 reg = al_reg_read32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_status); in al_eth_link_status_get()
3902 reg = al_reg_read32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_status); in al_eth_link_status_get()
3913 al_dbg("[%s]: mac %s port. link_status: %s.\n", adapter->name, in al_eth_link_status_get()
3914 al_eth_mac_mode_str(adapter->mac_mode), in al_eth_link_status_get()
3920 int al_eth_link_status_clear(struct al_hal_eth_adapter *adapter) in al_eth_link_status_clear() argument
3924 if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) { in al_eth_link_status_clear()
3925 al_reg_write32(&adapter->mac_regs_base->kr.pcs_addr, ETH_MAC_KR_PCS_BASE_R_STATUS2); in al_eth_link_status_clear()
3926 al_reg_read32(&adapter->mac_regs_base->kr.pcs_data); in al_eth_link_status_clear()
3928 al_reg_read32(&adapter->mac_regs_base->mac_10g.status); in al_eth_link_status_clear()
3937 int al_eth_led_set(struct al_hal_eth_adapter *adapter, al_bool link_is_up) in al_eth_led_set() argument
3956 al_reg_write32(&adapter->mac_regs_base->gen.led_cfg, reg); in al_eth_led_set()
3962 int al_eth_mac_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_mac_stats *stats) in al_eth_mac_stats_get() argument
3968 if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) { in al_eth_mac_stats_get()
3970 &adapter->mac_regs_base->mac_1g.stats; in al_eth_mac_stats_get()
4014 } else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) { in al_eth_mac_stats_get()
4015 if (adapter->rev_id < AL_ETH_REV_ID_3) { in al_eth_mac_stats_get()
4017 &adapter->mac_regs_base->mac_10g.stats.v2; in al_eth_mac_stats_get()
4069 &adapter->mac_regs_base->mac_10g.stats.v3.rx; in al_eth_mac_stats_get()
4071 &adapter->mac_regs_base->mac_10g.stats.v3.tx; in al_eth_mac_stats_get()
4124 &adapter->mac_regs_base->mac_10g.stats.v3.rx; in al_eth_mac_stats_get()
4126 &adapter->mac_regs_base->mac_10g.stats.v3.tx; in al_eth_mac_stats_get()
4130 #define _40g_mac_reg_read32(field) al_eth_40g_mac_reg_read(adapter, \ in al_eth_mac_stats_get()
4131 ((uint8_t *)(field)) - ((uint8_t *)&adapter->mac_regs_base->mac_10g)) in al_eth_mac_stats_get()
4182 stats->eee_in = al_reg_read32(&adapter->mac_regs_base->stat.eee_in); in al_eth_mac_stats_get()
4183 stats->eee_out = al_reg_read32(&adapter->mac_regs_base->stat.eee_out); in al_eth_mac_stats_get()
4192 int al_eth_ec_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_ec_stats *stats) in al_eth_ec_stats_get() argument
4195 stats->faf_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.faf_in_rx_pkt); in al_eth_ec_stats_get()
4196 stats->faf_in_rx_short = al_reg_read32(&adapter->ec_regs_base->stat.faf_in_rx_short); in al_eth_ec_stats_get()
4197 stats->faf_in_rx_long = al_reg_read32(&adapter->ec_regs_base->stat.faf_in_rx_long); in al_eth_ec_stats_get()
4198 stats->faf_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_rx_pkt); in al_eth_ec_stats_get()
4199 stats->faf_out_rx_short = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_rx_short); in al_eth_ec_stats_get()
4200 stats->faf_out_rx_long = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_rx_long); in al_eth_ec_stats_get()
4201 stats->faf_out_drop = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_drop); in al_eth_ec_stats_get()
4202 stats->rxf_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_in_rx_pkt); in al_eth_ec_stats_get()
4203 stats->rxf_in_fifo_err = al_reg_read32(&adapter->ec_regs_base->stat.rxf_in_fifo_err); in al_eth_ec_stats_get()
4204 stats->lbf_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.lbf_in_rx_pkt); in al_eth_ec_stats_get()
4205 stats->lbf_in_fifo_err = al_reg_read32(&adapter->ec_regs_base->stat.lbf_in_fifo_err); in al_eth_ec_stats_get()
4206 stats->rxf_out_rx_1_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_rx_1_pkt); in al_eth_ec_stats_get()
4207 stats->rxf_out_rx_2_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_rx_2_pkt); in al_eth_ec_stats_get()
4208 stats->rxf_out_drop_1_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_drop_1_pkt); in al_eth_ec_stats_get()
4209 stats->rxf_out_drop_2_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_drop_2_pkt); in al_eth_ec_stats_get()
4210 stats->rpe_1_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_1_in_rx_pkt); in al_eth_ec_stats_get()
4211 stats->rpe_1_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_1_out_rx_pkt); in al_eth_ec_stats_get()
4212 stats->rpe_2_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_2_in_rx_pkt); in al_eth_ec_stats_get()
4213 stats->rpe_2_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_2_out_rx_pkt); in al_eth_ec_stats_get()
4214 stats->rpe_3_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_3_in_rx_pkt); in al_eth_ec_stats_get()
4215 stats->rpe_3_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_3_out_rx_pkt); in al_eth_ec_stats_get()
4216 stats->tpe_in_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tpe_in_tx_pkt); in al_eth_ec_stats_get()
4217 stats->tpe_out_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tpe_out_tx_pkt); in al_eth_ec_stats_get()
4218 stats->tpm_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tpm_tx_pkt); in al_eth_ec_stats_get()
4219 stats->tfw_in_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tfw_in_tx_pkt); in al_eth_ec_stats_get()
4220 stats->tfw_out_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tfw_out_tx_pkt); in al_eth_ec_stats_get()
4221 stats->rfw_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_rx_pkt); in al_eth_ec_stats_get()
4222 stats->rfw_in_vlan_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_vlan_drop); in al_eth_ec_stats_get()
4223 stats->rfw_in_parse_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_parse_drop); in al_eth_ec_stats_get()
4224 stats->rfw_in_mc = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_mc); in al_eth_ec_stats_get()
4225 stats->rfw_in_bc = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_bc); in al_eth_ec_stats_get()
4226 stats->rfw_in_vlan_exist = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_vlan_exist); in al_eth_ec_stats_get()
4227 stats->rfw_in_vlan_nexist = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_vlan_nexist); in al_eth_ec_stats_get()
4228 stats->rfw_in_mac_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_mac_drop); in al_eth_ec_stats_get()
4229 stats->rfw_in_mac_ndet_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_mac_ndet_drop); in al_eth_ec_stats_get()
4230 stats->rfw_in_ctrl_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_ctrl_drop); in al_eth_ec_stats_get()
4231 stats->rfw_in_prot_i_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_prot_i_drop); in al_eth_ec_stats_get()
4232 stats->eee_in = al_reg_read32(&adapter->ec_regs_base->stat.eee_in); in al_eth_ec_stats_get()
4239 int al_eth_ec_stat_udma_get(struct al_hal_eth_adapter *adapter, uint8_t idx, struct al_eth_ec_stat_… in al_eth_ec_stat_udma_get() argument
4244 stats->rfw_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].rfw_out_rx_pkt); in al_eth_ec_stat_udma_get()
4245 stats->rfw_out_drop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].rfw_out_drop); in al_eth_ec_stat_udma_get()
4246 stats->msw_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_in_rx_pkt); in al_eth_ec_stat_udma_get()
4247 stats->msw_drop_q_full = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_drop_q_full); in al_eth_ec_stat_udma_get()
4248 stats->msw_drop_sop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_drop_sop); in al_eth_ec_stat_udma_get()
4249 stats->msw_drop_eop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_drop_eop); in al_eth_ec_stat_udma_get()
4250 stats->msw_wr_eop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_wr_eop); in al_eth_ec_stat_udma_get()
4251 stats->msw_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_out_rx_pkt); in al_eth_ec_stat_udma_get()
4252 stats->tso_no_tso_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_no_tso_pkt); in al_eth_ec_stat_udma_get()
4253 stats->tso_tso_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_tso_pkt); in al_eth_ec_stat_udma_get()
4254 stats->tso_seg_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_seg_pkt); in al_eth_ec_stat_udma_get()
4255 stats->tso_pad_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_pad_pkt); in al_eth_ec_stat_udma_get()
4256 stats->tpm_tx_spoof = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tpm_tx_spoof); in al_eth_ec_stat_udma_get()
4257 stats->tmi_in_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tmi_in_tx_pkt); in al_eth_ec_stat_udma_get()
4258 stats->tmi_out_to_mac = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tmi_out_to_mac); in al_eth_ec_stat_udma_get()
4259 stats->tmi_out_to_rx = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tmi_out_to_rx); in al_eth_ec_stat_udma_get()
4260 stats->tx_q0_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q0_bytes); in al_eth_ec_stat_udma_get()
4261 stats->tx_q1_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q1_bytes); in al_eth_ec_stat_udma_get()
4262 stats->tx_q2_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q2_bytes); in al_eth_ec_stat_udma_get()
4263 stats->tx_q3_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q3_bytes); in al_eth_ec_stat_udma_get()
4264 stats->tx_q0_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q0_pkts); in al_eth_ec_stat_udma_get()
4265 stats->tx_q1_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q1_pkts); in al_eth_ec_stat_udma_get()
4266 stats->tx_q2_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q2_pkts); in al_eth_ec_stat_udma_get()
4267 stats->tx_q3_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q3_pkts); in al_eth_ec_stat_udma_get()
4296 /* prevent adapter reset */ in al_eth_flr_rmn()
4697 struct al_hal_eth_adapter *adapter, in al_eth_wol_enable() argument
4706 al_reg_write32(&adapter->ec_regs_base->wol.magic_pswd_l, reg); in al_eth_wol_enable()
4709 al_reg_write32(&adapter->ec_regs_base->wol.magic_pswd_h, reg); in al_eth_wol_enable()
4716 al_reg_write32(&adapter->ec_regs_base->wol.ipv4_dip, reg); in al_eth_wol_enable()
4723 al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word0, reg); in al_eth_wol_enable()
4726 al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word1, reg); in al_eth_wol_enable()
4729 al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word2, reg); in al_eth_wol_enable()
4732 al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word3, reg); in al_eth_wol_enable()
4741 al_reg_write32(&adapter->ec_regs_base->wol.ethertype, reg); in al_eth_wol_enable()
4749 al_reg_write32(&adapter->ec_regs_base->wol.wol_en, reg); in al_eth_wol_enable()
4755 struct al_hal_eth_adapter *adapter) in al_eth_wol_disable() argument
4757 al_reg_write32(&adapter->ec_regs_base->wol.wol_en, 0); in al_eth_wol_disable()
4762 int al_eth_tx_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_tx_fwd_vid_table_set() argument
4770 al_reg_write32(&adapter->ec_regs_base->tfw.tx_vid_table_addr, idx); in al_eth_tx_fwd_vid_table_set()
4771 al_reg_write32(&adapter->ec_regs_base->tfw.tx_vid_table_data, val); in al_eth_tx_fwd_vid_table_set()
4775 int al_eth_tx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_tx_protocol_detect_table_entry_set() argument
4799 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_addr, idx); in al_eth_tx_protocol_detect_table_entry_set()
4800 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_ctrl, in al_eth_tx_protocol_detect_table_entry_set()
4803 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_mask_2, in al_eth_tx_protocol_detect_table_entry_set()
4806 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_mask_1, in al_eth_tx_protocol_detect_table_entry_set()
4809 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_data_2, in al_eth_tx_protocol_detect_table_entry_set()
4812 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_data_1, in al_eth_tx_protocol_detect_table_entry_set()
4818 int al_eth_tx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_tx_generic_crc_table_entry_set() argument
4863 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_addr, idx); in al_eth_tx_generic_crc_table_entry_set()
4864 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_gen, in al_eth_tx_generic_crc_table_entry_set()
4866 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_1, in al_eth_tx_generic_crc_table_entry_set()
4868 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_2, in al_eth_tx_generic_crc_table_entry_set()
4870 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_3, in al_eth_tx_generic_crc_table_entry_set()
4872 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_4, in al_eth_tx_generic_crc_table_entry_set()
4874 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_5, in al_eth_tx_generic_crc_table_entry_set()
4876 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_6, in al_eth_tx_generic_crc_table_entry_set()
4878 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_crc_init, in al_eth_tx_generic_crc_table_entry_set()
4880 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_res, in al_eth_tx_generic_crc_table_entry_set()
4882 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_alu_opcode, in al_eth_tx_generic_crc_table_entry_set()
4884 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_alu_opsel, in al_eth_tx_generic_crc_table_entry_set()
4886 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_alu_val, in al_eth_tx_generic_crc_table_entry_set()
4891 int al_eth_tx_crc_chksum_replace_cmd_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_tx_crc_chksum_replace_cmd_entry_set() argument
4902 al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address); in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4903 al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table, in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4909 al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address); in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4910 al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table, in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4916 al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address); in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4917 al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table, in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4923 al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address); in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4924 al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table, in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4930 int al_eth_rx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_rx_protocol_detect_table_entry_set() argument
4971 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_addr, idx); in al_eth_rx_protocol_detect_table_entry_set()
4972 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_ctrl, in al_eth_rx_protocol_detect_table_entry_set()
4974 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_mask_2, in al_eth_rx_protocol_detect_table_entry_set()
4976 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_mask_1, in al_eth_rx_protocol_detect_table_entry_set()
4978 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_data_2, in al_eth_rx_protocol_detect_table_entry_set()
4980 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_data_1, in al_eth_rx_protocol_detect_table_entry_set()
4985 int al_eth_rx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, in al_eth_rx_generic_crc_table_entry_set() argument
5029 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_addr, idx); in al_eth_rx_generic_crc_table_entry_set()
5030 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_gen, in al_eth_rx_generic_crc_table_entry_set()
5032 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_1, in al_eth_rx_generic_crc_table_entry_set()
5034 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_2, in al_eth_rx_generic_crc_table_entry_set()
5036 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_3, in al_eth_rx_generic_crc_table_entry_set()
5038 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_4, in al_eth_rx_generic_crc_table_entry_set()
5040 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_5, in al_eth_rx_generic_crc_table_entry_set()
5042 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_6, in al_eth_rx_generic_crc_table_entry_set()
5044 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_crc_init, in al_eth_rx_generic_crc_table_entry_set()
5046 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_res, in al_eth_rx_generic_crc_table_entry_set()
5048 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_alu_opcode, in al_eth_rx_generic_crc_table_entry_set()
5050 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_alu_opsel, in al_eth_rx_generic_crc_table_entry_set()
5052 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_alu_val, in al_eth_rx_generic_crc_table_entry_set()
5578 int al_eth_tx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter) in al_eth_tx_protocol_detect_table_init() argument
5581 al_assert((adapter->rev_id > AL_ETH_REV_ID_2)); in al_eth_tx_protocol_detect_table_init()
5584 al_eth_tx_protocol_detect_table_entry_set(adapter, idx, in al_eth_tx_protocol_detect_table_init()
5590 int al_eth_tx_generic_crc_table_init(struct al_hal_eth_adapter *adapter) in al_eth_tx_generic_crc_table_init() argument
5593 al_assert((adapter->rev_id > AL_ETH_REV_ID_2)); in al_eth_tx_generic_crc_table_init()
5595 al_dbg("eth [%s]: enable tx_generic_crc\n", adapter->name); in al_eth_tx_generic_crc_table_init()
5596 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_legacy, 0x0); in al_eth_tx_generic_crc_table_init()
5597 al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace, 0x0); in al_eth_tx_generic_crc_table_init()
5599 al_eth_tx_generic_crc_table_entry_set(adapter, idx, in al_eth_tx_generic_crc_table_init()
5605 int al_eth_tx_crc_chksum_replace_cmd_init(struct al_hal_eth_adapter *adapter) in al_eth_tx_crc_chksum_replace_cmd_init() argument
5608 al_assert((adapter->rev_id > AL_ETH_REV_ID_2)); in al_eth_tx_crc_chksum_replace_cmd_init()
5611 al_eth_tx_crc_chksum_replace_cmd_entry_set(adapter, idx, in al_eth_tx_crc_chksum_replace_cmd_init()
5617 int al_eth_rx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter) in al_eth_rx_protocol_detect_table_init() argument
5620 al_assert((adapter->rev_id > AL_ETH_REV_ID_2)); in al_eth_rx_protocol_detect_table_init()
5621 al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p1, in al_eth_rx_protocol_detect_table_init()
5623 al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p2, in al_eth_rx_protocol_detect_table_init()
5625 al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p3, in al_eth_rx_protocol_detect_table_init()
5627 al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p4, in al_eth_rx_protocol_detect_table_init()
5629 al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p5, in al_eth_rx_protocol_detect_table_init()
5631 al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p6, in al_eth_rx_protocol_detect_table_init()
5633 al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p7, in al_eth_rx_protocol_detect_table_init()
5635 al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p8, in al_eth_rx_protocol_detect_table_init()
5639 al_eth_rx_protocol_detect_table_entry_set(adapter, idx, in al_eth_rx_protocol_detect_table_init()
5644 int al_eth_rx_generic_crc_table_init(struct al_hal_eth_adapter *adapter) in al_eth_rx_generic_crc_table_init() argument
5649 al_assert((adapter->rev_id > AL_ETH_REV_ID_2)); in al_eth_rx_generic_crc_table_init()
5651 al_dbg("eth [%s]: enable rx_generic_crc\n", adapter->name); in al_eth_rx_generic_crc_table_init()
5652 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_legacy, 0x0); in al_eth_rx_generic_crc_table_init()
5655 al_eth_rx_generic_crc_table_entry_set(adapter, idx, in al_eth_rx_generic_crc_table_init()
5662 al_reg_write32_masked(&adapter->ec_regs_base->gen_v3.rx_comp_desc, in al_eth_rx_generic_crc_table_init()