Lines Matching +full:eee +full:- +full:pcs
1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
153 al_bool eee; /**< Energy Efficient Ethernet */ member
194 * will be set according to inner packet when packet is tunneled, for non-tunneled
327 uint8_t l4_header_len; /**< in words(32-bits) */
342 * Target-ID to be assigned to the packet descriptors
343 * Requires Target-ID in descriptor to be enabled for the specific UDMA
356 /* Packet Rx flags - word 3 in Rx completion descriptor */
386 * Target-ID to be assigned to the packet descriptors
387 * Requires Target-ID in descriptor to be enabled for the specific UDMA
464 * - initialize the adapter data structure
465 * - initialize the Tx and Rx UDMA
466 * - enable the Tx and Rx UDMA, the rings will be still disabled at this point.
527 * @return -EPERM (not implemented yet).
537 * @return -EPERM (not implemented yet).
577 * @param tx_reset assert and de-assert reset for tx lanes
578 * @param rx_reset assert and de-assert reset for rx lanes
730 al_udma_q_handle_get(&adapter->tx_udma, qid, &udma_q); in al_eth_tx_available_get()
918 * bits[1:0] - input selection: selects the input for the thash (2/4 tuple, inner/outer)
919 * bit[2] - selects whether to use thash output, or default values for the queue and udma
1370 uint32_t tx_eee_timer; /**< time in cycles the interface delays prior to entering eee state */
1371 uint32_t min_interval; /**< minimum interval in cycles between two eee states */
1372 uint32_t stop_cnt; /**< time in cycles to stop Tx mac i/f after getting out of eee state */
1377 * configure EEE mode
1379 * @param params pointer to the eee input parameters.
1386 * get EEE configuration
1388 * @param params pointer to the eee output parameters.
1397 * This is a generic time-stamp mechanism that can be used as generic to
1398 * time-stamp every received or transmit packet it can also support IEEE 1588v2
1400 * In addition to time-stamp, an internal system time is maintained. For
1403 * to the rest of the ports - that is outside the scope of the Ethernet
1404 * Controller - please refer to Annapurna Labs Alpine Hardware Wiki
1424 * This is the size of the on-chip array that keeps the time-stamp of the
1443 * returns -EAGAIN.
1447 * @return -EAGAIN if the sample was not updated yet. 0 when the sample
1463 * The HW maintains 50 bits for the sub-seconds portion in femto resolution,
1465 * sub-nanoseconds accuracy, which is not needed.
1707 … FIFO Overflow, CRC, Payload Length, Jabber and Oversized, Alignment or PHY/PCS error indication */
1857 /* EEE, number of times the system went into EEE state */
1875 /* Multi-stream write, number of Rx packets */
1877 /* Multi-stream write, number of dropped packets at SOP, Q full indication */
1879 /* Multi-stream write, number of dropped packets at SOP */
1881 /* Multi-stream write, number of dropped packets at EOP, */
1884 …/* Multi-stream write, number of packets written to the stream FIFO with EOP and without packet lo…
1886 /* Multi-stream write, number of packets read from the FIFO into the stream */
2041 al_bool autoneg_enable; /**< enable Auto-Negotiation */
2042 al_bool kr_lt_enable; /**< enable KR Link-Training */
2047 enum al_eth_board_auto_neg_mode an_mode; /**< auto-negotiation mode (in-band / out-of-band) */
2052 al_bool force_1000_base_x; /**< set mac to 1000 base-x mode (instead sgmii) */
2093 * Wake-On-Lan (WoL)
2095 * The following few functions configure the Wake-On-Lan packet detection
2099 * external 1000Base-T transceiver to set WoL mode.
2101 * These APIs do not set the system-wide power-state, nor responsible on the
2196 * the udmas, through the Rx path (udma_mask is one-hot representation)
2439 /* *INDENT-ON* */