Lines Matching +full:0 +full:x38000
44 #define AL_PCI_COMMAND 0x04 /* 16 bits */
45 #define AL_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
46 #define AL_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
47 #define AL_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
49 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
51 #define AL_PCI_BASE_ADDRESS_SPACE_IO 0x01
52 #define AL_PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
53 #define AL_PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
54 #define AL_PCI_BASE_ADDRESS_DEVICE_ID 0x0c
56 #define AL_PCI_BASE_ADDRESS_0 0x10
57 #define AL_PCI_BASE_ADDRESS_0_HI 0x14
58 #define AL_PCI_BASE_ADDRESS_2 0x18
59 #define AL_PCI_BASE_ADDRESS_2_HI 0x1c
60 #define AL_PCI_BASE_ADDRESS_4 0x20
61 #define AL_PCI_BASE_ADDRESS_4_HI 0x24
63 #define AL_PCI_EXP_ROM_BASE_ADDRESS 0x30
65 #define AL_PCI_AXI_CFG_AND_CTR_0 0x110
66 #define AL_PCI_AXI_CFG_AND_CTR_1 0x130
67 #define AL_PCI_AXI_CFG_AND_CTR_2 0x150
68 #define AL_PCI_AXI_CFG_AND_CTR_3 0x170
70 #define AL_PCI_APP_CONTROL 0x220
72 #define AL_PCI_SRIOV_TOTAL_AND_INITIAL_VFS 0x30c
74 #define AL_PCI_VF_BASE_ADDRESS_0 0x324
77 #define AL_PCI_EXP_CAP_BASE 0x40
79 #define AL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
80 #define AL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
81 #define AL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
82 #define AL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
83 #define AL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
84 #define AL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
85 #define AL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
86 #define AL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
87 #define AL_PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
88 #define AL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
89 #define AL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
90 #define AL_PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
92 #define AL_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
93 #define AL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
94 #define AL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
95 #define AL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
96 #define AL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
97 #define AL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
98 #define AL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
99 #define AL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
100 #define AL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
101 #define AL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
102 #define AL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
103 #define AL_PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
104 #define AL_PCI_EXP_DEVSTA 0xA /* Device Status */
105 #define AL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
106 #define AL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
107 #define AL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
108 #define AL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
109 #define AL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
110 #define AL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
111 #define AL_PCI_EXP_LNKCAP 0xC /* Link Capabilities */
112 #define AL_PCI_EXP_LNKCAP_SLS 0xf /* Supported Link Speeds */
113 #define AL_PCI_EXP_LNKCAP_SLS_2_5GB 0x1 /* LNKCAP2 SLS Vector bit 0 (2.5GT/s) */
114 #define AL_PCI_EXP_LNKCAP_SLS_5_0GB 0x2 /* LNKCAP2 SLS Vector bit 1 (5.0GT/s) */
115 #define AL_PCI_EXP_LNKCAP_MLW 0x3f0 /* Maximum Link Width */
116 #define AL_PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
117 #define AL_PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
118 #define AL_PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
119 #define AL_PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */
120 #define AL_PCI_EXP_LNKCAP_SDERC 0x80000 /* Surprise Down Error Reporting Capable */
121 #define AL_PCI_EXP_LNKCAP_DLLLARC 0x100000 /* Data Link Layer Link Active Reporting Capable */
122 #define AL_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
123 #define AL_PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
125 #define AL_PCI_EXP_LNKCTL 0x10 /* Link Control */
126 #define AL_PCI_EXP_LNKCTL_LNK_DIS 0x4 /* Link Disable Status */
127 #define AL_PCI_EXP_LNKCTL_LNK_RTRN 0x5 /* Link Retrain Status */
129 #define AL_PCI_EXP_LNKSTA 0x12 /* Link Status */
130 #define AL_PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
131 #define AL_PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
132 #define AL_PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
133 #define AL_PCI_EXP_LNKSTA_CLS_8_0GB 0x03 /* Current Link Speed 8.0GT/s */
134 #define AL_PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */
136 #define AL_PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
137 #define AL_PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
138 #define AL_PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
139 #define AL_PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
140 #define AL_PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
142 #define AL_PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */
144 #define AL_PCI_MSIX_MSGCTRL 0 /* MSIX message control reg */
145 #define AL_PCI_MSIX_MSGCTRL_TBL_SIZE 0x7ff /* MSIX table size */
147 #define AL_PCI_MSIX_MSGCTRL_EN 0x80000000 /* MSIX enable */
148 #define AL_PCI_MSIX_MSGCTRL_MASK 0x40000000 /* MSIX mask */
150 #define AL_PCI_MSIX_TABLE 0x4 /* MSIX table offset and bar reg */
151 #define AL_PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* MSIX table offset */
152 #define AL_PCI_MSIX_TABLE_BAR 0x7 /* MSIX table BAR */
154 #define AL_PCI_MSIX_PBA 0x8 /* MSIX pba offset and bar reg */
155 #define AL_PCI_MSIX_PBA_OFFSET 0xfffffff8 /* MSIX pba offset */
156 #define AL_PCI_MSIX_PBA_BAR 0x7 /* MSIX pba BAR */
159 /* Adapter power management register 0 */
160 #define AL_ADAPTER_PM_0 0x80
161 #define AL_ADAPTER_PM_0_PM_NEXT_CAP_MASK 0xff00
163 #define AL_ADAPTER_PM_0_PM_NEXT_CAP_VAL_MSIX 0x90
166 #define AL_ADAPTER_PM_1 0x84
167 #define AL_ADAPTER_PM_1_PME_EN 0x100 /* PM enable */
168 #define AL_ADAPTER_PM_1_PWR_STATE_MASK 0x3 /* PM state mask */
169 #define AL_ADAPTER_PM_1_PWR_STATE_D3 0x3 /* PM D3 state */
172 #define AL_ADAPTER_SMCC 0x110
173 #define AL_ADAPTER_SMCC_CONF_2 0x114
176 #define AL_ADAPTER_INT_CAUSE 0x1B0
178 #define AL_ADAPTER_INT_CAUSE_RD_ERR AL_BIT(0)
182 #define AL_ADAPTER_AXI_MSTR_WR_ERR_ATTR 0x1B4
183 #define AL_ADAPTER_AXI_MSTR_RD_ERR_ATTR 0x1B8
185 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_STAT_MASK AL_FIELD_MASK(1, 0)
186 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_STAT_SHIFT 0
196 #define AL_ADAPTER_INT_CAUSE_MASK 0x1BC
198 #define AL_ADAPTER_INT_CAUSE_MASK_RD_ERR AL_BIT(0)
201 #define AL_ADAPTER_AXI_MSTR_WR_ERR_LO_LATCH 0x1C0
204 #define AL_ADAPTER_AXI_MSTR_WR_ERR_HI_LATCH 0x1C4
207 #define AL_ADAPTER_AXI_MSTR_RD_ERR_LO_LATCH 0x1C8
210 #define AL_ADAPTER_AXI_MSTR_RD_ERR_HI_LATCH 0x1CC
213 #define AL_ADAPTER_AXI_MSTR_TO 0x1D0
216 #define AL_ADAPTER_AXI_MSTR_TO_RD_MASK AL_FIELD_MASK(15, 0)
217 #define AL_ADAPTER_AXI_MSTR_TO_RD_SHIFT 0
223 /* Control 0 */
224 #define AL_ADAPTER_GENERIC_CONTROL_0 0x1E0
226 #define AL_ADAPTER_GENERIC_CONTROL_2 0x1E8
228 #define AL_ADAPTER_GENERIC_CONTROL_3 0x1EC
230 #define AL_ADAPTER_GENERIC_CONTROL_9 0x218
232 #define AL_ADAPTER_GENERIC_CONTROL_10 0x21C
234 #define AL_ADAPTER_GENERIC_CONTROL_11 0x220
236 #define AL_ADAPTER_GENERIC_CONTROL_12 0x224
238 #define AL_ADAPTER_GENERIC_CONTROL_13 0x228
240 #define AL_ADAPTER_GENERIC_CONTROL_14 0x22C
242 #define AL_ADAPTER_GENERIC_CONTROL_15 0x230
244 #define AL_ADAPTER_GENERIC_CONTROL_16 0x234
246 #define AL_ADAPTER_GENERIC_CONTROL_17 0x238
248 #define AL_ADAPTER_GENERIC_CONTROL_18 0x23C
250 #define AL_ADAPTER_GENERIC_CONTROL_19 0x240
253 #define AL_ADAPTER_GENERIC_CONTROL_0_CLK_GATE_EN 0x01
255 #define AL_ADAPTER_GENERIC_CONTROL_0_ADAPTER_DIS 0x40
266 /* AXUSER selection and value per bit (1 = address, 0 = register) */
268 #define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_VAL_MASK AL_FIELD_MASK(15, 0)
269 #define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_VAL_SHIFT 0
273 #define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_VAL_MASK AL_FIELD_MASK(15, 0)
274 #define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_VAL_SHIFT 0
278 #define AL_ADPTR_GEN_CTL_14_SATA_MSIX_TGTID_SEL AL_BIT(0)
290 #define AL_ADPTR_GEN_CTL_15_SATA_VM_AWDDR_HI AL_FIELD_MASK(31, 0)
292 #define AL_ADPTR_GEN_CTL_16_SATA_VM_ARDDR_HI AL_FIELD_MASK(31, 0)
298 #define AL_ADPTR_GEN_CTL_19_READ_ROB_EN AL_BIT(0)