Lines Matching +full:0 +full:x0007ffff
59 /* [0x0] Completion write master configuration */
61 /* [0x4] Completion write master configuration */
63 /* [0x8] Data read master configuration */
65 /* [0xc] Data read master configuration */
67 /* [0x10] Descriptor read master configuration */
69 /* [0x14] Descriptor read master configuration */
71 /* [0x18] Data read master configuration */
73 /* [0x1c] Descriptors read master configuration */
75 /* [0x20] Descriptors write master configuration (completion) */
77 /* [0x24] AXI outstanding configuration */
83 * [0x0] DMA state.
90 /* [0x4] CPU request to change DMA state */
94 * [0xc] M2S DMA error log mask.
98 * 0 - Log is enabled.
104 * [0x14] DMA header log.
109 * [0x18] DMA header log.
114 * [0x1c] DMA header log.
119 * [0x20] DMA header log.
123 /* [0x24] DMA clear error log */
125 /* [0x28] M2S data FIFO status */
127 /* [0x2c] M2S header FIFO status */
129 /* [0x30] M2S unack FIFO status */
131 /* [0x34] Select queue for debug */
134 * [0x38] M2S prefetch FIFO status.
139 * [0x3c] M2S completion FIFO status.
144 * [0x40] M2S rate limit status.
149 * [0x44] M2S DWRR scheduler status.
153 /* [0x48] M2S state machine and FIFO clear control */
155 /* [0x4c] Misc Check enable */
157 /* [0x50] M2S FIFO enable control, internal */
159 /* [0x54] M2S packet length configuration */
161 /* [0x58] Stream interface configuration */
166 /* [0x0] M2S descriptor prefetch configuration */
168 /* [0x4] M2S descriptor prefetch configuration */
170 /* [0x8] M2S descriptor prefetch configuration */
173 /* [0x10] Data burst read configuration */
178 /* [0x0] Tx DMA DWRR scheduler configuration */
180 /* [0x4] Token bucket rate limit control */
185 /* [0x0] Token bucket rate limit configuration */
188 * [0x4] Token bucket rate limit control.
193 * [0x8] Token bucket rate limit control.
201 /* [0x0] Token bucket configuration */
203 /* [0x4] Token bucket rate limit configuration */
205 /* [0x8] Token bucket rate limit configuration */
207 /* [0xc] Token bucket rate limit configuration */
209 /* [0x10] Token bucket rate limit configuration */
212 * [0x14] Mask the different types of rate limiter.
213 * 0 - Rate limit is active.
224 /* [0x0] Completion controller configuration */
226 /* [0x4] Completion controller coalescing configuration */
228 /* [0x8] Completion controller application acknowledge configuration */
233 /* [0x0] Statistics counters configuration */
235 /* [0x4] Counting number of descriptors with First-bit set. */
238 * [0x8] Counting the net length of the data buffers [64-bit]
243 * [0xc] Counting the net length of the data buffers [64-bit],
248 /* [0x10] Total number of descriptors read from the host memory */
250 /* [0x14] Number of packets read from the unack FIFO */
252 /* [0x18] Number of descriptors written into the completion ring */
255 * [0x1c] Number of acknowledged packets.
263 * [0x0] M2S Feature register.
267 /* [0x4] Reserved M2S feature register */
270 * [0x8] M2S Feature register.
275 * [0xc] M2S Feature register.
280 * [0x10] M2S Feature register.
288 /* [0x20] M2S descriptor ring configuration */
290 /* [0x24] M2S descriptor ring status and information */
292 /* [0x28] TX Descriptor Ring Base Pointer [31:4] */
294 /* [0x2c] TX Descriptor Ring Base Pointer [63:32] */
297 * [0x30] TX Descriptor Ring Length[23:2]
300 /* [0x34] TX Descriptor Ring Head Pointer */
302 /* [0x38] Tx Descriptor Tail Pointer increment */
304 /* [0x3c] Tx Descriptor Tail Pointer */
306 /* [0x40] TX Descriptor Current Pointer */
308 /* [0x44] Tx Completion Ring Base Pointer [31:4] */
310 /* [0x48] TX Completion Ring Base Pointer [63:32] */
312 /* [0x4c] TX Completion Ring Head Pointer */
315 * [0x50] Tx Completion Ring Head Pointer internal (Before the
320 /* [0x60] Rate limit configuration */
323 /* [0x80] DWRR scheduler configuration */
325 /* [0x84] DWRR scheduler configuration */
327 /* [0x88] DWRR scheduler configuration */
329 /* [0x8c] DWRR scheduler software control */
332 /* [0xa0] Completion controller configuration */
335 /* [0xb0] SW control */
338 /* [0xc0] Number of M2S Tx packets after the scheduler */
345 struct udma_axi_m2s axi_m2s; /* [0x100] */
346 struct udma_m2s m2s; /* [0x200] */
347 struct udma_m2s_rd m2s_rd; /* [0x300] */
348 struct udma_m2s_dwrr m2s_dwrr; /* [0x340] */
349 struct udma_m2s_rate_limiter m2s_rate_limiter; /* [0x380] */
350 struct udma_m2s_stream_rate_limiter m2s_stream_rate_limiter; /* [0x3c0] */
351 struct udma_m2s_comp m2s_comp; /* [0x400] */
352 struct udma_m2s_stat m2s_stat; /* [0x500] */
353 struct udma_m2s_feature m2s_feature; /* [0x600] */
355 struct udma_m2s_q m2s_q[4]; /* [0x1000] */
366 #define UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK 0x000000FF
367 #define UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_SHIFT 0
369 #define UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_MASK 0x000F0000
372 #define UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_MASK 0x03000000
377 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK 0x000FFFFF
378 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_SHIFT 0
380 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_MASK 0x00700000
386 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_MASK 0x07000000
389 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_MASK 0x70000000
394 #define UDMA_AXI_M2S_DATA_RD_CFG_1_ARID_MASK 0x000000FF
395 #define UDMA_AXI_M2S_DATA_RD_CFG_1_ARID_SHIFT 0
397 #define UDMA_AXI_M2S_DATA_RD_CFG_1_ARCACHE_MASK 0x000F0000
400 #define UDMA_AXI_M2S_DATA_RD_CFG_1_ARBURST_MASK 0x03000000
405 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARUSER_MASK 0x000FFFFF
406 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARUSER_SHIFT 0
408 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARSIZE_MASK 0x00700000
414 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARQOS_MASK 0x07000000
417 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARPROT_MASK 0x70000000
422 #define UDMA_AXI_M2S_DESC_RD_CFG_1_ARID_MASK 0x000000FF
423 #define UDMA_AXI_M2S_DESC_RD_CFG_1_ARID_SHIFT 0
425 #define UDMA_AXI_M2S_DESC_RD_CFG_1_ARCACHE_MASK 0x000F0000
428 #define UDMA_AXI_M2S_DESC_RD_CFG_1_ARBURST_MASK 0x03000000
433 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARUSER_MASK 0x000FFFFF
434 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARUSER_SHIFT 0
436 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARSIZE_MASK 0x00700000
442 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARQOS_MASK 0x07000000
445 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARPROT_MASK 0x70000000
453 #define UDMA_AXI_M2S_DATA_RD_CFG_MAX_AXI_BEATS_MASK 0x000000FF
454 #define UDMA_AXI_M2S_DATA_RD_CFG_MAX_AXI_BEATS_SHIFT 0
468 #define UDMA_AXI_M2S_DESC_RD_CFG_3_MAX_AXI_BEATS_MASK 0x000000FF
469 #define UDMA_AXI_M2S_DESC_RD_CFG_3_MAX_AXI_BEATS_SHIFT 0
481 #define UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK 0x000000FF
482 #define UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_SHIFT 0
490 #define UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK 0x00FF0000
495 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_MASK 0x0000003F
496 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_SHIFT 0
500 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_MASK 0x00003F00
505 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_MASK 0x003F0000
511 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_MASK 0xFF000000
516 #define UDMA_M2S_STATE_COMP_CTRL_MASK 0x00000003
517 #define UDMA_M2S_STATE_COMP_CTRL_SHIFT 0
519 #define UDMA_M2S_STATE_STREAM_IF_MASK 0x00000030
522 #define UDMA_M2S_STATE_DATA_RD_CTRL_MASK 0x00000300
525 #define UDMA_M2S_STATE_DESC_PREF_MASK 0x00003000
530 #define UDMA_M2S_CHANGE_STATE_NORMAL (1 << 0)
545 #define UDMA_M2S_ERR_LOG_MASK_COMP_PKT_MISMATCH (1 << 0)
583 #define UDMA_M2S_ERR_LOG_MASK_INTERNAL_MASK 0xFFF80000
588 #define UDMA_M2S_CLEAR_ERR_LOG_CLEAR (1 << 0)
592 #define UDMA_M2S_DATA_FIFO_STATUS_USED_MASK 0x0000FFFF
593 #define UDMA_M2S_DATA_FIFO_STATUS_USED_SHIFT 0
601 #define UDMA_M2S_HEADER_FIFO_STATUS_USED_MASK 0x0000FFFF
602 #define UDMA_M2S_HEADER_FIFO_STATUS_USED_SHIFT 0
610 #define UDMA_M2S_UNACK_FIFO_STATUS_USED_MASK 0x0000FFFF
611 #define UDMA_M2S_UNACK_FIFO_STATUS_USED_SHIFT 0
619 #define UDMA_M2S_INDIRECT_CTRL_Q_NUM_MASK 0x00000FFF
620 #define UDMA_M2S_INDIRECT_CTRL_Q_NUM_SHIFT 0
624 #define UDMA_M2S_SEL_PREF_FIFO_STATUS_USED_MASK 0x0000FFFF
625 #define UDMA_M2S_SEL_PREF_FIFO_STATUS_USED_SHIFT 0
633 #define UDMA_M2S_SEL_COMP_FIFO_STATUS_USED_MASK 0x0000FFFF
634 #define UDMA_M2S_SEL_COMP_FIFO_STATUS_USED_SHIFT 0
642 #define UDMA_M2S_SEL_RATE_LIMIT_STATUS_TOKEN_CNT_MASK 0x00FFFFFF
643 #define UDMA_M2S_SEL_RATE_LIMIT_STATUS_TOKEN_CNT_SHIFT 0
647 #define UDMA_M2S_SEL_DWRR_STATUS_DEFICIT_CNT_MASK 0x00FFFFFF
648 #define UDMA_M2S_SEL_DWRR_STATUS_DEFICIT_CNT_SHIFT 0
652 #define UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_MASK 0x000FFFFF
653 #define UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_SHIFT 0
656 * 0 - length 0x0000 = 0
657 * 1 - length 0x0000 = 64k
666 #define UDMA_M2S_STREAM_CFG_DISABLE (1 << 0)
669 * 0 - Cut through
674 #define UDMA_M2S_STREAM_CFG_RD_TH_MASK 0x0003FF00
679 #define UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK 0x000000FF
680 #define UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_SHIFT 0
684 #define UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK 0x0000001F
685 #define UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_SHIFT 0
688 * 0 -Standard arbitration based on queue QoS
699 #define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK 0x0000000F
700 #define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_SHIFT 0
705 #define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK 0x000000F0
712 #define UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK 0x0000FF00
721 #define UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK 0x000003FF
722 #define UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_SHIFT 0
727 #define UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_MASK 0x00FF0000
733 * If this bit is 0, queues with same QoS will be served with RR scheduler.
735 #define UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR (1 << 0)
738 * 0 - Byte mode
749 #define UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_MASK 0x00000300
756 #define UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_MASK 0x000F0000
765 #define UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_MASK 0x00FFFFFF
766 #define UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_SHIFT 0
770 #define UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_MASK 0x0000FFFF
771 #define UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_SHIFT 0
774 * 0 - Byte mode
781 #define UDMA_M2S_RATE_LIMITER_CTRL_CYCLE_CNT_RST (1 << 0)
789 #define UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_MASK 0x00FFFFFF
790 #define UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_SHIFT 0
794 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_MASK 0x00FFFFFF
795 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_SHIFT 0
803 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_MASK 0x0000FFFF
804 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_SHIFT 0
808 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK 0x0007FFFF
809 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_SHIFT 0
813 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK 0x0007FFFF
814 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_SHIFT 0
818 #define UDMA_M2S_STREAM_RATE_LIMITER_SW_CTRL_RST_TOKEN_CNT (1 << 0)
822 #define UDMA_M2S_STREAM_RATE_LIMITER_MASK_EXTERNAL_RATE_LIMITER (1 << 0)
833 #define UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_MASK 0x000000FF
834 #define UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_SHIFT 0
839 #define UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_MASK 0x0001FF00
850 #define UDMA_M2S_COMP_CFG_1C_Q_FREE_MIN_MASK 0xF0000000
858 #define UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_MASK 0x00FFFFFF
859 #define UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_SHIFT 0
863 #define UDMA_M2S_STAT_CFG_ST_USE_EXTRA_LEN (1 << 0)
870 #define UDMA_M2S_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_MASK 0x000000FF
871 #define UDMA_M2S_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_SHIFT 0
879 #define UDMA_M2S_FEATURE_REG_3_DATA_FIFO_DEPTH_MASK 0x000003FF
880 #define UDMA_M2S_FEATURE_REG_3_DATA_FIFO_DEPTH_SHIFT 0
885 #define UDMA_M2S_FEATURE_REG_3_DATA_RD_MAX_PKT_LIMIT_MASK 0x00FF0000
893 #define UDMA_M2S_FEATURE_REG_4_COMP_FIFO_DEPTH_MASK 0x000000FF
894 #define UDMA_M2S_FEATURE_REG_4_COMP_FIFO_DEPTH_SHIFT 0
896 #define UDMA_M2S_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_MASK 0x0001FF00
901 #define UDMA_M2S_FEATURE_REG_5_MAX_DATA_RD_OSTAND_MASK 0x0000003F
902 #define UDMA_M2S_FEATURE_REG_5_MAX_DATA_RD_OSTAND_SHIFT 0
904 #define UDMA_M2S_FEATURE_REG_5_MAX_DESC_RD_OSTAND_MASK 0x00003F00
910 #define UDMA_M2S_FEATURE_REG_5_MAX_COMP_REQ_MASK 0x003F0000
916 #define UDMA_M2S_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_MASK 0xFF000000
924 #define UDMA_M2S_Q_CFG_PKT_LEN_OFFSET_MASK 0x0000FFFF
925 #define UDMA_M2S_Q_CFG_PKT_LEN_OFFSET_SHIFT 0
939 #define UDMA_M2S_Q_CFG_AXI_AWCACHE_COMP_MASK 0x0F000000
946 #define UDMA_M2S_Q_CFG_AXI_QOS_MASK 0x70000000
951 #define UDMA_M2S_Q_STATUS_Q_USED_MASK 0x01FFFFFF
952 #define UDMA_M2S_Q_STATUS_Q_USED_SHIFT 0
955 * 0 – prefetch operation is stopped
961 * 0 – queue is not active and not participating in scheduling
975 * [3:0] - 0 - 16B alignment is enforced
976 * ([11:4] should be 0 for 4KB alignment)
978 #define UDMA_M2S_Q_TDRBP_LOW_ADDR_MASK 0xFFFFFFF0
987 #define UDMA_M2S_Q_TDRL_OFFSET_MASK 0x00FFFFFF
988 #define UDMA_M2S_Q_TDRL_OFFSET_SHIFT 0
998 #define UDMA_M2S_Q_TDRHP_OFFSET_MASK 0x00FFFFFF
999 #define UDMA_M2S_Q_TDRHP_OFFSET_SHIFT 0
1001 #define UDMA_M2S_Q_TDRHP_RING_ID_MASK 0xC0000000
1006 #define UDMA_M2S_Q_TDRTP_INC_VAL_MASK 0x00FFFFFF
1007 #define UDMA_M2S_Q_TDRTP_INC_VAL_SHIFT 0
1014 #define UDMA_M2S_Q_TDRTP_OFFSET_MASK 0x00FFFFFF
1015 #define UDMA_M2S_Q_TDRTP_OFFSET_SHIFT 0
1017 #define UDMA_M2S_Q_TDRTP_RING_ID_MASK 0xC0000000
1025 #define UDMA_M2S_Q_TDCP_OFFSET_MASK 0x00FFFFFF
1026 #define UDMA_M2S_Q_TDCP_OFFSET_SHIFT 0
1028 #define UDMA_M2S_Q_TDCP_RING_ID_MASK 0xC0000000
1033 * [3:0] - 0 - 16B alignment is enforced
1034 * ([11:4] should be 0 for 4KB alignment)
1039 #define UDMA_M2S_Q_TCRBP_LOW_ADDR_MASK 0xFFFFFFF0
1048 #define UDMA_M2S_Q_TCRHP_OFFSET_MASK 0x00FFFFFF
1049 #define UDMA_M2S_Q_TCRHP_OFFSET_SHIFT 0
1051 #define UDMA_M2S_Q_TCRHP_RING_ID_MASK 0xC0000000
1060 #define UDMA_M2S_Q_TCRHP_INTERNAL_OFFSET_MASK 0x00FFFFFF
1061 #define UDMA_M2S_Q_TCRHP_INTERNAL_OFFSET_SHIFT 0
1063 #define UDMA_M2S_Q_TCRHP_INTERNAL_RING_ID_MASK 0xC0000000
1068 #define UDMA_M2S_Q_RATE_LIMIT_CFG_1_MAX_BURST_SIZE_MASK 0x00FFFFFF
1069 #define UDMA_M2S_Q_RATE_LIMIT_CFG_1_MAX_BURST_SIZE_SHIFT 0
1077 #define UDMA_M2S_Q_RATE_LIMIT_CFG_CYCLE_LONG_CYCLE_SIZE_MASK 0x0000FFFF
1078 #define UDMA_M2S_Q_RATE_LIMIT_CFG_CYCLE_LONG_CYCLE_SIZE_SHIFT 0
1082 #define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK 0x0007FFFF
1083 #define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_1_LONG_CYCLE_SHIFT 0
1087 #define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK 0x0007FFFF
1088 #define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_2_SHORT_CYCLE_SHIFT 0
1092 #define UDMA_M2S_Q_RATE_LIMIT_SW_CTRL_RST_TOKEN_CNT (1 << 0)
1096 #define UDMA_M2S_Q_RATE_LIMIT_MASK_EXTERNAL_RATE_LIMITER (1 << 0)
1109 #define UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_MASK 0x00FFFFFF
1110 #define UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_SHIFT 0
1122 #define UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK 0x000000FF
1123 #define UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_SHIFT 0
1127 #define UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK 0x000000FF
1128 #define UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_SHIFT 0
1132 #define UDMA_M2S_Q_DWRR_SW_CTRL_RST_CNT (1 << 0)
1136 #define UDMA_M2S_Q_COMP_CFG_EN_COMP_RING_UPDATE (1 << 0)
1145 #define UDMA_M2S_Q_SW_CTRL_RST_DMB (1 << 0)