Lines Matching +full:0 +full:x0000000f
58 /* [0x0] Reserved register for the interrupt controller */
60 /* [0x4] Revision register */
62 /* [0x8] Reserved for future use */
64 /* [0xc] Reserved for future use */
66 /* [0x10] Reserved for future use */
68 /* [0x14] Reserved for future use */
70 /* [0x18] General timer configuration */
76 * [0x0] Mailbox interrupt generator.
80 /* [0x4] Mailbox message data out */
82 /* [0x8] Mailbox message data in */
87 /* [0x0] Configuration of the AXI masters */
89 /* [0x4] Configuration of the AXI masters */
91 /* [0x8] Configuration of the AXI masters. Endianess configuration */
96 /* [0x0] Timing configuration */
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
122 /* [0x0] TX VMPR control */
124 /* [0x4] TX VMPR Address High Regsiter */
126 /* [0x8] TX queue Target-ID values */
128 /* [0xc] TX queue Target-ID values */
130 /* [0x10] RX VMPR control */
132 /* [0x14] RX VMPR Buffer2 MSB address */
134 /* [0x18] RX queue Target-ID values */
136 /* [0x1c] RX queue BUF1 Target-ID values */
138 /* [0x20] RX queue BUF2 Target-ID values */
140 /* [0x24] RX queue Direct Data Placement Target-ID values */
142 /* [0x28] RX VMPR BUF1 Address High Regsiter */
144 /* [0x2c] RX VMPR BUF2 Address High Regsiter */
146 /* [0x30] RX VMPR DDP Address High Regsiter */
152 struct udma_iofic_regs interrupt_regs; /* [0x0000] */
153 struct udma_gen_dma_misc dma_misc; /* [0x2080] */
154 struct udma_gen_mailbox mailbox[4]; /* [0x2180] */
155 struct udma_gen_axi axi; /* [0x2280] */
156 struct udma_gen_sram_ctrl sram_ctrl[25]; /* [0x2380] */
158 struct udma_gen_tgtid tgtid; /* [0x23ec] */
159 struct udma_gen_tgtaddr tgtaddr; /* [0x2400] */
161 struct udma_gen_vmpr vmpr[4]; /* [0x2800] */
174 * 0 – 32 bit
176 #define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_64 (1 << 0)
178 #define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_3_1_MASK 0x0000000E
181 #define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_AXI_QOS_MASK 0x00000070
184 #define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_31_7_MASK 0xFFFFFF80
189 #define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_MASK 0x00000FFF
190 #define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_SHIFT 0
192 #define UDMA_GEN_DMA_MISC_REVISION_MINOR_ID_MASK 0x00FFF000
195 #define UDMA_GEN_DMA_MISC_REVISION_MAJOR_ID_MASK 0xFF000000
200 #define UDMA_GEN_MAILBOX_INTERRUPT_SET (1 << 0)
207 #define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK 0x0000000F
208 #define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_SHIFT 0
212 #define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC (1 << 0)
221 * 0 - Swap groups of 4 bytes
228 #define UDMA_GEN_SRAM_CTRL_TIMING_RMA_MASK 0x0000000F
229 #define UDMA_GEN_SRAM_CTRL_TIMING_RMA_SHIFT 0
233 #define UDMA_GEN_SRAM_CTRL_TIMING_RMB_MASK 0x000F0000
239 /* For M2S queues 3:0, enable usage of the Target-ID from the buffer address 63:56 */
240 #define UDMA_GEN_TGTID_CFG_TGTID_0_TX_Q_TGTID_DESC_EN_MASK 0x0000000F
241 #define UDMA_GEN_TGTID_CFG_TGTID_0_TX_Q_TGTID_DESC_EN_SHIFT 0
243 * For M2S queues 3:0, enable usage of the Target-ID from the configuration register
246 #define UDMA_GEN_TGTID_CFG_TGTID_0_TX_Q_TGTID_QUEUE_EN_MASK 0x000000F0
248 /* use Target-ID_n [7:0] from MSI-X Controller for MSI-X message */
252 /* For S2M queues 3:0, enable usage of the Target-ID from the buffer address 63:56 */
253 #define UDMA_GEN_TGTID_CFG_TGTID_0_RX_Q_TGTID_DESC_EN_MASK 0x000F0000
256 * For S2M queues 3:0, enable usage of the Target-ID from the configuration register
259 #define UDMA_GEN_TGTID_CFG_TGTID_0_RX_Q_TGTID_QUEUE_EN_MASK 0x00F00000
262 #define UDMA_GEN_TGTID_CFG_TGTID_SHIFT(qid) (((qid) & 0x1) ? 16 : 0)
263 #define UDMA_GEN_TGTID_CFG_TGTID_MASK(qid) (((qid) & 0x1) ? 0xFFFF0000 : 0x0000FFFF)
266 /* TX queue 0 Target-ID value */
267 #define UDMA_GEN_TGTID_CFG_TGTID_1_TX_Q_0_TGTID_MASK 0x0000FFFF
268 #define UDMA_GEN_TGTID_CFG_TGTID_1_TX_Q_0_TGTID_SHIFT 0
270 #define UDMA_GEN_TGTID_CFG_TGTID_1_TX_Q_1_TGTID_MASK 0xFFFF0000
275 #define UDMA_GEN_TGTID_CFG_TGTID_2_TX_Q_2_TGTID_MASK 0x0000FFFF
276 #define UDMA_GEN_TGTID_CFG_TGTID_2_TX_Q_2_TGTID_SHIFT 0
278 #define UDMA_GEN_TGTID_CFG_TGTID_2_TX_Q_3_TGTID_MASK 0xFFFF0000
282 /* RX queue 0 Target-ID value */
283 #define UDMA_GEN_TGTID_CFG_TGTID_3_RX_Q_0_TGTID_MASK 0x0000FFFF
284 #define UDMA_GEN_TGTID_CFG_TGTID_3_RX_Q_0_TGTID_SHIFT 0
286 #define UDMA_GEN_TGTID_CFG_TGTID_3_RX_Q_1_TGTID_MASK 0xFFFF0000
291 #define UDMA_GEN_TGTID_CFG_TGTID_4_RX_Q_2_TGTID_MASK 0x0000FFFF
292 #define UDMA_GEN_TGTID_CFG_TGTID_4_RX_Q_2_TGTID_SHIFT 0
294 #define UDMA_GEN_TGTID_CFG_TGTID_4_RX_Q_3_TGTID_MASK 0xFFFF0000
297 #define UDMA_GEN_TGTADDR_CFG_SHIFT(qid) (((qid) & 0x1) ? 16 : 0)
298 #define UDMA_GEN_TGTADDR_CFG_MASK(qid) (((qid) & 0x1) ? 0xFFFF0000 : 0x0000FFFF)
301 /* TX queue 0 Target-Address value */
302 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_0_TX_Q_0_TGTADDR_MASK 0x0000FFFF
303 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_0_TX_Q_0_TGTADDR_SHIFT 0
305 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_0_TX_Q_1_TGTADDR_MASK 0xFFFF0000
310 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_1_TX_Q_2_TGTADDR_MASK 0x0000FFFF
311 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_1_TX_Q_2_TGTADDR_SHIFT 0
313 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_1_TX_Q_3_TGTADDR_MASK 0xFFFF0000
317 /* RX queue 0 Target-Address value */
318 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_2_RX_Q_0_TGTADDR_MASK 0x0000FFFF
319 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_2_RX_Q_0_TGTADDR_SHIFT 0
321 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_2_RX_Q_1_TGTADDR_MASK 0xFFFF0000
326 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_3_RX_Q_2_TGTADDR_MASK 0x0000FFFF
327 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_3_RX_Q_2_TGTADDR_SHIFT 0
329 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_3_RX_Q_3_TGTADDR_MASK 0xFFFF0000
334 #define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_MASK 0x0000003F
335 #define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_SHIFT 0
345 #define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_TGTID_MASK 0x0000FFFF
346 #define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_TGTID_SHIFT 0
348 #define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_TGTID_MASK 0xFFFF0000
353 #define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_TGTID_MASK 0x0000FFFF
354 #define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_TGTID_SHIFT 0
356 #define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_TGTID_SEL_MASK 0xFFFF0000
361 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_MASK 0x0000003F
362 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_SHIFT 0
366 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_MASK 0x00003F00
371 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_MASK 0x003F0000
376 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_MASK 0x0F000000
385 #define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_TGTID_MASK 0x0000FFFF
386 #define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_TGTID_SHIFT 0
388 #define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_TGTID_MASK 0xFFFF0000
393 #define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_TGTID_MASK 0x0000FFFF
394 #define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_TGTID_SHIFT 0
396 #define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_TGTID_SEL_MASK 0xFFFF0000
401 #define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_TGTID_MASK 0x0000FFFF
402 #define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_TGTID_SHIFT 0
404 #define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_TGTID_SEL_MASK 0xFFFF0000
409 #define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_TGTID_MASK 0x0000FFFF
410 #define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_TGTID_SHIFT 0
412 #define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_TGTID_SEL_MASK 0xFFFF0000