113 		reg_addr = &udma_q->q_regs->m2s_q.rlimit.mask;  in al_udma_q_config()
136 		reg_addr = &udma_q->q_regs->m2s_q.comp_cfg;  in al_udma_q_config_compl()
138 		reg_addr = &udma_q->q_regs->s2m_q.comp_cfg;  in al_udma_q_config_compl()
179 	al_reg_write32(&udma_q->q_regs->rings.drbp_low,  in al_udma_q_set_pointers()
181 	al_reg_write32(&udma_q->q_regs->rings.drbp_high,  in al_udma_q_set_pointers()
184 	al_reg_write32(&udma_q->q_regs->rings.drl, udma_q->size);  in al_udma_q_set_pointers()
194 		al_reg_write32(&udma_q->q_regs->rings.crbp_low,  in al_udma_q_set_pointers()
196 		al_reg_write32(&udma_q->q_regs->rings.crbp_high,  in al_udma_q_set_pointers()
213 	uint32_t reg = al_reg_read32(&udma_q->q_regs->rings.cfg);  in al_udma_q_enable()
222 	al_reg_write32(&udma_q->q_regs->rings.cfg, reg);  in al_udma_q_enable()
311 		udma_q->q_regs = (union udma_q_regs __iomem *)  in al_udma_q_init()
314 		udma_q->q_regs = (union udma_q_regs __iomem *)  in al_udma_q_init()
384 	status_reg = &udma_q->q_regs->rings.status;  in al_udma_q_reset()
406 	dcp_reg = &udma_q->q_regs->rings.dcp;  in al_udma_q_reset()
407 	crhp_reg = &udma_q->q_regs->rings.crhp;  in al_udma_q_reset()
428 		q_sw_ctrl_reg = &udma_q->q_regs->m2s_q.q_sw_ctrl;  in al_udma_q_reset()
430 		q_sw_ctrl_reg = &udma_q->q_regs->s2m_q.q_sw_ctrl;  in al_udma_q_reset()