Lines Matching refs:m2s
142 &udma->udma_regs->m2s.axi_m2s.comp_wr_cfg_1, in al_udma_m2s_axi_set()
143 &udma->udma_regs->m2s.axi_m2s.comp_wr_cfg_2, in al_udma_m2s_axi_set()
144 &udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1); in al_udma_m2s_axi_set()
147 &udma->udma_regs->m2s.axi_m2s.data_rd_cfg_1, in al_udma_m2s_axi_set()
148 &udma->udma_regs->m2s.axi_m2s.data_rd_cfg_2, in al_udma_m2s_axi_set()
149 &udma->udma_regs->m2s.axi_m2s.data_rd_cfg); in al_udma_m2s_axi_set()
152 &udma->udma_regs->m2s.axi_m2s.desc_rd_cfg_1, in al_udma_m2s_axi_set()
153 &udma->udma_regs->m2s.axi_m2s.desc_rd_cfg_2, in al_udma_m2s_axi_set()
154 &udma->udma_regs->m2s.axi_m2s.desc_rd_cfg_3); in al_udma_m2s_axi_set()
156 reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.data_rd_cfg); in al_udma_m2s_axi_set()
161 al_reg_write32(&udma->udma_regs->m2s.axi_m2s.data_rd_cfg, reg); in al_udma_m2s_axi_set()
163 reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1); in al_udma_m2s_axi_set()
168 al_reg_write32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1, reg); in al_udma_m2s_axi_set()
170 reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.ostand_cfg); in al_udma_m2s_axi_set()
186 al_reg_write32(&udma->udma_regs->m2s.axi_m2s.ostand_cfg, reg); in al_udma_m2s_axi_set()
303 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s.cfg_len); in al_udma_m2s_packet_size_cfg_set()
327 al_reg_write32(&udma->udma_regs->m2s.m2s.cfg_len, reg); in al_udma_m2s_packet_size_cfg_set()
349 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1); in al_udma_m2s_pref_set()
352 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1, reg); in al_udma_m2s_pref_set()
354 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2); in al_udma_m2s_pref_set()
368 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2, reg); in al_udma_m2s_pref_set()
370 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3); in al_udma_m2s_pref_set()
385 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3, reg); in al_udma_m2s_pref_set()
387 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.data_cfg); in al_udma_m2s_pref_set()
396 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.data_cfg, reg); in al_udma_m2s_pref_set()
407 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1); in al_udma_m2s_pref_get()
412 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2); in al_udma_m2s_pref_get()
422 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3); in al_udma_m2s_pref_get()
458 al_reg_write32_masked(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2, in al_udma_m2s_max_descs_set()
462 al_reg_write32_masked(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3, in al_udma_m2s_max_descs_set()
664 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_dwrr.cfg_sched); in al_udma_m2s_sc_set()
680 al_reg_write32(&udma->udma_regs->m2s.m2s_dwrr.cfg_sched, reg); in al_udma_m2s_sc_set()
682 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_dwrr.ctrl_deficit_cnt); in al_udma_m2s_sc_set()
685 al_reg_write32(&udma->udma_regs->m2s.m2s_dwrr.ctrl_deficit_cnt, reg); in al_udma_m2s_sc_set()
695 &udma->udma_regs->m2s.m2s_rate_limiter.gen_cfg); in al_udma_m2s_rlimit_set()
704 al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.gen_cfg, reg); in al_udma_m2s_rlimit_set()
706 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_token); in al_udma_m2s_rlimit_set()
710 al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_token, reg); in al_udma_m2s_rlimit_set()
718 &udma->udma_regs->m2s.m2s_rate_limiter.ctrl_cycle_cnt); in al_udma_m2s_rlimit_reset()
720 al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_cycle_cnt, in al_udma_m2s_rlimit_reset()
796 &udma->udma_regs->m2s.m2s_stream_rate_limiter.rlimit; in al_udma_m2s_strm_rlimit_set()
805 &udma->udma_regs->m2s.m2s_stream_rate_limiter.rlimit; in al_udma_m2s_strm_rlimit_act()
896 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_1c); in al_udma_m2s_comp_timeouts_set()
919 al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_1c, reg); in al_udma_m2s_comp_timeouts_set()
921 al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_coal in al_udma_m2s_comp_timeouts_set()
924 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_application_ack); in al_udma_m2s_comp_timeouts_set()
927 al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_application_ack, reg); in al_udma_m2s_comp_timeouts_set()
934 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_1c); in al_udma_m2s_comp_timeouts_get()
956 &udma->udma_regs->m2s.m2s_comp.cfg_coal); in al_udma_m2s_comp_timeouts_get()
959 &udma->udma_regs->m2s.m2s_comp.cfg_application_ack); in al_udma_m2s_comp_timeouts_get()