Lines Matching full:conf
301 struct al_udma_m2s_pkt_len_conf *conf) in al_udma_m2s_packet_size_cfg_set() argument
308 if (conf->encode_64k_as_zero == AL_TRUE) in al_udma_m2s_packet_size_cfg_set()
311 if (conf->max_pkt_size > max_supported_size) { in al_udma_m2s_packet_size_cfg_set()
314 conf->max_pkt_size, max_supported_size); in al_udma_m2s_packet_size_cfg_set()
319 if (conf->encode_64k_as_zero == AL_TRUE) in al_udma_m2s_packet_size_cfg_set()
325 reg |= conf->max_pkt_size; in al_udma_m2s_packet_size_cfg_set()
345 struct al_udma_m2s_desc_pref_conf *conf) in al_udma_m2s_pref_set() argument
351 reg |= conf->desc_fifo_depth; in al_udma_m2s_pref_set()
356 if (conf->sch_mode == SRR) in al_udma_m2s_pref_set()
358 else if (conf->sch_mode == STRICT) in al_udma_m2s_pref_set()
362 "mode (%d) is invalid\n", udma->name, conf->sch_mode); in al_udma_m2s_pref_set()
366 reg |= conf->max_desc_per_packet & in al_udma_m2s_pref_set()
372 reg |= conf->min_burst_below_thr & in al_udma_m2s_pref_set()
376 reg |=(conf->min_burst_above_thr << in al_udma_m2s_pref_set()
381 reg |= (conf->pref_thr << in al_udma_m2s_pref_set()
389 reg |= conf->data_fifo_depth & in al_udma_m2s_pref_set()
393 reg |= (conf->max_pkt_limit in al_udma_m2s_pref_set()
403 struct al_udma_m2s_desc_pref_conf *conf) in al_udma_m2s_pref_get() argument
408 conf->desc_fifo_depth = in al_udma_m2s_pref_get()
414 conf->sch_mode = SRR; in al_udma_m2s_pref_get()
416 conf->sch_mode = STRICT; in al_udma_m2s_pref_get()
417 conf->max_desc_per_packet = in al_udma_m2s_pref_get()
424 conf->min_burst_below_thr = in al_udma_m2s_pref_get()
429 conf->min_burst_above_thr = in al_udma_m2s_pref_get()
434 conf->pref_thr = AL_REG_FIELD_GET(reg, in al_udma_m2s_pref_get()
514 struct al_udma_s2m_desc_pref_conf *conf) in al_udma_s2m_pref_set() argument
520 reg |= conf->desc_fifo_depth; in al_udma_s2m_pref_set()
525 if (conf->sch_mode == SRR) in al_udma_s2m_pref_set()
527 else if (conf->sch_mode == STRICT) in al_udma_s2m_pref_set()
531 "mode (%d) is invalid\n", udma->name, conf->sch_mode); in al_udma_s2m_pref_set()
534 if (conf->q_promotion == AL_TRUE) in al_udma_s2m_pref_set()
539 if (conf->force_promotion == AL_TRUE) in al_udma_s2m_pref_set()
544 if (conf->en_pref_prediction == AL_TRUE) in al_udma_s2m_pref_set()
550 reg |= (conf->promotion_th in al_udma_s2m_pref_set()
558 reg |= (conf->pref_thr << UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT) & in al_udma_s2m_pref_set()
562 reg |= conf->min_burst_below_thr & in al_udma_s2m_pref_set()
566 reg |=(conf->min_burst_above_thr << in al_udma_s2m_pref_set()
574 reg |= conf->a_full_thr & UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK; in al_udma_s2m_pref_set()
583 struct al_udma_s2m_data_write_conf *conf) in al_udma_s2m_data_write_set() argument
589 reg |= conf->data_fifo_depth & in al_udma_s2m_data_write_set()
592 reg |= (conf->max_pkt_limit << in al_udma_s2m_data_write_set()
596 reg |= (conf->fifo_margin << in al_udma_s2m_data_write_set()
603 reg |= conf->desc_wait_timer & in al_udma_s2m_data_write_set()
610 reg |= conf->flags & in al_udma_s2m_data_write_set()
623 struct al_udma_s2m_completion_conf *conf) in al_udma_s2m_completion_set() argument
627 reg |= conf->desc_size & UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK; in al_udma_s2m_completion_set()
628 if (conf->cnt_words == AL_TRUE) in al_udma_s2m_completion_set()
632 if (conf->q_promotion == AL_TRUE) in al_udma_s2m_completion_set()
636 if (conf->force_rr == AL_TRUE) in al_udma_s2m_completion_set()
641 reg |= (conf->q_free_min << UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_SHIFT) & in al_udma_s2m_completion_set()
647 reg |= conf->comp_fifo_depth in al_udma_s2m_completion_set()
650 reg |= (conf->unack_fifo_depth in al_udma_s2m_completion_set()
656 conf->timeout); in al_udma_s2m_completion_set()
727 struct al_udma_m2s_rlimit_cfg *conf) in al_udma_common_rlimit_set() argument
734 reg |= conf->max_burst_sz & in al_udma_common_rlimit_set()
740 reg |= conf->long_cycle_sz & in al_udma_common_rlimit_set()
746 reg |= conf->long_cycle & in al_udma_common_rlimit_set()
752 reg |= conf->short_cycle & in al_udma_common_rlimit_set()
758 reg |= conf->mask & 0xf; in al_udma_common_rlimit_set()
793 struct al_udma_m2s_rlimit_cfg *conf) in al_udma_m2s_strm_rlimit_set() argument
798 return al_udma_common_rlimit_set(rlimit_regs, conf); in al_udma_m2s_strm_rlimit_set()
817 struct al_udma_m2s_rlimit_cfg *conf) in al_udma_m2s_q_rlimit_set() argument
821 return al_udma_common_rlimit_set(rlimit_regs, conf); in al_udma_m2s_q_rlimit_set()
840 struct al_udma_m2s_q_dwrr_conf *conf) in al_udma_m2s_q_sc_set() argument
845 reg |= conf->max_deficit_cnt_sz & in al_udma_m2s_q_sc_set()
847 if (conf->strict == AL_TRUE) in al_udma_m2s_q_sc_set()
855 reg |= (conf->axi_qos << UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_SHIFT) & in al_udma_m2s_q_sc_set()
858 reg |= conf->q_qos & UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK; in al_udma_m2s_q_sc_set()
863 reg |= conf->weight & UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK; in al_udma_m2s_q_sc_set()
894 struct al_udma_m2s_comp_timeouts *conf) in al_udma_m2s_comp_timeouts_set() argument
898 if (conf->sch_mode == SRR) in al_udma_m2s_comp_timeouts_set()
900 else if (conf->sch_mode == STRICT) in al_udma_m2s_comp_timeouts_set()
905 udma->name, conf->sch_mode); in al_udma_m2s_comp_timeouts_set()
908 if (conf->enable_q_promotion == AL_TRUE) in al_udma_m2s_comp_timeouts_set()
914 conf->comp_fifo_depth << UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_SHIFT; in al_udma_m2s_comp_timeouts_set()
917 reg |= conf->unack_fifo_depth in al_udma_m2s_comp_timeouts_set()
922 , conf->coal_timeout); in al_udma_m2s_comp_timeouts_set()
926 reg |= conf->app_timeout << UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_SHIFT; in al_udma_m2s_comp_timeouts_set()
932 struct al_udma_m2s_comp_timeouts *conf) in al_udma_m2s_comp_timeouts_get() argument
937 conf->sch_mode = SRR; in al_udma_m2s_comp_timeouts_get()
939 conf->sch_mode = STRICT; in al_udma_m2s_comp_timeouts_get()
942 conf->enable_q_promotion = AL_TRUE; in al_udma_m2s_comp_timeouts_get()
944 conf->enable_q_promotion = AL_FALSE; in al_udma_m2s_comp_timeouts_get()
946 conf->comp_fifo_depth = in al_udma_m2s_comp_timeouts_get()
950 conf->unack_fifo_depth = in al_udma_m2s_comp_timeouts_get()
955 conf->coal_timeout = al_reg_read32( in al_udma_m2s_comp_timeouts_get()
961 conf->app_timeout = in al_udma_m2s_comp_timeouts_get()
1077 struct al_udma_s2m_q_comp_conf *conf) in al_udma_s2m_q_comp_set() argument
1080 if (conf->en_comp_ring_update == AL_TRUE) in al_udma_s2m_q_comp_set()
1085 if (conf->dis_comp_coal == AL_TRUE) in al_udma_s2m_q_comp_set()
1092 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg_2, conf->comp_timer); in al_udma_s2m_q_comp_set()
1097 reg |= conf->hdr_split_size & UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK; in al_udma_s2m_q_comp_set()
1098 if (conf->force_hdr_split == AL_TRUE) in al_udma_s2m_q_comp_set()
1102 if (conf->en_hdr_split == AL_TRUE) in al_udma_s2m_q_comp_set()
1111 reg |= conf->q_qos & UDMA_S2M_QOS_CFG_Q_QOS_MASK; in al_udma_s2m_q_comp_set()
1120 struct al_udma_gen_tgtid_conf *conf, in al_udma_gen_tgtid_conf_queue_set() argument
1131 (conf->tx_q_conf[qid].desc_en << qid) << in al_udma_gen_tgtid_conf_queue_set()
1133 (conf->tx_q_conf[qid].desc_en << qid) << in al_udma_gen_tgtid_conf_queue_set()
1138 (conf->tx_q_conf[qid].queue_en << qid) << in al_udma_gen_tgtid_conf_queue_set()
1140 (conf->tx_q_conf[qid].queue_en << qid) << in al_udma_gen_tgtid_conf_queue_set()
1145 (conf->rx_q_conf[qid].desc_en << qid) << in al_udma_gen_tgtid_conf_queue_set()
1147 (conf->rx_q_conf[qid].desc_en << qid) << in al_udma_gen_tgtid_conf_queue_set()
1152 (conf->rx_q_conf[qid].queue_en << qid) << in al_udma_gen_tgtid_conf_queue_set()
1154 (conf->rx_q_conf[qid].queue_en << qid) << in al_udma_gen_tgtid_conf_queue_set()
1179 conf->tx_q_conf[qid].tgtid << UDMA_GEN_TGTID_CFG_TGTID_SHIFT(qid)); in al_udma_gen_tgtid_conf_queue_set()
1183 conf->rx_q_conf[qid].tgtid << UDMA_GEN_TGTID_CFG_TGTID_SHIFT(qid)); in al_udma_gen_tgtid_conf_queue_set()
1188 conf->tx_q_conf[qid].tgtaddr << UDMA_GEN_TGTADDR_CFG_SHIFT(qid)); in al_udma_gen_tgtid_conf_queue_set()
1192 conf->rx_q_conf[qid].tgtaddr << UDMA_GEN_TGTADDR_CFG_SHIFT(qid)); in al_udma_gen_tgtid_conf_queue_set()
1199 struct al_udma_gen_tgtid_conf *conf) in al_udma_gen_tgtid_conf_set() argument
1204 al_udma_gen_tgtid_conf_queue_set(unit_regs, conf, i); in al_udma_gen_tgtid_conf_set()
1210 struct al_udma_gen_tgtid_msix_conf *conf) in al_udma_gen_tgtid_msix_conf_set() argument
1216 (conf->access_en ? UDMA_GEN_TGTID_CFG_TGTID_0_MSIX_TGTID_ACCESS_EN : 0) | in al_udma_gen_tgtid_msix_conf_set()
1217 (conf->sel ? UDMA_GEN_TGTID_CFG_TGTID_0_MSIX_TGTID_SEL : 0)); in al_udma_gen_tgtid_msix_conf_set()