1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
60 /* *INDENT-OFF* */
64 /* *INDENT-ON* */
78 /* Statistics - TBD */
82 	/* TX */
87 	} tx;  member
88 	/* TX Meta, used by upper layer */
103 /* TX desc length and control fields */
132 /* TX/RX descriptor Target-ID field (in the buffer address 64 bit field) */
137 	/* TX completion */
148 /* TX/RX common completion desc ctrl_meta feilds */
167 	uint32_t num; /**< Number of buffers of the block */  member
170 	 * Target-ID to be assigned to the block descriptors
171 	 * Requires Target-ID in descriptor to be enabled for the specific UDMA
228 	enum al_udma_type type;	/**< Tx or Rx */
229 	uint8_t num_of_queues; /**< number of queues supported by the UDMA */
247 					 * equals to size - 1
303 	enum al_udma_type type;	/* Tx or Rx */
305 	uint8_t num_of_queues; /* number of queues supported by the UDMA */
324  * @return 0 on success. -EINVAL otherwise.
336  *	   -EINVAL if the qid is out of range
337  *	   -EIO if queue was already initialized
370  * @return  0 on success. -EINVAL otherwise.
403  * @return num of free descriptors.
407 	uint16_t tmp = udma_q->next_cdesc_idx - (udma_q->next_desc_idx + 1);  in al_udma_available_get()
408 	tmp &= udma_q->size_mask;  in al_udma_available_get()
423 	if (((udma_q->next_cdesc_idx - udma_q->next_desc_idx) &  in al_udma_is_empty()
424 	     udma_q->size_mask) == 0)  in al_udma_is_empty()
443 	next_desc_idx = udma_q->next_desc_idx;  in al_udma_desc_get()
444 	desc = udma_q->desc_base_ptr + next_desc_idx;  in al_udma_desc_get()
449 	udma_q->next_desc_idx = next_desc_idx & udma_q->size_mask;  in al_udma_desc_get()
468 	ring_id = udma_q->desc_ring_id;  in al_udma_ring_id_get()
472 	if (unlikely(udma_q->next_desc_idx) == 0)  in al_udma_ring_id_get()
473 		udma_q->desc_ring_id = (udma_q->desc_ring_id + 1) &  in al_udma_ring_id_get()
478 /* add DMA action - trigger the engine */
480  * add num descriptors to the submission queue.
483  * @param num number of descriptors to add to the queues ring.
488 					  uint32_t num)  in al_udma_desc_action_add()  argument
493 	al_assert((num > 0) && (num <= udma_q->size));  in al_udma_desc_action_add()
495 	addr = &udma_q->q_regs->rings.drtp_inc;  in al_udma_desc_action_add()
504 	al_reg_write32_relaxed(addr, num);  in al_udma_desc_action_add()
525 	volatile uint8_t *tmp = (volatile uint8_t *) cdesc + offset * udma_q->cdesc_size;  in al_cdesc_next()
530 	if (unlikely((tmp > udma_q->end_cdesc_ptr)))  in al_cdesc_next()
532 			(udma_q->cdesc_base_ptr +  in al_cdesc_next()
533 			(tmp - udma_q->end_cdesc_ptr - udma_q->cdesc_size));  in al_cdesc_next()
553 	    == udma_q->comp_ring_id)  in al_udma_new_cdesc()
574 	if (unlikely(((volatile uint8_t *) cdesc == udma_q->end_cdesc_ptr))) {  in al_cdesc_next_update()
575 		udma_q->comp_ring_id =  in al_cdesc_next_update()
576 		    (udma_q->comp_ring_id + 1) & DMA_RING_ID_MASK;  in al_cdesc_next_update()
577 		return (union al_udma_cdesc *) udma_q->cdesc_base_ptr;  in al_cdesc_next_update()
579 	return (volatile union al_udma_cdesc *) ((volatile uint8_t *) cdesc + udma_q->cdesc_size);  in al_cdesc_next_update()
607 	((volatile union al_udma_cdesc *) ((udma_q)->cdesc_base_ptr +	\
608 				(idx) * (udma_q)->cdesc_size))
632 	udma_q->comp_head_idx = (uint16_t)  in al_udma_cdesc_get_all()
633 				(al_reg_read32(&udma_q->q_regs->rings.crhp) &  in al_udma_cdesc_get_all()
636 	count = (udma_q->comp_head_idx - udma_q->next_cdesc_idx) &  in al_udma_cdesc_get_all()
637 		udma_q->size_mask;  in al_udma_cdesc_get_all()
640 		*cdesc = al_udma_cdesc_idx_to_ptr(udma_q, udma_q->next_cdesc_idx);  in al_udma_cdesc_get_all()
650  * @param num number of descriptors to acknowledge
654 static INLINE int al_udma_cdesc_ack(struct al_udma_q *udma_q, uint32_t num)  in al_udma_cdesc_ack()  argument
658 	udma_q->next_cdesc_idx += num;  in al_udma_cdesc_ack()
659 	udma_q->next_cdesc_idx &= udma_q->size_mask;  in al_udma_cdesc_ack()
664 /* *INDENT-OFF* */
668 /* *INDENT-ON* */