Lines Matching +full:cdr +full:- +full:mode
9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
95 /** Serdes loopback mode */
108 * Loops back the TX serializer output into the CDR.
109 * CDR recovered bit clock used (without attenuation)
115 * CDR recovered bit clock used (only through IO)
122 * CDR recovered bit clock used
168 /** SerDes power mode */
178 * Tx de-emphasis parameters
183 AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */
196 * Transmit Amplitude control signal. Used to define the full-scale
198 * 000 - Not Supported
199 * 001 - 952mVdiff-pkpk
200 * 010 - 1024mVdiff-pkpk
201 * 011 - 1094mVdiff-pkpk
202 * 100 - 1163mVdiff-pkpk
203 * 101 - 1227mVdiff-pkpk
204 * 110 - 1283mVdiff-pkpk
205 * 111 - 1331mVdiff-pkpk
211 * first post-cursor (C+1) tap. */
214 * second post-cursor (C+2) tap. */
217 * first pre-cursor (C-1) tap. */
220 * 00 - 31ps
221 * 01 - 33ps
222 * 10 - 68ps
223 * 11 - 170ps
238 * -3'b000: -3dB
239 * -3'b001: -2.5dB
240 * -3'b010: -2dB
241 * -3'b011: -1.5dB
242 * -3'b100: -1dB
243 * -3'b101: -0.5dB
244 * -3'b110: -0dB
245 * -3'b111: 0.5dB
248 /* DFE post-shaping tap 3dB frequency
249 * -3'b000: 684MHz
250 * -3'b001: 576MHz
251 * -3'b010: 514MHz
252 * -3'b011: 435MHz
253 * -3'b100: 354MHz
254 * -3'b101: 281MHz
255 * -3'b110: 199MHz
256 * -3'b111: 125MHz
259 /* DFE post-shaping tap gain
261 * 1: -24mVpeak
262 * 2: -45mVpeak
263 * 3: -64mVpeak
264 * 4: -80mVpeak
265 * 5: -93mVpeak
266 * 6: -101mVpeak
267 * 7: -105mVpeak
271 * -4'b0000: +1mVpeak
272 * -4'b0001: +10mVpeak
274 * -4'b0110: +55mVpeak
275 * -4'b0111: +64mVpeak
276 * -4'b1000: -1mVpeak
277 * -4'b1001: -10mVpeak
279 * -4'b1110: -55mVpeak
280 * -4'b1111: -64mVpeak
284 * -4'b0000: +0mVpeak
285 * -4'b0001: +9mVpeak
287 * -4'b0110: +46mVpeak
288 * -4'b0111: +53mVpeak
289 * -4'b1000: -0mVpeak
290 * -4'b1001: -9mVpeak
292 * -4'b1110: -46mVpeak
293 * -4'b1111: -53mVpeak
297 * -4'b0000: +0mVpeak
298 * -4'b0001: +7mVpeak
300 * -4'b0110: +38mVpeak
301 * -4'b0111: +44mVpeak
302 * -4'b1000: -0mVpeak
303 * -4'b1001: -7mVpeak
305 * -4'b1110: -38mVpeak
306 * -4'b1111: -44mVpeak
310 * -4'b0000: +0mVpeak
311 * -4'b0001: +6mVpeak
313 * -4'b0110: +29mVpeak
314 * -4'b0111: +33mVpeak
315 * -4'b1000: -0mVpeak
316 * -4'b1001: -6mVpeak
318 * -4'b1110: -29mVpeak
319 * -4'b1111: -33mVpeak
323 * -3'b000: Disconnected
324 * -3'b001: -18.5dB
325 * -3'b010: -12.5dB
326 * -3'b011: -9dB
327 * -3'b100: -6.5dB
328 * -3'b101: -4.5dB
329 * -3'b110: -2.9dB
330 * -3'b111: -1.6dB
333 /* Provides a RX Equalizer pre-hint, prior to beginning
344 /* ATT (PLE Flat-Band Gain) */
346 /* APG (CTLE's Flat-Band Gain) */
348 /* LFG (Low-Freq Gain) */
350 /* HFG (High-Freq Gain) */
352 /* MBG (MidBand-Freq-knob Gain) */
354 /* MBF (MidBand-Freq-knob Frequency position Gain) */
420 /* Controls the frequency accuracy threshold (ppm) for lock detection CDR */
422 /* Controls the frequency accuracy threshold (ppm) for lock detection in the CDR */
431 * Sets the depth of the buffer while in PCIE mode, GEN1/GEN2
435 * Sets the depth of the buffer while in PCIE mode, GEN3
440 /** SerDes PCIe Rate - values are important for proper behavior */
464 * @param offset The SERDES register offset (0 - 4095)
478 * @param offset The SERDES register offset (0 - 4095)
560 * SERDES group power mode control
564 * @param pm The required power mode
568 * SERDES lane power mode control
573 * @param rx_pm The required RX power mode
574 * @param tx_pm The required TX power mode
603 * @param mode The requested loopback mode
657 * Set the tx de-emphasis to preset values
665 * Increase tx de-emphasis param.
669 * @param param which tx de-emphasis to change
676 * Decrease tx de-emphasis param.
680 * @param param which tx de-emphasis to change
693 * (0 - completely closed eye, 0xffff - completely open eye).
704 * @param x Sampling X position (0 - 63 --> -1.00 UI ... 1.00 UI)
705 * @param y Sampling Y position (0 - 62 --> 500mV ... -500mV)
707 * @param value Eye diagram sample value (BER - 0x0000 - 0xffff)
727 * @param buf_size array size - must be equal to
728 * (((y_stop - y_start) / y_step) + 1) *
729 * (((x_stop - x_start) / x_step) + 1)
747 * Check if CDR is locked
752 * @return true if cdr is locked. false otherwise.
799 * Switch entire SerDes group to SGMII mode based on 156.25 Mhz reference clock
806 * Switch entire SerDes group to KR mode based on 156.25 Mhz reference clock
866 /* *INDENT-OFF* */
871 /* *INDENT-ON* */