Lines Matching +full:0 +full:x234
51 /* [0x0] */
53 /* [0x4] */
55 /* [0x8] */
58 /* [0x10] */
63 /* [0x0] */
65 /* [0x4] */
67 /* [0x8] */
70 /* [0x10] */
72 /* [0x14] */
74 /* [0x18] */
76 /* [0x1c] */
80 /* [0x0] */
82 /* [0x4] */
84 /* [0x8] */
86 /* [0xc] */
88 /* [0x10] */
90 /* [0x14] */
96 /* [0x0] */
100 /* [0x0] */
104 /* [0x0] */
106 /* [0x4] */
108 /* [0x8] */
110 /* [0xc] */
112 /* [0x10] */
114 /* [0x14] */
116 /* [0x18] */
118 /* [0x1c] */
120 /* [0x20] */
122 /* [0x24] */
124 /* [0x28] */
126 /* [0x2c] */
128 /* [0x30] */
130 /* [0x34] */
132 /* [0x38] */
134 /* [0x3c] */
136 /* [0x40] */
138 /* [0x44] */
140 /* [0x48] */
142 /* [0x4c] */
144 /* [0x50] */
146 /* [0x54] */
148 /* [0x58] */
150 /* [0x5c] */
152 /* [0x60] */
154 /* [0x64] */
156 /* [0x68] */
158 /* [0x6c] */
160 /* [0x70] */
162 /* [0x74] */
164 /* [0x78] */
166 /* [0x7c] */
168 /* [0x80] */
170 /* [0x84] */
172 /* [0x88] */
174 /* [0x8c] */
176 /* [0x90] */
178 /* [0x94] */
180 /* [0x98] */
182 /* [0x9c] */
184 /* [0xa0] */
186 /* [0xa4] */
192 /* [0x0] */
194 /* [0x4] */
196 /* [0x8] */
198 /* [0xc] */
202 /* [0x0] */
204 /* [0x4] */
206 /* [0x8] */
208 /* [0xc] */
211 /* [0x14] */
215 /* [0x0] */
217 /* [0x4] */
221 /* [0x0] */
223 /* [0x4] */
227 /* [0x0] */
231 /* [0x0] */
233 /* [0x4] */
237 /* [0x0] */
241 /* [0x0] */
243 /* [0x18] */
247 /* [0x0] */
249 /* [0x30] */
251 /* [0x50] */
256 /* [0x0] */
260 /* [0x0] */
262 /* [0x4] */
264 /* [0x8] */
266 /* [0xc] */
268 /* [0x10] */
270 /* [0x14] */
272 /* [0x18] */
276 /* [0x0] */
280 /* [0x0] */
282 /* [0x4] */
284 /* [0x8] */
286 /* [0xc] */
288 /* [0x10] */
290 /* [0x14] */
292 /* [0x18] */
294 /* [0x1c] */
296 /* [0x20] */
298 /* [0x24] */
302 /* [0x0] */
304 /* [0x4] */
306 /* [0x8] */
308 /* [0xc] */
310 /* [0x10] */
312 /* [0x14] */
314 /* [0x18] */
316 /* [0x1c] */
318 /* [0x20] */
320 /* [0x24] */
322 /* [0x28] */
324 /* [0x2c] */
326 /* [0x30] */
330 /* [0x0] */
332 /* [0x4] */
334 /* [0x8] */
336 /* [0xc] */
338 /* [0x10] */
340 /* [0x14] */
342 /* [0x18] */
344 /* [0x1c] */
346 /* [0x20] */
348 /* [0x24] */
350 /* [0x28] */
352 /* [0x2c] */
354 /* [0x30] */
360 * [0x0] latch the header in case of any error occur in the core, read
367 * [0x0] latch the header in case of any error occure in the core, read
374 * [0x0] Interrupt Cause Register
381 * Write-0 clears a bit. Write-1 has no effect.
391 * [0x8] Interrupt Cause Set Register
393 * enabling software to generate a hardware interrupt. Write 0 has no
399 * [0x10] Interrupt Mask Register
407 * [0x18] Interrupt Mask Clear Register
410 * with 1 (old value) that hardware has just cleared to 0.
411 * Write 0 to this register clears its corresponding mask bit. Write 1
417 * [0x20] Interrupt Status Register
422 /* [0x28] Interrupt Control Register */
426 * [0x30] Interrupt Mask Register
437 * [0x38] Interrupt Log Register
450 struct al_pcie_rev1_w_global_ctrl global_ctrl; /* [0x0] */
452 struct al_pcie_revx_w_debug debug; /* [0x80] */
453 struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */
455 struct al_pcie_rev1_w_soc_int soc_int; /* [0x200] */
456 struct al_pcie_revx_w_link_down link_down; /* [0x228] */
457 struct al_pcie_revx_w_cntl_gen ctrl_gen; /* [0x230] */
458 struct al_pcie_revx_w_parity parity; /* [0x234] */
459 struct al_pcie_revx_w_last_wr last_wr; /* [0x23c] */
460 struct al_pcie_rev1_2_w_atu atu; /* [0x240] */
462 struct al_pcie_revx_w_int_grp int_grp_a_m0; /* [0x300] */
463 struct al_pcie_revx_w_int_grp int_grp_b_m0; /* [0x340] */
465 struct al_pcie_revx_w_int_grp int_grp_a; /* [0x400] */
466 struct al_pcie_revx_w_int_grp int_grp_b; /* [0x440] */
470 struct al_pcie_rev2_w_global_ctrl global_ctrl; /* [0x0] */
472 struct al_pcie_revx_w_debug debug; /* [0x80] */
473 struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */
474 struct al_pcie_revx_w_ap_user_send_msg ap_user_send_msg; /* [0xa8] */
476 struct al_pcie_rev2_w_soc_int soc_int; /* [0x100] */
478 struct al_pcie_revx_w_link_down link_down; /* [0x228] */
479 struct al_pcie_revx_w_cntl_gen ctrl_gen; /* [0x230] */
480 struct al_pcie_revx_w_parity parity; /* [0x234] */
481 struct al_pcie_revx_w_last_wr last_wr; /* [0x23c] */
482 struct al_pcie_rev1_2_w_atu atu; /* [0x240] */
484 struct al_pcie_revx_w_ap_err ap_err[4]; /* [0x288] */
486 struct al_pcie_revx_w_status_per_func status_per_func; /* [0x300] */
488 struct al_pcie_revx_w_int_grp int_grp_a; /* [0x400] */
489 struct al_pcie_revx_w_int_grp int_grp_b; /* [0x440] */
493 struct al_pcie_rev3_w_global_ctrl global_ctrl; /* [0x0] */
495 struct al_pcie_revx_w_debug debug; /* [0x80] */
496 struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */
497 struct al_pcie_revx_w_ap_user_send_msg ap_user_send_msg; /* [0xa8] */
499 struct al_pcie_revx_w_link_down link_down; /* [0x228] */
500 struct al_pcie_revx_w_cntl_gen ctrl_gen; /* [0x230] */
501 struct al_pcie_revx_w_parity parity; /* [0x234] */
502 struct al_pcie_revx_w_last_wr last_wr; /* [0x23c] */
503 struct al_pcie_rev3_w_atu atu; /* [0x240] */
505 struct al_pcie_rev3_w_cfg_func_ext cfg_func_ext; /* [0x2e0] */
506 struct al_pcie_rev3_w_app_hdr_interface_send app_hdr_interface_send;/* [0x2e4] */
507 struct al_pcie_rev3_w_diag_command diag_command; /* [0x300] */
509 struct al_pcie_rev3_w_soc_int_per_func soc_int_per_func[REV3_MAX_NUM_OF_PFS]; /* [0x310] */
511 struct al_pcie_rev3_w_events_gen_per_func events_gen_per_func[REV3_MAX_NUM_OF_PFS]; /* [0x490] */
513 struct al_pcie_rev3_w_pm_state_per_func pm_state_per_func[REV3_MAX_NUM_OF_PFS];/* [0x4b0] */
515 struct al_pcie_rev3_w_cfg_bars_ovrd cfg_bars_ovrd[REV3_MAX_NUM_OF_PFS]; /* [0x500] */
518 struct al_pcie_revx_w_ap_err ap_err[5]; /* [0xac0] */
520 struct al_pcie_revx_w_status_per_func status_per_func[4]; /* [0xb00] */
522 struct al_pcie_revx_w_int_grp int_grp_a; /* [0x1000] */
523 struct al_pcie_revx_w_int_grp int_grp_b; /* [0x1040] */
524 struct al_pcie_revx_w_int_grp int_grp_c; /* [0x1080] */
525 struct al_pcie_revx_w_int_grp int_grp_d; /* [0x10c0] */
535 #define PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK (1 << 0)
536 #define PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_SHIFT (0)
547 #define PCIE_W_GLOBAL_CTRL_PORT_INIT_DEVICE_TYPE_MASK 0x000000F0
568 #define PCIE_W_GLOBAL_CTRL_PORT_STS_PHY_LINK_UP (1 << 0)
587 #define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_DSTATE_MASK 0x00000380
599 * 0: core_clk is required to be active for the current power state.
608 * D1, D2, or D3 power state. EP mode only. Change the value from 0 to 1 to send
612 #define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME (1 << 0)
613 #define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME_FUNC_MASK 0x000000FF
614 #define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME_FUNC_SHIFT 0
662 #define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_NO_SRIS_MASK 0x000001FF
663 #define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_NO_SRIS_SHIFT 0
665 #define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_MASK 0x0003FE00
668 #define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN21_SRIS_MASK 0x1FFC0000
671 #define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_RSRVD_MASK 0x60000000
678 #define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTD (1 << 0)
683 /* Transmit INT_A Interrupt ControlEvery transition from 0 to 1 ... */
688 #define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_MASK 0x000003E0
699 #define PCIE_W_LCL_LOG_CPL_TO_INFO_TC_MASK 0x00000003
700 #define PCIE_W_LCL_LOG_CPL_TO_INFO_TC_SHIFT 0
702 #define PCIE_W_LCL_LOG_CPL_TO_INFO_FUN_NUM_MASK 0x000000FC
705 #define PCIE_W_LCL_LOG_CPL_TO_INFO_TAG_MASK 0x0000FF00
708 #define PCIE_W_LCL_LOG_CPL_TO_INFO_ATTR_MASK 0x00030000
711 #define PCIE_W_LCL_LOG_CPL_TO_INFO_LEN_MASK 0x3FFC0000
722 #define PCIE_W_LCL_LOG_RCV_MSG0_0_REQ_ID_MASK 0x0000FFFF
723 #define PCIE_W_LCL_LOG_RCV_MSG0_0_REQ_ID_SHIFT 0
732 #define PCIE_W_LCL_LOG_RCV_MSG1_0_REQ_ID_MASK 0x0000FFFF
733 #define PCIE_W_LCL_LOG_RCV_MSG1_0_REQ_ID_SHIFT 0
745 #define PCIE_W_LCL_LOG_CORE_Q_STATUS_CPL_LUT_VALID_MASK 0x0000FFFF
746 #define PCIE_W_LCL_LOG_CORE_Q_STATUS_CPL_LUT_VALID_SHIFT 0
749 #define PCIE_W_LCL_LOG_CPL_TO_REQID_MASK 0x0000FFFF
750 #define PCIE_W_LCL_LOG_CPL_TO_REQID_SHIFT 0
754 #define PCIE_W_DEBUG_INFO_0_PM_CURRENT_STATE_MASK 0x00000007
755 #define PCIE_W_DEBUG_INFO_0_PM_CURRENT_STATE_SHIFT 0
757 #define PCIE_W_DEBUG_INFO_0_LTSSM_STATE_MASK 0x000001F8
762 #define PCIE_W_DEBUG_INFO_0_CXPL_DEBUG_INFO_EI_MASK 0x03FFFC00
767 #define PCIE_W_OB_VEN_MSG_CONTROL_REQ (1 << 0)
771 #define PCIE_W_OB_VEN_MSG_PARAM_1_FMT_MASK 0x00000003
772 #define PCIE_W_OB_VEN_MSG_PARAM_1_FMT_SHIFT 0
774 #define PCIE_W_OB_VEN_MSG_PARAM_1_TYPE_MASK 0x0000007C
777 #define PCIE_W_OB_VEN_MSG_PARAM_1_TC_MASK 0x00000380
784 #define PCIE_W_OB_VEN_MSG_PARAM_1_ATTR_MASK 0x00003000
787 #define PCIE_W_OB_VEN_MSG_PARAM_1_LEN_MASK 0x00FFC000
790 #define PCIE_W_OB_VEN_MSG_PARAM_1_TAG_MASK 0xFF000000
795 #define PCIE_W_OB_VEN_MSG_PARAM_2_REQ_ID_MASK 0x0000FFFF
796 #define PCIE_W_OB_VEN_MSG_PARAM_2_REQ_ID_SHIFT 0
798 #define PCIE_W_OB_VEN_MSG_PARAM_2_CODE_MASK 0x00FF0000
801 #define PCIE_W_OB_VEN_MSG_PARAM_2_RSVD_31_24_MASK 0xFF000000
806 #define PCIE_W_AP_USER_SEND_MSG_ACK_INFO_ACK (1 << 0)
814 #define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_MASK 0x0000FFFF
815 #define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_SHIFT 0
817 #define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_MASK 0xFFFF0000
825 #define PCIE_W_CFG_FUNC_EXT_CFG_CFG_TPH_REQ_EN_MASK 0x000000FF
826 #define PCIE_W_CFG_FUNC_EXT_CFG_CFG_TPH_REQ_EN_SHIFT 0
832 #define PCIE_W_CFG_FUNC_EXT_CFG_RSRVD_MASK 0xFFFFFE00
841 * regardless of the value this bus. Function numbering starts at '0'.
843 #define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_APP_ERR_FUNC_NUM_MASK 0x0000FFFF
844 #define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_APP_ERR_FUNC_NUM_SHIFT 0
871 #define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_RSRVD_MASK 0xFFFE0000
878 #define PCIE_W_APP_HDR_INTERFACE_SEND_APP_HDR_CMD_APP_HDR_VALID (1 << 0)
882 #define PCIE_W_APP_HDR_INTERFACE_SEND_APP_HDR_CMD_RSRVD_MASK 0xFFFFFFFE
890 #define PCIE_W_DIAG_COMMAND_DIAG_CTRL_DIAG_CTRL_BUS_MASK 0x00000007
891 #define PCIE_W_DIAG_COMMAND_DIAG_CTRL_DIAG_CTRL_BUS_SHIFT 0
895 #define PCIE_W_DIAG_COMMAND_DIAG_CTRL_RSRVD_MASK 0xFFFFFFF8
901 #define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTD (1 << 0)
908 * Every transition from 0 to 1 schedules an Assert_ INT interrupt message for
910 * Every transition from 1 to 0, schedules a Deassert_INT interrupt message for
920 #define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_MASK 0x000003E0
924 * from 0 to 1 to send hot reset. Only func 0 is supported.
928 * The application request unlock message to be sent. Change the value from 0 to
929 * 1 to send the message. Only func 0 is supported.
947 #define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_DSTATE_MASK 0x0000000F
948 #define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_DSTATE_SHIFT 0
977 #define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_EN_MASK 0x00000003
978 #define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_EN_SHIFT 0
980 #define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_IO_MASK 0x0000000C
983 #define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_RSRVS_MASK 0xFFFFFFF0
988 #define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_EN_MASK 0x00000003
989 #define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_EN_SHIFT 0
991 #define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_IO_MASK 0x0000000C
994 #define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_RSRVS_MASK 0xFFFFFFF0
999 #define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_EN_MASK 0x00000003
1000 #define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_EN_SHIFT 0
1002 #define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_IO_MASK 0x0000000C
1005 #define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_RSRVS_MASK 0xFFFFFFF0
1010 #define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_EN_MASK 0x00000003
1011 #define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_EN_SHIFT 0
1013 #define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_IO_MASK 0x0000000C
1016 #define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_RSRVS_MASK 0xFFFFFFF0
1021 #define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_EN_MASK 0x00000003
1022 #define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_EN_SHIFT 0
1024 #define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_IO_MASK 0x0000000C
1027 #define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_RSRVS_MASK 0xFFFFFFF0
1032 #define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_EN_MASK 0x00000003
1033 #define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_EN_SHIFT 0
1035 #define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_IO_MASK 0x0000000C
1038 #define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_RSRVS_MASK 0xFFFFFFF0
1043 #define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTD (1 << 0)
1112 * - INTx Assertion Disable bit in the Command register is 0.
1132 * - Any bit in the Slot Status register transitions from 0 to 1 and the
1139 * - INTx Assertion Disable bit in the Command register is 0.
1155 * - Any bit in the Slot Status register transitions from 0 to 1 and the
1192 #define PCIE_W_INT_GRP_A_CONTROL_A_CLEAR_ON_READ (1 << 0)
1208 * Interrupt Status = 0.
1209 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
1215 * cause bits are cleared to 0, enabling immediate interrupt assertion if any
1226 #define PCIE_W_INT_GRP_A_CONTROL_A_AWID_MASK 0x00000F00
1232 #define PCIE_W_INT_GRP_A_CONTROL_A_MOD_INTV_MASK 0x00FF0000
1236 * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
1240 #define PCIE_W_INT_GRP_A_CONTROL_A_MOD_RES_MASK 0x0F000000
1245 #define PCIE_W_INT_GRP_B_CAUSE_B_MSG_PM_PME (1 << 0)
1310 #define PCIE_W_INT_GRP_B_CONTROL_B_CLEAR_ON_READ (1 << 0)
1326 * Interrupt Status = 0.
1327 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
1333 * cause bits are cleared to 0, enabling an immediate interrupt assertion if any
1344 #define PCIE_W_INT_GRP_B_CONTROL_B_AWID_MASK 0x00000F00
1350 #define PCIE_W_INT_GRP_B_CONTROL_B_MOD_INTV_MASK 0x00FF0000
1354 * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
1358 #define PCIE_W_INT_GRP_B_CONTROL_B_MOD_RES_MASK 0x0F000000
1363 #define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_VPD_INT_FUNC_MASK 0x0000000F
1364 #define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_VPD_INT_FUNC_SHIFT 0
1366 #define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_FLR_PF_ACTIVE_MASK 0x000000F0
1369 #define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_SYS_ERR_RC_MASK 0x00000F00
1372 #define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_INT_MASK 0x0000F000
1375 #define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_MSI_MASK 0x000F0000
1378 #define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_MSI_MASK 0x00F00000
1381 #define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_INT_MASK 0x0F000000
1394 #define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_CLEAR_ON_READ (1 << 0)
1410 * Interrupt Status = 0.
1411 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
1417 * cause bits are cleared to 0, enabling immediate interrupt assertion if any
1428 #define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AWID_MASK 0x00000F00
1434 #define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_INTV_MASK 0x00FF0000
1438 * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
1442 #define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_RES_MASK 0x0F000000
1447 #define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_CLEAR_ON_READ (1 << 0)
1463 * Interrupt Status = 0.
1464 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
1470 * cause bits are cleared to 0, enabling immediate interrupt assertion if any
1481 #define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AWID_MASK 0x00000F00
1487 #define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_INTV_MASK 0x00FF0000
1491 * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
1495 #define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_RES_MASK 0x0F000000