Lines Matching +full:iatu +full:- +full:capable
1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
65 /** Number of outbound atu regions - rev 1/2 */
67 /** Number of outbound atu regions - rev 3 */
80 uint32_t rsrvd[(0x270 - 0x224) >> 2];
85 uint32_t reserved1[(0x10 - 0x4) >> 2];
87 uint32_t reserved2[(0x18 - 0x14) >> 2];
90 uint32_t reserved3[(0x48 - 0x20) >> 2];
94 uint32_t reserved4[(0x10C - 0x54) >> 2];
96 uint32_t reserved5[(0x190 - 0x110) >> 2];
104 uint32_t reserved7[(0x1B8 - 0x1AC) >> 2];
107 uint32_t reserved8[(0x1D0 - 0x1C0) >> 2];
109 uint32_t reserved9[(0x200 - 0x1D4) >> 2];
110 struct al_pcie_core_iatu_regs iatu; member
111 uint32_t reserved10[(0x448 - 0x270) >> 2];
115 /* 0x0 - PCI Express Extended Capability Header */
117 /* 0x4 - Uncorrectable Error Status Register */
119 /* 0x8 - Uncorrectable Error Mask Register */
121 /* 0xc - Uncorrectable Error Severity Register */
123 /* 0x10 - Correctable Error Status Register */
125 /* 0x14 - Correctable Error Mask Register */
127 /* 0x18 - Advanced Error Capabilities and Control Register */
129 /* 0x1c - Header Log Registers */
131 /* 0x2c - Root Error Command Register */
133 /* 0x30 - Root Error Status Register */
135 /* 0x34 - Error Source Identification Register */
142 uint32_t reserved1[(0x70 - 0x44) >> 2];
147 uint32_t reserved2[(0xB0 - 0x80) >> 2];
149 uint32_t reserved3[(0x100 - 0xB4) >> 2];
151 uint32_t reserved4[(0x150 -
155 uint32_t reserved5[(0x700 - 0x154) >> 2];
157 uint32_t reserved6[(0x1000 -
165 uint32_t reserved1[(0x70 - 0x44) >> 2];
170 uint32_t reserved2[(0xB0 - 0x80) >> 2];
172 uint32_t reserved3[(0x100 - 0xB4) >> 2];
174 uint32_t reserved4[(0x158 -
179 uint32_t reserved5[(0x178 - 0x15C) >> 2];
182 uint32_t reserved6[(0x700 - 0x17C) >> 2];
185 uint32_t reserved7[(0x1000 -
213 uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET -
217 uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET -
225 uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET -
229 uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET -
237 uint32_t reserved1[(AL_PCIE_REV_3_APP_REGS_OFFSET -
241 uint32_t reserved2[(AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET -
478 /**** iATU, Control Register 1 ****/
481 * When the Address and BAR matching logic in the core indicate that a MEM-I/O
484 * Number Match Enable" bit of the "iATU Control 2 Register" is set
489 /**** iATU, Control Register 2 ****/
532 /* ECRC Check Capable */
539 /* Non-Fatal Error Reporting Enable */
554 /* Non-Fatal Error Messages Received */