Lines Matching +full:write +full:- +full:only

1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
50  *  Only 2 interrupts go from the pcie unit to the GIC:
52  *  2. INTA assert/deassert (RC only).
67 	AL_PCIE_INT_GRP_C, /* Rev3 only */
68 	AL_PCIE_INT_GRP_D, /* Rev3 only */
73  * App group A interrupts mask - don't change
77 	/** [RC only] Deassert_INTD received */
79 	/** [RC only] Deassert_INTC received */
81 	/** [RC only] Deassert_INTB received */
84 	 * [RC only] Deassert_INTA received - there's a dedicated GIC interrupt
88 	/** [RC only] Assert_INTD received */
90 	/** [RC only] Assert_INTC received */
92 	/** [RC only] Assert_INTB received */
95 	 * [RC only] Assert_INTA received - there's a dedicated GIC interrupt
99 	/** [RC only] MSI Controller Interrupt */
101 	/** [EP only] MSI sent grant */
103 	/** [RC only] System error detected  (ERR_COR, ERR_FATAL, ERR_NONFATAL) */
105 	/** [EP only] Software initiates FLR on a Physical Function */
107 	/** [RC only] Root Error Command register assertion notification */
109 	/** [RC only] Root Error Command register assertion notification With MSI or MSIX enabled */
111 	/** [RC only] PME Status bit assertion in the Root Status register With INTA */
113 	/** [RC only] PME Status bit assertion in the Root Status register With MSI or MSIX enabled */
117 	/** [EP only] When the EP gets a command to shut down, signal the software to block any new TLP. */
126 	 * [RC/EP] CFG write transaction to the configuration space by the RC peer
127 	 * For RC the int/ will be set from DBI write (internal SoC write)]
130 	/** [EP only] CFG access in EP mode */
135  * App group B interrupts mask - don't change
139 	/** [RC only] PM_PME Message received */
141 	/** [RC only] PME_TO_Ack Message received */
143 	/** [EP only] PME_Turn_Off Message received */
145 	/** [RC only] ERR_CORR Message received */
147 	/** [RC only] ERR_NONFATAL Message received */
149 	/** [RC only] ERR_FATAL Message received */
154 	 * messages only, and latch the headers in registers
160 	 * messages only, and latch the headers in registers
163 	/** [EP only] Link Autonomous Bandwidth Status is updated */
165 	/** [EP only] Link Equalization Request bit in the Link Status 2 Register has been set */
169 	/** [RC only] CPL timeout from the PCIe core indication */
175 	/** [EP only] Speed change request */
180  * AXI interrupts mask - don't change
196 	/** [RC/EP] PARITY ERROR on the slave addr write channel */
198 	/** [RC/EP] PARITY ERROR on the slave data write channel */
200 	/** [RC only] Software error: ECAM write request with invalid bus number */
202 	/** [RC only] Software error: ECAM read request with invalid bus number */
206 	/** [RC/EP] Write AXI completion has ERROR */
210 	/** [RC/EP] Write AXI completion has timed out */