Lines Matching full:ep

101 	/** [EP only] MSI sent grant */
105 	/** [EP only] Software initiates FLR on a Physical Function */
115 	/** [RC/EP] The core assert link down event, whenever the link is going down */
117 	/** [EP only] When the EP gets a command to shut down, signal the software to block any new TLP. */
119 	/** [RC/EP] PHY/MAC link up */
121 	/** [RC/EP] Data link up */
123 	/** [RC/EP] The LTSSM is in RCVRY_LOCK state. */
126 	 * [RC/EP] CFG write transaction to the configuration space by the RC peer
130 	/** [EP only] CFG access in EP mode */
143 	/** [EP only] PME_Turn_Off Message received */
152 	 * [RC/EP] Vendor Defined Message received
158 	 * [RC/EP] Vendor Defined Message received
163 	/** [EP only] Link Autonomous Bandwidth Status is updated */
165 	/** [EP only] Link Equalization Request bit in the Link Status 2 Register has been set */
167 	/** [RC/EP] OB Vendor message request is granted by the PCIe core */
171 	/** [RC/EP] Slave Response Composer Lookup Error */
173 	/** [RC/EP] Parity Error */
175 	/** [EP only] Speed change request */
190 	/** [RC/EP] Master Response Composer Lookup Error */
192 	/** [RC/EP] PARITY ERROR on the master data read channel */
194 	/** [RC/EP] PARITY ERROR on the slave addr read channel */
196 	/** [RC/EP] PARITY ERROR on the slave addr write channel */
198 	/** [RC/EP] PARITY ERROR on the slave data write channel */
204 	/** [RC/EP] Read AXI completion has ERROR */
206 	/** [RC/EP] Write AXI completion has ERROR */
208 	/** [RC/EP] Read AXI completion has timed out */
210 	/** [RC/EP] Write AXI completion has timed out */
212 	/** [RC/EP] Parity error AXI domain */
214 	/** [RC/EP] POS error interrupt */