Lines Matching +full:0 +full:x0000003c
53 /* [0x0] */
56 /* [0x8] */
58 /* [0xc] */
60 /* [0x10] */
62 /* [0x14] */
64 /* [0x18] */
66 /* [0x1c] */
68 /* [0x20] */
70 /* [0x24] */
72 /* [0x28] */
74 /* [0x2c] */
79 /* [0x0] */
82 /* [0x8] */
84 /* [0xc] */
86 /* [0x10] */
88 /* [0x14] */
90 /* [0x18] */
92 /* [0x1c] */
94 /* [0x20] */
96 /* [0x24] */
98 /* [0x28] */
100 /* [0x2c] */
104 /* [0x0] */
106 /* [0x4] */
108 /* [0x8] */
110 /* [0xc] */
112 /* [0x10] */
114 /* [0x14] */
116 /* [0x18] */
118 /* [0x1c] */
120 /* [0x20] */
122 /* [0x24] */
127 /* [0x0] */
129 /* [0x4] */
131 /* [0x8] */
133 /* [0xc] */
135 /* [0x10] */
137 /* [0x14] */
139 /* [0x18] */
141 /* [0x1c] */
143 /* [0x20] */
145 /* [0x24] */
148 * [0x28] this register override the Target-ID field in the AXUSER [19:4],
152 /* [0x2c] this register override the ADDR[63:32] AXI master port. */
154 /* [0x30] this register override the ADDR[63:32] AXI master port. */
157 * [0x34] Define the size to replace in the master axi address bits
164 /* [0x0] */
166 /* [0x4] */
168 /* [0x8] */
170 /* [0xc] */
172 /* [0x10] */
174 /* [0x14] */
176 /* [0x18] */
178 /* [0x1c] */
180 /* [0x20] */
182 /* [0x24] */
184 /* [0x28] */
186 /* [0x2c] */
188 /* [0x30] */
190 /* [0x34] */
192 /* [0x38] */
194 /* [0x3c] */
196 /* [0x40] */
199 * [0x44] this register override the Target-ID field in the AXUSER [19:4],
203 /* [0x48] this register override the ADDR[63:32] AXI master port. */
205 /* [0x4c] this register override the ADDR[63:32] AXI master port. */
208 * [0x50] Define the size to replace in the master axi address bits
215 /* [0x0] */
217 /* [0x4] */
219 /* [0x8] */
223 /* [0x0] */
227 /* [0x0] */
229 /* [0x4] */
233 /* [0x0] */
235 /* [0x4] */
239 /* [0x0] */
241 /* [0x4] */
245 /* [0x0] */
247 /* [0x4] */
251 /* [0x0] */
253 /* [0x4] */
257 /* [0x0] */
261 /* [0x0] */
263 /* [0x4] */
265 /* [0x8] */
267 /* [0xc] */
271 /* [0x0] */
273 /* [0x4] */
275 /* [0x8] */
277 /* [0xc] */
279 /* [0x10] */
281 /* [0x14] */
283 /* [0x18] */
285 /* [0x1c] */
290 /* [0x0] */
292 /* [0x4] */
294 /* [0x8] */
296 /* [0xc] */
298 /* [0x10] */
300 /* [0x14] */
302 /* [0x18] */
304 /* [0x1c] */
308 /* [0x0] */
310 /* [0x4] */
312 /* [0x8] */
314 /* [0xc] */
316 /* [0x10] */
318 /* [0x14] */
320 /* [0x18] */
322 /* [0x1c] */
324 /* [0x20] */
326 /* [0x24] */
328 /* [0x28] */
330 /* [0x2c] */
332 /* [0x30] */
334 /* [0x34] */
336 /* [0x38] */
338 /* [0x3c] */
344 /* [0x0] 4 option, the index comes from */
349 /* [0x0] */
351 /* [0x4] */
355 /* [0x0] */
357 /* [0x4] */
361 /* [0x0] */
365 /* [0x0] */
369 /* [0x0] */
375 * [0x0] The sum of all the fields below must be 97
377 * [0x0] The sum of all the fields below must be 259
383 * [0x0] Interrupt Cause Register
390 * Write-0 clears a bit. Write-1 has no effect.
400 * [0x8] Interrupt Cause Set Register
402 * enabling software to generate a hardware interrupt. Write 0 has no
408 * [0x10] Interrupt Mask Register
416 * [0x18] Interrupt Mask Clear Register
419 * another bit with 1 (old value) that hardware has just cleared to 0.
420 * Writing 0 to this register clears its corresponding mask bit. Write 1
426 * [0x20] Interrupt Status Register
431 /* [0x28] Interrupt Control Register */
435 * [0x30] Interrupt Mask Register
446 * [0x38] Interrupt Log Register
459 /* [0x0] */
461 /* [0x4] */
463 /* [0x8] */
465 /* [0xc] */
467 /* [0x10] */
469 /* [0x14] */
471 /* [0x18] */
473 /* [0x1c] */
475 /* [0x20] */
477 /* [0x24] */
479 /* [0x28] */
481 /* [0x2c] */
486 /* [0x0] */
488 /* [0x4] */
490 /* [0x8] */
494 /* [0x0] */
498 /* [0x0] */
500 /* [0x4] */
502 /* [0x8] */
504 /* [0xc] */
506 /* [0x10] */
508 /* [0x14] */
510 /* [0x18] */
515 /* [0x0] */
520 * [0x0] In case of hit on the io message bar and
525 /* [0x4] in case of message this register set the below attributes */
528 * [0x8] In case of hit on the io message bar and
533 /* [0xc] in case of message this register set the below attributes */
535 /* [0x10] in case of message this register set the below attributes */
541 * [0x0] In case of hit on the io message bar and
546 /* [0x4] in case of message this register set the below attributes */
549 * [0x8] In case of hit on the io message bar and
555 * [0xc] In case of hit on the io message bar and
561 * [0x10] In case of hit on the io message bar and
567 * [0x14] In case of hit on the io message bar and
573 * [0x18] In case of hit on the io message bar and
579 * [0x1c] In case of hit on the io message bar and
585 * [0x20] In case of hit on the io message bar and
591 * [0x24] In case of hit on the io message bar and
601 struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
605 struct al_pcie_rev1_2_axi_ctrl ctrl; /* [0x0] */
606 struct al_pcie_rev1_axi_ob_ctrl ob_ctrl; /* [0x40] */
608 struct al_pcie_revx_axi_msg msg; /* [0x90] */
609 struct al_pcie_revx_axi_pcie_status pcie_status; /* [0x9c] */
610 struct al_pcie_revx_axi_rd_parity rd_parity; /* [0xa0] */
611 struct al_pcie_revx_axi_rd_cmpl rd_cmpl; /* [0xa8] */
612 struct al_pcie_revx_axi_rd_to rd_to; /* [0xb0] */
613 struct al_pcie_revx_axi_wr_cmpl wr_cmpl; /* [0xb8] */
614 struct al_pcie_revx_axi_wr_to wr_to; /* [0xc0] */
615 struct al_pcie_revx_axi_pcie_global pcie_global; /* [0xc8] */
616 struct al_pcie_rev1_2_axi_status status; /* [0xcc] */
617 struct al_pcie_rev1_2_axi_conf conf; /* [0xdc] */
618 struct al_pcie_revx_axi_parity parity; /* [0xfc] */
619 struct al_pcie_revx_axi_pos_logged pos_logged; /* [0x104] */
620 struct al_pcie_revx_axi_ordering ordering; /* [0x10c] */
621 struct al_pcie_revx_axi_link_down link_down; /* [0x110] */
622 struct al_pcie_revx_axi_pre_configuration pre_configuration; /* [0x114] */
623 struct al_pcie_revx_axi_init_fc init_fc; /* [0x118] */
625 struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
627 struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x200] */
631 struct al_pcie_rev1_2_axi_ctrl ctrl; /* [0x0] */
632 struct al_pcie_rev2_axi_ob_ctrl ob_ctrl; /* [0x40] */
634 struct al_pcie_revx_axi_msg msg; /* [0x90] */
635 struct al_pcie_revx_axi_pcie_status pcie_status; /* [0x9c] */
636 struct al_pcie_revx_axi_rd_parity rd_parity; /* [0xa0] */
637 struct al_pcie_revx_axi_rd_cmpl rd_cmpl; /* [0xa8] */
638 struct al_pcie_revx_axi_rd_to rd_to; /* [0xb0] */
639 struct al_pcie_revx_axi_wr_cmpl wr_cmpl; /* [0xb8] */
640 struct al_pcie_revx_axi_wr_to wr_to; /* [0xc0] */
641 struct al_pcie_revx_axi_pcie_global pcie_global; /* [0xc8] */
642 struct al_pcie_rev1_2_axi_status status; /* [0xcc] */
643 struct al_pcie_rev1_2_axi_conf conf; /* [0xdc] */
644 struct al_pcie_revx_axi_parity parity; /* [0xfc] */
645 struct al_pcie_revx_axi_pos_logged pos_logged; /* [0x104] */
646 struct al_pcie_revx_axi_ordering ordering; /* [0x10c] */
647 struct al_pcie_revx_axi_link_down link_down; /* [0x110] */
648 struct al_pcie_revx_axi_pre_configuration pre_configuration; /* [0x114] */
649 struct al_pcie_revx_axi_init_fc init_fc; /* [0x118] */
651 struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
653 struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x200] */
657 struct al_pcie_rev3_axi_ctrl ctrl; /* [0x0] */
658 struct al_pcie_rev3_axi_ob_ctrl ob_ctrl;/* [0x30] */
659 struct al_pcie_revx_axi_msg msg; /* [0x90] */
660 struct al_pcie_revx_axi_pcie_status pcie_status; /* [0x9c] */
661 struct al_pcie_revx_axi_rd_parity rd_parity; /* [0xa0] */
662 struct al_pcie_revx_axi_rd_cmpl rd_cmpl; /* [0xa8] */
663 struct al_pcie_revx_axi_rd_to rd_to; /* [0xb0] */
664 struct al_pcie_revx_axi_wr_cmpl wr_cmpl; /* [0xb8] */
665 struct al_pcie_revx_axi_wr_to wr_to; /* [0xc0] */
666 struct al_pcie_revx_axi_pcie_global pcie_global; /* [0xc8] */
668 struct al_pcie_revx_axi_parity parity; /* [0xd0] */
669 struct al_pcie_revx_axi_pos_logged pos_logged; /* [0xd8] */
670 struct al_pcie_revx_axi_ordering ordering; /* [0xe0] */
671 struct al_pcie_revx_axi_link_down link_down; /* [0xe4] */
672 struct al_pcie_revx_axi_pre_configuration pre_configuration;/* [0xe8] */
673 struct al_pcie_revx_axi_init_fc init_fc; /* [0xec] */
675 struct al_pcie_rev3_axi_eq_ovrd_tx_rx_values eq_ovrd_tx_rx_values;/* [0x100] */
676 struct al_pcie_rev3_axi_dbg_outstading_trans_axi dbg_outstading_trans_axi;/* [0x160] */
677 struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
678 struct al_pcie_revx_axi_power_mang_ovrd_cntl power_mang_ovrd_cntl;/* [0x170] */
679 struct al_pcie_rev3_axi_dbg_outstading_trans_axi_write dbg_outstading_trans_axi_write;/* [0x190] */
681 struct al_pcie_rev3_axi_attr_ovrd axi_attr_ovrd; /* [0x1a0] */
682 struct al_pcie_rev3_axi_pf_axi_attr_ovrd pf_axi_attr_ovrd[REV3_MAX_NUM_OF_PFS];/* [0x1c0] */
684 struct al_pcie_rev3_axi_status status; /* [0x3c0] */
685 struct al_pcie_rev3_axi_conf conf; /* [0x400] */
687 struct al_pcie_revx_axi_msg_attr_axuser_table msg_attr_axuser_table; /* [0x500] */
689 struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x800] */
699 #define PCIE_AXI_DEVICE_ID_REG_DEV_ID_X4 (0 << PCIE_AXI_DEVICE_ID_REG_DEV_ID_SHIFT)
701 #define PCIE_AXI_DEVICE_ID_REG_REV_ID_MASK AL_FIELD_MASK(15, 0)
702 #define PCIE_AXI_DEVICE_ID_REG_REV_ID_SHIFT 0
709 #define PCIE_AXI_CTRL_GLOBAL_CPL_AFTER_P_ORDER_DIS (1 << 0)
728 #define PCIE_REV3_AXI_CTRL_GLOBAL_MEM_BAR_MAP_TO_ERR_MASK 0x00000FF0
777 #define PCIE_AXI_CTRL_MASTER_ARCTL_OVR_ARCACHE (1 << 0)
779 #define PCIE_AXI_CTRL_MASTER_ARCTL_ARACHE_VA_MASK 0x0000001E
784 #define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_VALUE_MASK 0x000001C0
787 #define PCIE_AXI_CTRL_MASTER_ARCTL_TGTID_VAL_MASK 0x01FFFE00
798 #define PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_MASK 0xF0000000
804 #define PCIE_AXI_CTRL_MASTER_AWCTL_OVR_ARCACHE (1 << 0)
806 #define PCIE_AXI_CTRL_MASTER_AWCTL_AWACHE_VA_MASK 0x0000001E
811 #define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_VALUE_MASK 0x000001C0
814 #define PCIE_AXI_CTRL_MASTER_AWCTL_TGTID_VAL_MASK 0x01FFFE00
825 #define PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_MASK 0xF0000000
835 * If set to 0, take the bit from the ECAM bar, otherwise from the busnum of
839 #define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK 0x000000FF
840 #define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_SHIFT 0
842 #define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_MASK 0x0000FF00
847 #define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_PBUS_MASK 0x000000FF
848 #define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_PBUS_SHIFT 0
853 #define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SUBBUS_MASK 0x0000FF00
856 #define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SEC_BUS_MASK 0x00FF0000
866 #define PCIE_AXI_MISC_OB_CTRL_IO_START_H_ADDR_MASK 0x000003FF
867 #define PCIE_AXI_MISC_OB_CTRL_IO_START_H_ADDR_SHIFT 0
874 #define PCIE_AXI_MISC_OB_CTRL_IO_LIMIT_H_ADDR_MASK 0x000003FF
875 #define PCIE_AXI_MISC_OB_CTRL_IO_LIMIT_H_ADDR_SHIFT 0
882 #define PCIE_AXI_MISC_OB_CTRL_MSG_START_H_ADDR_MASK 0x000003FF
883 #define PCIE_AXI_MISC_OB_CTRL_MSG_START_H_ADDR_SHIFT 0
890 #define PCIE_AXI_MISC_OB_CTRL_MSG_LIMIT_H_ADDR_MASK 0x000003FF
891 #define PCIE_AXI_MISC_OB_CTRL_MSG_LIMIT_H_ADDR_SHIFT 0
899 #define PCIE_AXI_MISC_OB_CTRL_TGTID_REG_OVRD_SEL_MASK 0x0000FFFF
900 #define PCIE_AXI_MISC_OB_CTRL_TGTID_REG_OVRD_SEL_SHIFT 0
902 #define PCIE_AXI_MISC_OB_CTRL_TGTID_REG_OVRD_VALUE_MASK 0xFFFF0000
910 #define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_VALUE_MASK 0x0000FFFF
911 #define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_VALUE_SHIFT 0
913 #define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_RSRVD_MASK 0xFFFF0000
918 #define PCIE_AXI_MISC_MSG_TYPE_TYPE_MASK 0x00FFFFFF
919 #define PCIE_AXI_MISC_MSG_TYPE_TYPE_SHIFT 0
921 #define PCIE_AXI_MISC_MSG_TYPE_RSRVD_MASK 0xFF000000
926 #define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_AXI_BRIDGE_RESET (1 << 0)
943 #define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_RSRVD_MASK 0xFFFFFFE0
962 #define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK 0x0000000F
963 #define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_SHIFT 0
969 #define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK 0x000000F0
970 #define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_MASK 0xFFFFFF00
973 #define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK 0x000FFFF0
974 #define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_MASK 0xFFF00000
977 #define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN 0x100
978 #define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN 0x100000
982 #define PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_MASK AL_FIELD_MASK(2, 0)
983 #define PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_SHIFT 0
987 #define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_MASK 0x0000003f
988 #define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_SHIFT 0
990 #define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_MASK 0x00000fc0
999 #define PCIE_AXI_POS_ORDER_AXI_POS_BYPASS (1 << 0)
1050 #define PCIE_AXI_CORE_SETUP_DELAY_MAC_PHY_RATE_MASK 0x000000FF
1051 #define PCIE_AXI_CORE_SETUP_DELAY_MAC_PHY_RATE_SHIFT 0
1056 #define PCIE_AXI_CORE_SETUP_NOF_READS_ONSLAVE_INTRF_PCIE_CORE_MASK 0x0000FF00
1063 #define PCIE_AXI_REV3_CORE_SETUP_CFG_DELAY_AFTER_PCIE_EXIST_MASK 0x0FFE0000
1068 #define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_MASK 0x0000007F
1069 #define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_SHIFT 0
1071 #define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_NP_HDR_MASK 0x00003F80
1074 #define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_CPL_HDR_MASK 0x001FC000
1077 #define PCIE_AXI_REV1_2_INIT_FC_CFG_RSRVD_MASK 0xFFE00000
1081 #define PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_MASK 0x000001FF
1082 #define PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_SHIFT 0
1084 #define PCIE_AXI_REV3_INIT_FC_CFG_NOF_NP_HDR_MASK 0x0003FE00
1087 #define PCIE_AXI_REV3_INIT_FC_CFG_NOF_CPL_HDR_MASK 0x07FC0000
1095 #define PCIE_AXI_REV3_INIT_FC_CFG_RSRVD_MASK 0xF8000000
1103 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_OUTBOUND_MSG_NO_SNOOP_N (1 << 0)
1107 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_DATA_MASK 0x000003FC
1110 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_MASK 0x0003FC00
1113 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_ST_MASK 0x03FC0000
1120 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_PH_MASK 0x30000000
1123 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_RSRVD_MASK 0xC0000000
1128 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MISC_MSG_TYPE_VALUE_MASK 0x0000001F
1129 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MISC_MSG_TYPE_VALUE_SHIFT 0
1131 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_TYPE_VALUE_MASK 0x000003E0
1136 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_NO_DATA_AXI_SIZE_MSG_MASK 0x00003800
1141 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_AXI_SIZE_MSG_MASK 0x00038000
1144 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_RSRVD_MASK 0xFFFC0000
1152 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_OUTBOUND_MSG_NO_SNOOP_N (1 << 0)
1156 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_DATA_MASK 0x000003FC
1159 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_MASK 0x0003FC00
1162 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_ST_MASK 0x03FC0000
1169 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_PH_MASK 0x30000000
1172 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_RSRVD_MASK 0xC0000000
1177 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MISC_MSG_TYPE_VALUE_MASK 0x0000001F
1178 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MISC_MSG_TYPE_VALUE_SHIFT 0
1180 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_TYPE_VALUE_MASK 0x000003E0
1185 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_NO_DATA_AXI_SIZE_MSG_MASK 0x00003800
1190 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_AXI_SIZE_MSG_MASK 0x00038000
1193 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_RSRVD_MASK 0xFFFC0000
1198 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_AXUSER (1 << 0)
1202 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_ADDR_OFFSET_MASK 0x0000003C
1213 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_ADDR_OFFSET_MASK 0x00003C00
1218 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_RSRVD_MASK 0xFFFF8000
1223 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_OVRD_FROM_AXUSER (1 << 0)
1227 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_ADDR_OFFSET_MASK 0x0000003C
1232 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_AXUSER_MASK 0x00007F80
1235 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_REG_MASK 0x007F8000
1238 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_CFG_ST_VEC_OVRD_MASK 0x7F800000
1245 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_MASK 0x00000003
1246 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_SHIFT 0
1248 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_REG_MASK 0x0000000C
1251 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_ADDR_OFFSET_MASK 0x00000FF0
1254 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_PH_VEC_OVRD_MASK 0x00003000
1257 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_14_15_MASK 0x0000C000
1260 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_OVRD_FROM_AXUSER_MASK 0x00030000
1263 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_OVRD_FROM_REG_MASK 0x000C0000
1266 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_ADDR_OFFSET_MASK 0x0FF00000
1269 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_TGTID89_VEC_OVRD_MASK 0x30000000
1272 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_MASK 0xC0000000
1280 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_SEL_MASK 0x000003FF
1281 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_SEL_SHIFT 0
1283 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_OVRD_MASK 0x000FFC00
1289 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR54_63_SEL_MASK 0x3FF00000
1292 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_RSRVD_MASK 0xC0000000
1297 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_MASK 0x000003FF
1298 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_SHIFT 0
1300 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_OVRD_MASK 0x000FFC00
1303 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_RSRVD_MASK 0xFFF00000
1311 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_AW_PF_VEC_MSG_ADDR_SEL_MASK 0x000FFFFF
1312 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_AW_PF_VEC_MSG_ADDR_SEL_SHIFT 0
1314 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_RSRVD_MASK 0xFFF00000
1319 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_AW_PF_VEC_MSG_ADDR_OVRD_MASK 0x000FFFFF
1320 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_AW_PF_VEC_MSG_ADDR_OVRD_SHIFT 0
1322 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_RSRVD_MASK 0xFFF00000
1330 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_AR_PF_VEC_MSG_ADDR_SEL_MASK 0x000FFFFF
1331 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_AR_PF_VEC_MSG_ADDR_SEL_SHIFT 0
1333 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_RSRVD_MASK 0xFFF00000
1338 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_AR_PF_VEC_MSG_ADDR_OVRD_MASK 0x000FFFFF
1339 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_AR_PF_VEC_MSG_ADDR_OVRD_SHIFT 0
1341 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_RSRVD_MASK 0xFFF00000
1346 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_NO_SNOOP_OVRD (1 << 0)
1354 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_RSRVD_MASK 0xFFFFFFF0
1359 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_0_MASK 0x0000001F
1360 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_0_SHIFT 0
1362 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_1_MASK 0x000003E0
1365 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_2_MASK 0x00007C00
1368 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_3_MASK 0x000F8000
1375 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_RSRVD_MASK 0xFFC00000
1386 #define PCIE_AXI_INT_GRP_A_CAUSE_GM_COMPOSER_LOOKUP_ERR (1 << 0)
1446 #define PCIE_AXI_INT_GRP_A_CTRL_CLEAR_ON_READ (1 << 0)
1462 * Interrupt Status = 0.
1463 * When set,_on_Posedge =0, the bits in the Interrupt Cause register are set
1469 * cause bits are cleared to 0, enabling immediate interrupt assertion if any
1480 #define PCIE_AXI_INT_GRP_A_CTRL_AWID_MASK 0x00000F00
1486 #define PCIE_AXI_INT_GRP_A_CTRL_MOD_INTV_MASK 0x00FF0000
1490 * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
1494 #define PCIE_AXI_INT_GRP_A_CTRL_MOD_RES_MASK 0x0F000000