Lines Matching +full:pcie +full:- +full:ob
1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
41 * This header file provide API for the HAL driver of the pcie port, the driver
43 * - Port initialization
44 * - Link operation
45 * - Interrupts transactions generation (Endpoint mode).
46 * - Configuration Access management functions
47 * - Internal Translation Unit programming
50 * - PCIe transactions generation and reception (except interrupts as mentioned
53 * - Configuration Access: those transactions are generated automatically by
55 * through the fabric toward the PCIe port. This API provides management
57 * - Interrupt Handling.
58 * - Message Generation: common used messages are automatically generated, also,
60 * - PCIe Port Management: both link and port power management features can be
61 * managed using the PCI/PCIe standard power management and PCIe capabilities
63 * - PCIe link and protocol error handling: the feature can be managed using
64 * the Advanced Error Handling PCIe capability registers.
68 * - allocation and set zeros al_pcie_port and al_pcie_pf structures handles
69 * - call al_pcie_port_handle_init() with pointer to the allocated
72 * - call al_pcie_pf_handle_init() with pointer to the al_pcie_port handle
74 * - set the port mode, End-Point or Root-Compex (default).
75 * - set number of lanes connected to the controller.
76 * - enable the controller using the al_pcie_port_enable(). note that this
78 * - wait for 2000 South-bridge cycles.
79 * - prepare al_pcie_port_config_params and al_pcie_pf_config_params
85 * - Root Complex mode
86 * - Set the Max Link Speed to Gen2
87 * - Set the max lanes width to 2 (x2)
88 * - Enable Snoops to support I/O Hardware cache coherency
89 * - Enable pcie core RAM parity
90 * - Enable pcie core AXI parity
91 * - Keep transaction layer default credits
93 * - No EP parameters
94 * - No SR-IOV parameters
97 * - struct al_pcie_link_params link_params = {
101 * - struct al_pcie_port_config_params config_params = {
104 * AL_TRUE, // enable pcie port RAM parity
105 * AL_TRUE, // enable pcie port AXI parity
115 * - now call al_pcie_port_config() with pcie_port and port_config_params
116 * @subsection link-init Link Initialization
117 * - once the port configured, we can start PCIe link:
118 * - call al_pcie_link_start()
119 * - call al_pcie_link_up_wait()
120 * - allocate al_pcie_link_status struct and call al_pcie_link_status() and
124 * - Once the link is established, we can prepare the port for pci
128 * secondary bus), the sub-ordinary bus will be temporarily set to maximum
131 * - call al_pcie_secondary_bus_set() with sec-bus = 5
132 * - call al_pcie_subordinary_bus_set() with sub-bus = 255
135 * - we assume using ECAM method, in this method, the software issues pcie Cfg
136 * access by accessing the ECAM memory space of the pcie port. For example, to
144 * - call al_pcie_target_bus_set() with target_bus set to the required bus of
164 * PCIe Core revision IDs:
181 /** Inbound header credits sum - rev1/2 */
183 /** Inbound header credits sum - rev3 */
187 * PCIe AER uncorrectable error bits
189 * - al_pcie_aer_config
190 * - al_pcie_aer_uncorr_get_and_clear
218 * PCIe AER correctable error bits
220 * - al_pcie_aer_config
221 * - al_pcie_aer_corr_get_and_clear
233 /** Advisory Non-Fatal Error */
247 * inbound posted/non-posted parameters.
252 /* Internally used - see 'al_pcie_ib_hcrd_os_ob_reads_config' */
255 /* Internally used - see 'al_pcie_ib_hcrd_os_ob_reads_config' */
269 * al_pcie_port: data structure used by the HAL to handle a specific pcie port.
327 /** PCIe capabilities that supported by a specific port */
337 /** PCIe link related parameters */
344 /** PCIe gen2 link parameters */
351 /** PCIe gen 3 standard per lane equalization parameters */
359 /** PCIe gen 3 equalization parameters */
376 * Inbound posted/non-posted header credits and outstanding outbound reads
380 * the PCIe port. This resource includes the PCIe TLP headers coming on the PCIe
382 * - Inbound Non-posted, which are PCIe Reads as well as PCIe Config Cycles
383 * - Inbound Posted, i.e. PCIe Writes
384 * - Inbound Read-completion, which are the completions matching and outbound
390 * where a different ratio between Posted-Writes and Read-Completions is desired
393 * - nof_cpl_hdr + nof_np_hdr + nof_p_hdr ==
395 * - nof_cpl_hdr > 0
396 * - nof_p_hdr > 0
397 * - nof_np_hdr > 0
410 * This value set the possible outstanding headers reads (non-posted
425 * PCIe Ack/Nak Latency and Replay timers
428 * very slow external devices like low-end FPGA or hardware devices
439 * Description: SRIS is PCI SIG ECN, that enables the two peers on a given PCIe
441 * clock and requires inserting PCIe SKP symbols on the link in faster frequency
442 * that original PCIe spec
457 * - For downstream port, set enable_tx_relaxed_ordering
458 * - For upstream port
459 * - set enable_rx_relaxed_ordering
460 * - set enable tx_relaxed_ordering for emulated EP.
463 * - For Root-Complex:
464 * - tx_relaxed_ordering = AL_FALSE, rx_relaxed_ordering = AL_TRUE
465 * - For End-Point:
466 * - tx_relaxed_ordering = AL_TRUE, rx_relaxed_ordering = AL_FALSE
473 /** PCIe port configuration parameters
526 * disable advertising support for Function-Level-Reset
543 /** PCIe link status */
551 /** PCIe lane status */
558 * PCIe MSIX capability configuration parameters
562 /* Number of entries - size can be up to: 2024 */
571 /** PCIE AER capability parameters */
574 * while this feature is powerful, all known Chip-sets and processors
584 * 0 - no reporting at all
588 * Enabled reporting of non-fatal uncorrectable errors (bit mask)
590 * 0 - no reporting at all
596 * 0 - no reporting at all
602 /********************************** PCIe API **********************************/
605 /*************************** PCIe Initialization API **************************/
608 * Initializes a PCIe port handle structure.
610 * @param pcie_port an allocated, non-initialized instance.
625 * Initializes a PCIe pf handle structure
626 * @param pcie_pf an allocated, non-initialized instance of pf handle
627 * @param pcie_port pcie port handle
638 * @param pcie_port pcie port handle
643 /************************** Pre PCIe Port Enable API **************************/
646 * @brief set current pcie operating mode (root complex or endpoint)
650 * @param pcie_port pcie port handle
651 * @param mode pcie operating mode
662 * @param pcie_port pcie port handle
673 * @param pcie_port pcie port handle
677 * - this function must be called before any al_pcie_pf_config() calls
678 * - exposed on a given PCIe Endpoint port
679 * - PCIe rev1/rev2 supports only single Endpoint
680 * - PCIe rev3 can support up to 4
687 * @brief Inbound posted/non-posted header credits and outstanding outbound
690 * @param pcie_port pcie port handle
699 /** return PCIe operating mode
700 * @param pcie_port pcie port handle
707 * PCIe AXI quality of service configuration
710 * Initialized PCIe port handle
712 * AXI read quality of service (0 - 15)
714 * AXI write quality of service (0 - 15)
721 /**************************** PCIe Port Enable API ****************************/
724 * Enable PCIe unit (deassert reset)
728 * @param pcie_port pcie port handle
734 /** Disable PCIe unit (assert reset)
736 * @param pcie_port pcie port handle
742 * Memory shutdown should be called for an unused ports for power-saving
746 * @param pcie_port pcie port handle
756 * @param pcie_port pcie port handle
761 /*************************** PCIe Configuration API ***************************/
764 * @brief configure pcie port (mode, link params, etc..)
767 * @param pcie_port pcie port handle
779 * @param pcie_pf pcie pf handle
788 /************************** PCIe Link Operations API **************************/
791 * @brief start pcie link
793 * and pre port-enable and configurations are done
794 * @param pcie_port pcie port handle
801 * @brief stop pcie link
803 * @param pcie_port pcie port handle
810 * @brief check if pcie link is started
812 * @param pcie_port pcie port handle
818 * @brief trigger link-disable
820 * @param pcie_port pcie port handle
824 * functionality where both sides of the PCIe agrees to disable the link
833 * @param pcie_port pcie port handle
834 * @param timeout_ms maximum timeout in milli-seconds to wait for link up
837 * -ETIME if not.
844 * @param pcie_port pcie port handle
855 * pcie port handle
857 * PCIe lane
869 * this function initiates In-Band reset while link is up.
874 * @param pcie_port pcie port handle
875 * @param enable AL_TRUE to enable hot-reset and AL_FALSE to disable it
882 * @brief trigger link-retain
885 * re-entering Recovery is permitted but not required.
888 * @param pcie_port pcie port handle
890 * Note: there's no need to disable initiating link-retrain
897 * this function changes the port speed, it doesn't wait for link re-establishment
899 * @param pcie_port pcie port handle
914 * @brief configure pcie port axi snoop
915 * This enable the inbound PCIe posted write data or the Read completion data to
918 * @param pcie_port pcie port handle
930 * Configuration Space Access Through PCI-E_ECAM_Ext PASW
932 * on the PCIe ports by writing to part of the processor memory space marked by
933 * the PCI-E_EXCAM_Ext address window
938 * @param pcie_pf pcie pf handle
949 * @param pcie_pf pcie pf handle
960 * @param pcie_pf PCIe pf handle
965 * the PCIe Core specifications
966 * @param allow_ro_wr AL_TRUE to allow writing into read-only regs
983 * @param pcie_port pcie port handle
994 * @param pcie_port pcie port handle
1008 * @param pcie_port pcie port handle
1020 * @param pcie_port pcie port handle
1022 * downstream of the PCIE instance.
1032 * Other incoming non-configuration Requests complete with Unsupported Request status.
1036 * @param pcie_port pcie port handle
1043 * @param pcie_port pcie port handle
1055 /** decoding of the PCIe TLP Type as appears on the wire */
1083 /* the 64-bit address that get matched with the 64-bit address incoming
1084 * on the PCIe TLP
1089 * For Alpine V1 (PCIe rev1): only bits [39:0] are valid
1090 * For Alpine V2 (PCIe rev2/rev3): only bits [47:0] are valid
1092 * - address >= base_addr
1093 * - address <= base_addr + limit
1112 * PCIe TLP type
1117 * PCIe frame header attr field.
1128 * PCIe Message code
1136 * CFG Shift Mode. This is useful for CFG transactions where the PCIe
1140 * using a 28-bit effective address.Shifts bits [27:12] of the
1153 * MEM-I/O: 0 = Address Match Mode
1163 * - AL_TRUE : enables taking the function number of the translated TLP
1164 * from the PCIe core
1165 * - AL_FALSE: no function number is taken from PCIe core
1167 * - AL_TRUE : enables ATU function match mode
1168 * - AL_FALSE: no function match mode applied to transactions
1205 * @param pcie_port pcie port handle
1216 * @param pcie_port pcie port handle
1217 * @param direction input: iATU direction (IB/OB)
1231 * This is an EP feature, enabling PCIe IO transaction to be captured if it fits
1232 * within start and end address, and then mapped to internal 4-byte
1235 * @param pcie_port pcie port handle
1256 * @param pcie_pf pcie pf handle
1263 * @param pcie_pf pcie pf handle
1275 * @param pcie_pf pcie pf handle
1283 * @param pcie_pf pcie pf handle
1293 * @param pcie_pf pcie pf handle
1300 * @param pcie_pf pcie pf handle
1309 * @param pcie_pf pcie pf handle
1319 * @param pcie_pf pcie pf handle
1320 * @return bit mask of uncorrectable errors - see 'AL_PCIE_AER_UNCORR_*' for
1327 * @param pcie_pf pcie pf handle
1328 * @return bit mask of correctable errors - see 'AL_PCIE_AER_CORR_*' for
1336 * @param pcie_pf pcie pf handle
1345 * @param pcie_port pcie port handle
1355 * @param pcie_port pcie port handle
1356 * @return bit mask of uncorrectable errors - see 'AL_PCIE_AER_UNCORR_*' for
1364 * @param pcie_port pcie port handle
1365 * @return bit mask of correctable errors - see 'AL_PCIE_AER_CORR_*' for
1374 * @param pcie_port pcie port handle
1381 /******************** Loop-Back mode (RC and Endpoint modes) ******************/
1384 * @brief enter local pipe loop-back mode
1391 * @param pcie_port pcie port handle
1399 * @param pcie_port pcie port handle
1412 * @param pcie_port pcie port handle
1420 * @param pcie_port pcie port handle