Lines Matching +full:message +full:- +full:handling +full:- +full:unit
1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
43 * - Port initialization
44 * - Link operation
45 * - Interrupts transactions generation (Endpoint mode).
46 * - Configuration Access management functions
47 * - Internal Translation Unit programming
50 * - PCIe transactions generation and reception (except interrupts as mentioned
53 * - Configuration Access: those transactions are generated automatically by
57 * - Interrupt Handling.
58 * - Message Generation: common used messages are automatically generated, also,
60 * - PCIe Port Management: both link and port power management features can be
63 * - PCIe link and protocol error handling: the feature can be managed using
64 * the Advanced Error Handling PCIe capability registers.
68 * - allocation and set zeros al_pcie_port and al_pcie_pf structures handles
69 * - call al_pcie_port_handle_init() with pointer to the allocated
72 * - call al_pcie_pf_handle_init() with pointer to the al_pcie_port handle
74 * - set the port mode, End-Point or Root-Compex (default).
75 * - set number of lanes connected to the controller.
76 * - enable the controller using the al_pcie_port_enable(). note that this
78 * - wait for 2000 South-bridge cycles.
79 * - prepare al_pcie_port_config_params and al_pcie_pf_config_params
85 * - Root Complex mode
86 * - Set the Max Link Speed to Gen2
87 * - Set the max lanes width to 2 (x2)
88 * - Enable Snoops to support I/O Hardware cache coherency
89 * - Enable pcie core RAM parity
90 * - Enable pcie core AXI parity
91 * - Keep transaction layer default credits
93 * - No EP parameters
94 * - No SR-IOV parameters
97 * - struct al_pcie_link_params link_params = {
101 * - struct al_pcie_port_config_params config_params = {
115 * - now call al_pcie_port_config() with pcie_port and port_config_params
116 * @subsection link-init Link Initialization
117 * - once the port configured, we can start PCIe link:
118 * - call al_pcie_link_start()
119 * - call al_pcie_link_up_wait()
120 * - allocate al_pcie_link_status struct and call al_pcie_link_status() and
124 * - Once the link is established, we can prepare the port for pci
128 * secondary bus), the sub-ordinary bus will be temporarily set to maximum
131 * - call al_pcie_secondary_bus_set() with sec-bus = 5
132 * - call al_pcie_subordinary_bus_set() with sub-bus = 255
135 * - we assume using ECAM method, in this method, the software issues pcie Cfg
144 * - call al_pcie_target_bus_set() with target_bus set to the required bus of
181 /** Inbound header credits sum - rev1/2 */
183 /** Inbound header credits sum - rev3 */
189 * - al_pcie_aer_config
190 * - al_pcie_aer_uncorr_get_and_clear
220 * - al_pcie_aer_config
221 * - al_pcie_aer_corr_get_and_clear
233 /** Advisory Non-Fatal Error */
247 * inbound posted/non-posted parameters.
252 /* Internally used - see 'al_pcie_ib_hcrd_os_ob_reads_config' */
255 /* Internally used - see 'al_pcie_ib_hcrd_os_ob_reads_config' */
376 * Inbound posted/non-posted header credits and outstanding outbound reads
382 * - Inbound Non-posted, which are PCIe Reads as well as PCIe Config Cycles
383 * - Inbound Posted, i.e. PCIe Writes
384 * - Inbound Read-completion, which are the completions matching and outbound
390 * where a different ratio between Posted-Writes and Read-Completions is desired
393 * - nof_cpl_hdr + nof_np_hdr + nof_p_hdr ==
395 * - nof_cpl_hdr > 0
396 * - nof_p_hdr > 0
397 * - nof_np_hdr > 0
410 * This value set the possible outstanding headers reads (non-posted
428 * very slow external devices like low-end FPGA or hardware devices
457 * - For downstream port, set enable_tx_relaxed_ordering
458 * - For upstream port
459 * - set enable_rx_relaxed_ordering
460 * - set enable tx_relaxed_ordering for emulated EP.
463 * - For Root-Complex:
464 * - tx_relaxed_ordering = AL_FALSE, rx_relaxed_ordering = AL_TRUE
465 * - For End-Point:
466 * - tx_relaxed_ordering = AL_TRUE, rx_relaxed_ordering = AL_FALSE
494 * when true, the PCI unit will return Slave Error/Decoding Error to any
526 * disable advertising support for Function-Level-Reset
562 /* Number of entries - size can be up to: 2024 */
574 * while this feature is powerful, all known Chip-sets and processors
584 * 0 - no reporting at all
588 * Enabled reporting of non-fatal uncorrectable errors (bit mask)
590 * 0 - no reporting at all
596 * 0 - no reporting at all
610 * @param pcie_port an allocated, non-initialized instance.
626 * @param pcie_pf an allocated, non-initialized instance of pf handle
677 * - this function must be called before any al_pcie_pf_config() calls
678 * - exposed on a given PCIe Endpoint port
679 * - PCIe rev1/rev2 supports only single Endpoint
680 * - PCIe rev3 can support up to 4
687 * @brief Inbound posted/non-posted header credits and outstanding outbound
712 * AXI read quality of service (0 - 15)
714 * AXI write quality of service (0 - 15)
724 * Enable PCIe unit (deassert reset)
734 /** Disable PCIe unit (assert reset)
742 * Memory shutdown should be called for an unused ports for power-saving
793 * and pre port-enable and configurations are done
818 * @brief trigger link-disable
834 * @param timeout_ms maximum timeout in milli-seconds to wait for link up
837 * -ETIME if not.
869 * this function initiates In-Band reset while link is up.
875 * @param enable AL_TRUE to enable hot-reset and AL_FALSE to disable it
882 * @brief trigger link-retain
885 * re-entering Recovery is permitted but not required.
890 * Note: there's no need to disable initiating link-retrain
897 * this function changes the port speed, it doesn't wait for link re-establishment
930 * Configuration Space Access Through PCI-E_ECAM_Ext PASW
933 * the PCI-E_EXCAM_Ext address window
966 * @param allow_ro_wr AL_TRUE to allow writing into read-only regs
1032 * Other incoming non-configuration Requests complete with Unsupported Request status.
1048 /*************** Internal Address Translation Unit (ATU) API ******************/
1083 /* the 64-bit address that get matched with the 64-bit address incoming
1092 * - address >= base_addr
1093 * - address <= base_addr + limit
1128 * PCIe Message code
1129 * MSG TLPs (Message Code). When the address of an outbound TLP is
1131 * then the message field of the TLP is changed to the value in this
1140 * using a 28-bit effective address.Shifts bits [27:12] of the
1153 * MEM-I/O: 0 = Address Match Mode
1163 * - AL_TRUE : enables taking the function number of the translated TLP
1165 * - AL_FALSE: no function number is taken from PCIe core
1167 * - AL_TRUE : enables ATU function match mode
1168 * - AL_FALSE: no function match mode applied to transactions
1189 * Message Code Match Enable(Msg TLPS). Ensures that a successful
1190 * message Code TLP field comparison match (see Message msg_code)occurs
1232 * within start and end address, and then mapped to internal 4-byte
1255 /* @brief generate FLR_PF_DONE message
1262 * @brief generate INTx Assert/DeAssert Message
1264 * @param assert when true, Assert Message is sent
1265 * @param type type of message (INTA, INTB, etc)
1320 * @return bit mask of uncorrectable errors - see 'AL_PCIE_AER_UNCORR_*' for
1328 * @return bit mask of correctable errors - see 'AL_PCIE_AER_CORR_*' for
1356 * @return bit mask of uncorrectable errors - see 'AL_PCIE_AER_UNCORR_*' for
1365 * @return bit mask of correctable errors - see 'AL_PCIE_AER_CORR_*' for
1381 /******************** Loop-Back mode (RC and Endpoint modes) ******************/
1384 * @brief enter local pipe loop-back mode