113 	al_reg_write32(&pcie_port->regs->port_regs->rd_only_wr_en,  in al_pcie_port_wr_to_ro_set()
154 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_link_speed_ctrl_set()  local
161 			(uint32_t __iomem *)(regs->core_space[0].pcie_link_cap_base),  in al_pcie_port_link_speed_ctrl_set()
164 			(uint32_t __iomem *)(regs->core_space[0].pcie_cap_base  in al_pcie_port_link_speed_ctrl_set()
177 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_link_config()  local
194 		al_reg_write32_masked(regs->core_space[0].pcie_dev_ctrl_status,  in al_pcie_port_link_config()
213 	al_reg_write32_masked(&regs->port_regs->gen2_ctrl,  in al_pcie_port_link_config()
216 	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_port_link_config()
229 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_ram_parity_int_config()  local
231 	al_reg_write32(&regs->app.parity->en_core,  in al_pcie_port_ram_parity_int_config()
234 	al_reg_write32_masked(&regs->app.int_grp_b->mask,  in al_pcie_port_ram_parity_int_config()
246 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_axi_parity_int_config()  local
261 	al_reg_write32(regs->axi.parity.en_axi,  in al_pcie_port_axi_parity_int_config()
265 		al_reg_write32_masked(regs->axi.ctrl.global,  in al_pcie_port_axi_parity_int_config()
277 		al_reg_write32_masked(regs->axi.ctrl.global,  in al_pcie_port_axi_parity_int_config()
290 	al_reg_write32_masked(&regs->axi.int_grp_a->mask,  in al_pcie_port_axi_parity_int_config()
309 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_relaxed_pcie_ordering_config()  local
330 		regs->axi.ordering.pos_cntl,  in al_pcie_port_relaxed_pcie_ordering_config()
362 		struct al_pcie_revx_regs __iomem *regs =  in al_pcie_rev_id_get()  local
366 		dev_id = al_reg_read32(&regs->axi.device_id.device_rev_id) &  in al_pcie_rev_id_get()
390 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_lat_rply_timers_config()  local
396 	al_reg_write32(&regs->port_regs->ack_lat_rply_timer, reg);  in al_pcie_port_lat_rply_timers_config()
467 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_check_link()  local
471 	info_0 = al_reg_read32(&regs->app.debug->info_0);  in al_pcie_check_link()
493 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_gen2_params_config()  local
502 	gen2_ctrl = al_reg_read32(&regs->port_regs->gen2_ctrl);  in al_pcie_port_gen2_params_config()
519 	al_reg_write32(&regs->port_regs->gen2_ctrl, gen2_ctrl);  in al_pcie_port_gen2_params_config()
542 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_gen3_params_config()  local
544 …uint16_t __iomem *lanes_eq_base = (uint16_t __iomem *)(regs->core_space[0].pcie_sec_ext_cap_base +…  in al_pcie_port_gen3_params_config()
557 	al_reg_write32(regs->core_space[0].pcie_sec_ext_cap_base + (4 >> 2),  in al_pcie_port_gen3_params_config()
573 	reg = al_reg_read32(&regs->port_regs->gen3_ctrl);  in al_pcie_port_gen3_params_config()
584 	al_reg_write32(&regs->port_regs->gen3_ctrl, reg);  in al_pcie_port_gen3_params_config()
594 	al_reg_write32(&regs->port_regs->gen3_eq_fs_lf, reg);  in al_pcie_port_gen3_params_config()
603 	al_reg_write32(regs->axi.conf.zero_lane0, reg);  in al_pcie_port_gen3_params_config()
604 	al_reg_write32(regs->axi.conf.zero_lane1, reg);  in al_pcie_port_gen3_params_config()
605 	al_reg_write32(regs->axi.conf.zero_lane2, reg);  in al_pcie_port_gen3_params_config()
606 	al_reg_write32(regs->axi.conf.zero_lane3, reg);  in al_pcie_port_gen3_params_config()
608 		al_reg_write32(regs->axi.conf.zero_lane4, reg);  in al_pcie_port_gen3_params_config()
609 		al_reg_write32(regs->axi.conf.zero_lane5, reg);  in al_pcie_port_gen3_params_config()
610 		al_reg_write32(regs->axi.conf.zero_lane6, reg);  in al_pcie_port_gen3_params_config()
611 		al_reg_write32(regs->axi.conf.zero_lane7, reg);  in al_pcie_port_gen3_params_config()
623 	al_reg_write32(&regs->port_regs->gen3_eq_ctrl, reg);  in al_pcie_port_gen3_params_config()
633 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_pf_params_config()  local
643 			regs->core_space[pf_num].pcie_pm_cap_base,  in al_pcie_port_pf_params_config()
649 			regs->core_space[pf_num].pcie_dev_cap_base,  in al_pcie_port_pf_params_config()
653 			regs->core_space[pcie_pf->pf_num].pcie_dev_cap_base,  in al_pcie_port_pf_params_config()
659 			regs->core_space[pf_num].pcie_cap_base + (AL_PCI_EXP_LNKCAP >> 2),  in al_pcie_port_pf_params_config()
672 …uint32_t __iomem *bar_addr = &regs->core_space[pf_num].config_header[(AL_PCI_BASE_ADDRESS_0 >> 2) …  in al_pcie_port_pf_params_config()
780 			&regs->core_space[pf_num].config_header[AL_PCI_EXP_ROM_BASE_ADDRESS >> 2];  in al_pcie_port_pf_params_config()
788 			&regs->core_space[pf_num].config_header[AL_PCI_EXP_ROM_BASE_ADDRESS >> 2];  in al_pcie_port_pf_params_config()
794 		al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_0, (1 << 21));  in al_pcie_port_pf_params_config()
797 		al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_3, (1 << 18));  in al_pcie_port_pf_params_config()
820 		al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22));  in al_pcie_port_pf_params_config()
823 		al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_3, (1 << 19));  in al_pcie_port_pf_params_config()
845 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_sris_config()  local
860 		al_reg_write32_masked(&regs->app.cfg_func_ext->cfg,  in al_pcie_port_sris_config()
864 		al_reg_write32_masked(regs->app.global_ctrl.sris_kp_counter,  in al_pcie_port_sris_config()
883 		al_reg_write32_masked(&regs->port_regs->filter_mask_reg_1,  in al_pcie_port_sris_config()
901 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_ib_hcrd_config()  local
904 		&regs->port_regs->vc0_posted_rcv_q_ctrl,  in al_pcie_port_ib_hcrd_config()
910 		&regs->port_regs->vc0_non_posted_rcv_q_ctrl,  in al_pcie_port_ib_hcrd_config()
919 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_max_num_of_pfs_get()  local
929 		max_func_num = al_reg_read32(&regs->port_regs->timer_ctrl_max_func_num);  in al_pcie_port_max_num_of_pfs_get()
939 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_ecrc_gen_ob_atu_enable()  local
949 		al_reg_write32(&regs->port_regs->iatu.index, reg);  in al_pcie_ecrc_gen_ob_atu_enable()
950 		reg = al_reg_read32(&regs->port_regs->iatu.cr2);  in al_pcie_ecrc_gen_ob_atu_enable()
952 		reg = al_reg_read32(&regs->port_regs->iatu.cr1);  in al_pcie_ecrc_gen_ob_atu_enable()
959 			al_reg_write32(&regs->port_regs->iatu.cr1, reg);  in al_pcie_ecrc_gen_ob_atu_enable()
985 	pcie_port->regs = &pcie_port->regs_ptrs;  in al_pcie_port_handle_init()
998 	al_memset(pcie_port->regs, 0, sizeof(struct al_pcie_regs));  in al_pcie_port_handle_init()
1001 		struct al_pcie_rev1_regs __iomem *regs =  in al_pcie_port_handle_init()  local
1004 		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;  in al_pcie_port_handle_init()
1005 		pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;  in al_pcie_port_handle_init()
1006 		pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;  in al_pcie_port_handle_init()
1007 		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;  in al_pcie_port_handle_init()
1008 		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;  in al_pcie_port_handle_init()
1009 		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;  in al_pcie_port_handle_init()
1010 		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;  in al_pcie_port_handle_init()
1011 		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;  in al_pcie_port_handle_init()
1012 		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;  in al_pcie_port_handle_init()
1013 		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;  in al_pcie_port_handle_init()
1014 		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;  in al_pcie_port_handle_init()
1015 		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;  in al_pcie_port_handle_init()
1016 		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;  in al_pcie_port_handle_init()
1017 		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;  in al_pcie_port_handle_init()
1018 		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;  in al_pcie_port_handle_init()
1019 		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;  in al_pcie_port_handle_init()
1020 		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;  in al_pcie_port_handle_init()
1021 		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;  in al_pcie_port_handle_init()
1022 		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;  in al_pcie_port_handle_init()
1023 		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;  in al_pcie_port_handle_init()
1024 		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;  in al_pcie_port_handle_init()
1025 		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;  in al_pcie_port_handle_init()
1026 		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;  in al_pcie_port_handle_init()
1027 …pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_se…  in al_pcie_port_handle_init()
1028 		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;  in al_pcie_port_handle_init()
1029 		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;  in al_pcie_port_handle_init()
1031 		pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;  in al_pcie_port_handle_init()
1032 		pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;  in al_pcie_port_handle_init()
1033 		pcie_port->regs->app.global_ctrl.events_gen[0] = &regs->app.global_ctrl.events_gen;  in al_pcie_port_handle_init()
1034 		pcie_port->regs->app.debug = &regs->app.debug;  in al_pcie_port_handle_init()
1035 		pcie_port->regs->app.soc_int[0].status_0 = &regs->app.soc_int.status_0;  in al_pcie_port_handle_init()
1036 		pcie_port->regs->app.soc_int[0].status_1 = &regs->app.soc_int.status_1;  in al_pcie_port_handle_init()
1037 		pcie_port->regs->app.soc_int[0].status_2 = &regs->app.soc_int.status_2;  in al_pcie_port_handle_init()
1038 		pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = &regs->app.soc_int.mask_inta_leg_0;  in al_pcie_port_handle_init()
1039 		pcie_port->regs->app.soc_int[0].mask_inta_leg_1 = &regs->app.soc_int.mask_inta_leg_1;  in al_pcie_port_handle_init()
1040 		pcie_port->regs->app.soc_int[0].mask_inta_leg_2 = &regs->app.soc_int.mask_inta_leg_2;  in al_pcie_port_handle_init()
1041 		pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = &regs->app.soc_int.mask_msi_leg_0;  in al_pcie_port_handle_init()
1042 		pcie_port->regs->app.soc_int[0].mask_msi_leg_1 = &regs->app.soc_int.mask_msi_leg_1;  in al_pcie_port_handle_init()
1043 		pcie_port->regs->app.soc_int[0].mask_msi_leg_2 = &regs->app.soc_int.mask_msi_leg_2;  in al_pcie_port_handle_init()
1044 		pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;  in al_pcie_port_handle_init()
1045 		pcie_port->regs->app.parity = &regs->app.parity;  in al_pcie_port_handle_init()
1046 		pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;  in al_pcie_port_handle_init()
1047 		pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;  in al_pcie_port_handle_init()
1048 		pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;  in al_pcie_port_handle_init()
1049 		pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;  in al_pcie_port_handle_init()
1051 		pcie_port->regs->core_space[0].config_header = regs->core_space.config_header;  in al_pcie_port_handle_init()
1052 		pcie_port->regs->core_space[0].pcie_pm_cap_base = &regs->core_space.pcie_pm_cap_base;  in al_pcie_port_handle_init()
1053 		pcie_port->regs->core_space[0].pcie_cap_base = &regs->core_space.pcie_cap_base;  in al_pcie_port_handle_init()
1054 		pcie_port->regs->core_space[0].pcie_dev_cap_base = &regs->core_space.pcie_dev_cap_base;  in al_pcie_port_handle_init()
1055 		pcie_port->regs->core_space[0].pcie_dev_ctrl_status = &regs->core_space.pcie_dev_ctrl_status;  in al_pcie_port_handle_init()
1056 		pcie_port->regs->core_space[0].pcie_link_cap_base = &regs->core_space.pcie_link_cap_base;  in al_pcie_port_handle_init()
1057 		pcie_port->regs->core_space[0].msix_cap_base = &regs->core_space.msix_cap_base;  in al_pcie_port_handle_init()
1058 		pcie_port->regs->core_space[0].aer = &regs->core_space.aer;  in al_pcie_port_handle_init()
1059 		pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.pcie_sec_ext_cap_base;  in al_pcie_port_handle_init()
1061 		pcie_port->regs->port_regs = &regs->core_space.port_regs;  in al_pcie_port_handle_init()
1064 		struct al_pcie_rev2_regs __iomem *regs =  in al_pcie_port_handle_init()  local
1067 		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;  in al_pcie_port_handle_init()
1068 		pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;  in al_pcie_port_handle_init()
1069 		pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;  in al_pcie_port_handle_init()
1070 		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;  in al_pcie_port_handle_init()
1071 		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;  in al_pcie_port_handle_init()
1072 		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;  in al_pcie_port_handle_init()
1073 		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;  in al_pcie_port_handle_init()
1074 		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;  in al_pcie_port_handle_init()
1075 		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;  in al_pcie_port_handle_init()
1076 		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;  in al_pcie_port_handle_init()
1077 		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;  in al_pcie_port_handle_init()
1078 		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;  in al_pcie_port_handle_init()
1079 		pcie_port->regs->axi.ob_ctrl.tgtid_reg_ovrd = &regs->axi.ob_ctrl.tgtid_reg_ovrd;  in al_pcie_port_handle_init()
1080 		pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_sel = &regs->axi.ob_ctrl.addr_high_reg_ovrd_sel;  in al_pcie_port_handle_init()
1081 …pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_value = &regs->axi.ob_ctrl.addr_high_reg_ovrd_valu…  in al_pcie_port_handle_init()
1082 		pcie_port->regs->axi.ob_ctrl.addr_size_replace = &regs->axi.ob_ctrl.addr_size_replace;  in al_pcie_port_handle_init()
1083 		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;  in al_pcie_port_handle_init()
1084 		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;  in al_pcie_port_handle_init()
1085 		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;  in al_pcie_port_handle_init()
1086 		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;  in al_pcie_port_handle_init()
1087 		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;  in al_pcie_port_handle_init()
1088 		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;  in al_pcie_port_handle_init()
1089 		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;  in al_pcie_port_handle_init()
1090 		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;  in al_pcie_port_handle_init()
1091 		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;  in al_pcie_port_handle_init()
1092 		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;  in al_pcie_port_handle_init()
1093 		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;  in al_pcie_port_handle_init()
1094 …pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_se…  in al_pcie_port_handle_init()
1095 		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;  in al_pcie_port_handle_init()
1096 		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;  in al_pcie_port_handle_init()
1098 		pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;  in al_pcie_port_handle_init()
1099 		pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;  in al_pcie_port_handle_init()
1100 		pcie_port->regs->app.global_ctrl.events_gen[0] = &regs->app.global_ctrl.events_gen;  in al_pcie_port_handle_init()
1101 …pcie_port->regs->app.global_ctrl.corr_err_sts_int = &regs->app.global_ctrl.pended_corr_err_sts_int;  in al_pcie_port_handle_init()
1102 …pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = &regs->app.global_ctrl.pended_uncorr_err_sts…  in al_pcie_port_handle_init()
1103 		pcie_port->regs->app.global_ctrl.sris_kp_counter = &regs->app.global_ctrl.sris_kp_counter_value;  in al_pcie_port_handle_init()
1104 		pcie_port->regs->app.debug = &regs->app.debug;  in al_pcie_port_handle_init()
1105 		pcie_port->regs->app.ap_user_send_msg = &regs->app.ap_user_send_msg;  in al_pcie_port_handle_init()
1106 		pcie_port->regs->app.soc_int[0].status_0 = &regs->app.soc_int.status_0;  in al_pcie_port_handle_init()
1107 		pcie_port->regs->app.soc_int[0].status_1 = &regs->app.soc_int.status_1;  in al_pcie_port_handle_init()
1108 		pcie_port->regs->app.soc_int[0].status_2 = &regs->app.soc_int.status_2;  in al_pcie_port_handle_init()
1109 		pcie_port->regs->app.soc_int[0].status_3 = &regs->app.soc_int.status_3;  in al_pcie_port_handle_init()
1110 		pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = &regs->app.soc_int.mask_inta_leg_0;  in al_pcie_port_handle_init()
1111 		pcie_port->regs->app.soc_int[0].mask_inta_leg_1 = &regs->app.soc_int.mask_inta_leg_1;  in al_pcie_port_handle_init()
1112 		pcie_port->regs->app.soc_int[0].mask_inta_leg_2 = &regs->app.soc_int.mask_inta_leg_2;  in al_pcie_port_handle_init()
1113 		pcie_port->regs->app.soc_int[0].mask_inta_leg_3 = &regs->app.soc_int.mask_inta_leg_3;  in al_pcie_port_handle_init()
1114 		pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = &regs->app.soc_int.mask_msi_leg_0;  in al_pcie_port_handle_init()
1115 		pcie_port->regs->app.soc_int[0].mask_msi_leg_1 = &regs->app.soc_int.mask_msi_leg_1;  in al_pcie_port_handle_init()
1116 		pcie_port->regs->app.soc_int[0].mask_msi_leg_2 = &regs->app.soc_int.mask_msi_leg_2;  in al_pcie_port_handle_init()
1117 		pcie_port->regs->app.soc_int[0].mask_msi_leg_3 = &regs->app.soc_int.mask_msi_leg_3;  in al_pcie_port_handle_init()
1118 		pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;  in al_pcie_port_handle_init()
1119 		pcie_port->regs->app.parity = &regs->app.parity;  in al_pcie_port_handle_init()
1120 		pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;  in al_pcie_port_handle_init()
1121 		pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;  in al_pcie_port_handle_init()
1122 		pcie_port->regs->app.status_per_func[0] = &regs->app.status_per_func;  in al_pcie_port_handle_init()
1123 		pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;  in al_pcie_port_handle_init()
1124 		pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;  in al_pcie_port_handle_init()
1126 		pcie_port->regs->core_space[0].config_header = regs->core_space.config_header;  in al_pcie_port_handle_init()
1127 		pcie_port->regs->core_space[0].pcie_pm_cap_base = &regs->core_space.pcie_pm_cap_base;  in al_pcie_port_handle_init()
1128 		pcie_port->regs->core_space[0].pcie_cap_base = &regs->core_space.pcie_cap_base;  in al_pcie_port_handle_init()
1129 		pcie_port->regs->core_space[0].pcie_dev_cap_base = &regs->core_space.pcie_dev_cap_base;  in al_pcie_port_handle_init()
1130 		pcie_port->regs->core_space[0].pcie_dev_ctrl_status = &regs->core_space.pcie_dev_ctrl_status;  in al_pcie_port_handle_init()
1131 		pcie_port->regs->core_space[0].pcie_link_cap_base = &regs->core_space.pcie_link_cap_base;  in al_pcie_port_handle_init()
1132 		pcie_port->regs->core_space[0].msix_cap_base = &regs->core_space.msix_cap_base;  in al_pcie_port_handle_init()
1133 		pcie_port->regs->core_space[0].aer = &regs->core_space.aer;  in al_pcie_port_handle_init()
1134 		pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.pcie_sec_ext_cap_base;  in al_pcie_port_handle_init()
1136 		pcie_port->regs->port_regs = &regs->core_space.port_regs;  in al_pcie_port_handle_init()
1139 		struct al_pcie_rev3_regs __iomem *regs =  in al_pcie_port_handle_init()  local
1141 		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;  in al_pcie_port_handle_init()
1142 		pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;  in al_pcie_port_handle_init()
1143 		pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;  in al_pcie_port_handle_init()
1144 		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;  in al_pcie_port_handle_init()
1145 		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;  in al_pcie_port_handle_init()
1146 		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;  in al_pcie_port_handle_init()
1147 		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;  in al_pcie_port_handle_init()
1148 		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;  in al_pcie_port_handle_init()
1149 		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;  in al_pcie_port_handle_init()
1150 		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;  in al_pcie_port_handle_init()
1151 		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;  in al_pcie_port_handle_init()
1152 		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;  in al_pcie_port_handle_init()
1153 		pcie_port->regs->axi.ob_ctrl.io_addr_mask_h = &regs->axi.ob_ctrl.io_addr_mask_h;  in al_pcie_port_handle_init()
1154 		pcie_port->regs->axi.ob_ctrl.ar_msg_addr_mask_h = &regs->axi.ob_ctrl.ar_msg_addr_mask_h;  in al_pcie_port_handle_init()
1155 		pcie_port->regs->axi.ob_ctrl.aw_msg_addr_mask_h = &regs->axi.ob_ctrl.aw_msg_addr_mask_h;  in al_pcie_port_handle_init()
1156 		pcie_port->regs->axi.ob_ctrl.tgtid_reg_ovrd = &regs->axi.ob_ctrl.tgtid_reg_ovrd;  in al_pcie_port_handle_init()
1157 		pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_sel = &regs->axi.ob_ctrl.addr_high_reg_ovrd_sel;  in al_pcie_port_handle_init()
1158 …pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_value = &regs->axi.ob_ctrl.addr_high_reg_ovrd_valu…  in al_pcie_port_handle_init()
1159 		pcie_port->regs->axi.ob_ctrl.addr_size_replace = &regs->axi.ob_ctrl.addr_size_replace;  in al_pcie_port_handle_init()
1160 		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;  in al_pcie_port_handle_init()
1161 		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;  in al_pcie_port_handle_init()
1162 		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;  in al_pcie_port_handle_init()
1163 		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;  in al_pcie_port_handle_init()
1164 		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;  in al_pcie_port_handle_init()
1165 		pcie_port->regs->axi.conf.zero_lane4 = &regs->axi.conf.zero_lane4;  in al_pcie_port_handle_init()
1166 		pcie_port->regs->axi.conf.zero_lane5 = &regs->axi.conf.zero_lane5;  in al_pcie_port_handle_init()
1167 		pcie_port->regs->axi.conf.zero_lane6 = &regs->axi.conf.zero_lane6;  in al_pcie_port_handle_init()
1168 		pcie_port->regs->axi.conf.zero_lane7 = &regs->axi.conf.zero_lane7;  in al_pcie_port_handle_init()
1169 		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;  in al_pcie_port_handle_init()
1170 		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;  in al_pcie_port_handle_init()
1171 		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;  in al_pcie_port_handle_init()
1172 		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;  in al_pcie_port_handle_init()
1173 		pcie_port->regs->axi.status.lane[4] = &regs->axi.status.lane4;  in al_pcie_port_handle_init()
1174 		pcie_port->regs->axi.status.lane[5] = &regs->axi.status.lane5;  in al_pcie_port_handle_init()
1175 		pcie_port->regs->axi.status.lane[6] = &regs->axi.status.lane6;  in al_pcie_port_handle_init()
1176 		pcie_port->regs->axi.status.lane[7] = &regs->axi.status.lane7;  in al_pcie_port_handle_init()
1177 		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;  in al_pcie_port_handle_init()
1178 		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;  in al_pcie_port_handle_init()
1179 …pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_se…  in al_pcie_port_handle_init()
1180 		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;  in al_pcie_port_handle_init()
1181 		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;  in al_pcie_port_handle_init()
1182 		pcie_port->regs->axi.axi_attr_ovrd.write_msg_ctrl_0 = &regs->axi.axi_attr_ovrd.write_msg_ctrl_0;  in al_pcie_port_handle_init()
1183 		pcie_port->regs->axi.axi_attr_ovrd.write_msg_ctrl_1 = &regs->axi.axi_attr_ovrd.write_msg_ctrl_1;  in al_pcie_port_handle_init()
1184 		pcie_port->regs->axi.axi_attr_ovrd.pf_sel = &regs->axi.axi_attr_ovrd.pf_sel;  in al_pcie_port_handle_init()
1187 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_0 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_0;  in al_pcie_port_handle_init()
1188 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_1 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_1;  in al_pcie_port_handle_init()
1189 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_2 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_2;  in al_pcie_port_handle_init()
1190 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_3 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_3;  in al_pcie_port_handle_init()
1191 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_4 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_4;  in al_pcie_port_handle_init()
1192 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_5 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_5;  in al_pcie_port_handle_init()
1193 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_6 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_6;  in al_pcie_port_handle_init()
1194 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_7 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_7;  in al_pcie_port_handle_init()
1195 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_8 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_8;  in al_pcie_port_handle_init()
1196 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_9 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_9;  in al_pcie_port_handle_init()
1199 		pcie_port->regs->axi.msg_attr_axuser_table.entry_vec = &regs->axi.msg_attr_axuser_table.entry_vec;  in al_pcie_port_handle_init()
1201 		pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;  in al_pcie_port_handle_init()
1202 		pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;  in al_pcie_port_handle_init()
1203 …pcie_port->regs->app.global_ctrl.corr_err_sts_int = &regs->app.global_ctrl.pended_corr_err_sts_int;  in al_pcie_port_handle_init()
1204 …pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = &regs->app.global_ctrl.pended_uncorr_err_sts…  in al_pcie_port_handle_init()
1207 			pcie_port->regs->app.global_ctrl.events_gen[i] = &regs->app.events_gen_per_func[i].events_gen;  in al_pcie_port_handle_init()
1210 		pcie_port->regs->app.global_ctrl.sris_kp_counter = &regs->app.global_ctrl.sris_kp_counter_value;  in al_pcie_port_handle_init()
1211 		pcie_port->regs->app.debug = &regs->app.debug;  in al_pcie_port_handle_init()
1214 			pcie_port->regs->app.soc_int[i].status_0 = &regs->app.soc_int_per_func[i].status_0;  in al_pcie_port_handle_init()
1215 			pcie_port->regs->app.soc_int[i].status_1 = &regs->app.soc_int_per_func[i].status_1;  in al_pcie_port_handle_init()
1216 			pcie_port->regs->app.soc_int[i].status_2 = &regs->app.soc_int_per_func[i].status_2;  in al_pcie_port_handle_init()
1217 			pcie_port->regs->app.soc_int[i].status_3 = &regs->app.soc_int_per_func[i].status_3;  in al_pcie_port_handle_init()
1218 			pcie_port->regs->app.soc_int[i].mask_inta_leg_0 = &regs->app.soc_int_per_func[i].mask_inta_leg_0;  in al_pcie_port_handle_init()
1219 			pcie_port->regs->app.soc_int[i].mask_inta_leg_1 = &regs->app.soc_int_per_func[i].mask_inta_leg_1;  in al_pcie_port_handle_init()
1220 			pcie_port->regs->app.soc_int[i].mask_inta_leg_2 = &regs->app.soc_int_per_func[i].mask_inta_leg_2;  in al_pcie_port_handle_init()
1221 			pcie_port->regs->app.soc_int[i].mask_inta_leg_3 = &regs->app.soc_int_per_func[i].mask_inta_leg_3;  in al_pcie_port_handle_init()
1222 			pcie_port->regs->app.soc_int[i].mask_msi_leg_0 = &regs->app.soc_int_per_func[i].mask_msi_leg_0;  in al_pcie_port_handle_init()
1223 			pcie_port->regs->app.soc_int[i].mask_msi_leg_1 = &regs->app.soc_int_per_func[i].mask_msi_leg_1;  in al_pcie_port_handle_init()
1224 			pcie_port->regs->app.soc_int[i].mask_msi_leg_2 = &regs->app.soc_int_per_func[i].mask_msi_leg_2;  in al_pcie_port_handle_init()
1225 			pcie_port->regs->app.soc_int[i].mask_msi_leg_3 = &regs->app.soc_int_per_func[i].mask_msi_leg_3;  in al_pcie_port_handle_init()
1228 		pcie_port->regs->app.ap_user_send_msg = &regs->app.ap_user_send_msg;  in al_pcie_port_handle_init()
1229 		pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;  in al_pcie_port_handle_init()
1230 		pcie_port->regs->app.parity = &regs->app.parity;  in al_pcie_port_handle_init()
1231 		pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;  in al_pcie_port_handle_init()
1232 		pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;  in al_pcie_port_handle_init()
1233 		pcie_port->regs->app.cfg_func_ext = &regs->app.cfg_func_ext;  in al_pcie_port_handle_init()
1236 			pcie_port->regs->app.status_per_func[i] = &regs->app.status_per_func[i];  in al_pcie_port_handle_init()
1238 		pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;  in al_pcie_port_handle_init()
1239 		pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;  in al_pcie_port_handle_init()
1240 		pcie_port->regs->app.int_grp_c = &regs->app.int_grp_c;  in al_pcie_port_handle_init()
1241 		pcie_port->regs->app.int_grp_d = &regs->app.int_grp_d;  in al_pcie_port_handle_init()
1244 			pcie_port->regs->core_space[i].config_header = regs->core_space.func[i].config_header;  in al_pcie_port_handle_init()
1245 			pcie_port->regs->core_space[i].pcie_pm_cap_base = &regs->core_space.func[i].pcie_pm_cap_base;  in al_pcie_port_handle_init()
1246 			pcie_port->regs->core_space[i].pcie_cap_base = &regs->core_space.func[i].pcie_cap_base;  in al_pcie_port_handle_init()
1247 			pcie_port->regs->core_space[i].pcie_dev_cap_base = &regs->core_space.func[i].pcie_dev_cap_base;  in al_pcie_port_handle_init()
1248 …pcie_port->regs->core_space[i].pcie_dev_ctrl_status = &regs->core_space.func[i].pcie_dev_ctrl_stat…  in al_pcie_port_handle_init()
1249 			pcie_port->regs->core_space[i].pcie_link_cap_base = &regs->core_space.func[i].pcie_link_cap_base;  in al_pcie_port_handle_init()
1250 			pcie_port->regs->core_space[i].msix_cap_base = &regs->core_space.func[i].msix_cap_base;  in al_pcie_port_handle_init()
1251 			pcie_port->regs->core_space[i].aer = &regs->core_space.func[i].aer;  in al_pcie_port_handle_init()
1252 			pcie_port->regs->core_space[i].tph_cap_base = &regs->core_space.func[i].tph_cap_base;  in al_pcie_port_handle_init()
1257 …pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.func[0].pcie_sec_ext_cap_…  in al_pcie_port_handle_init()
1259 		pcie_port->regs->port_regs = &regs->core_space.func[0].port_regs;  in al_pcie_port_handle_init()
1304 	       pcie_port->regs);  in al_pcie_pf_handle_init()
1322 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_operating_mode_config()  local
1331 	reg = al_reg_read32(regs->axi.pcie_global.conf);  in al_pcie_port_operating_mode_config()
1343 			al_reg_write32_masked(regs->axi.axi_attr_ovrd.pf_sel,  in al_pcie_port_operating_mode_config()
1373 	al_reg_write32(regs->axi.pcie_global.conf, reg);  in al_pcie_port_operating_mode_config()
1381 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_max_lanes_set()  local
1393 	al_reg_write32_masked(regs->axi.pcie_global.conf,  in al_pcie_port_max_lanes_set()
1408 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_max_num_of_pfs_set()  local
1425 			&regs->port_regs->timer_ctrl_max_func_num,  in al_pcie_port_max_num_of_pfs_set()
1436 			(&regs->core_space[0].config_header[0] +  in al_pcie_port_max_num_of_pfs_set()
1453 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_ib_hcrd_os_ob_reads_config()  local
1475 			regs->axi.init_fc.cfg,  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1493 			regs->axi.init_fc.cfg,  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1506 		regs->axi.pre_configuration.pcie_core_setup,  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1524 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_operating_mode_get()  local
1529 	reg = al_reg_read32(regs->axi.pcie_global.conf);  in al_pcie_operating_mode_get()
1553 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_axi_qos_config()  local
1560 		regs->axi.ctrl.master_arctl,  in al_pcie_axi_qos_config()
1564 		regs->axi.ctrl.master_awctl,  in al_pcie_axi_qos_config()
1577 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_enable()  local
1599 			regs->axi.ordering.pos_cntl,  in al_pcie_port_enable()
1638 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_memory_shutdown_set()  local
1649 	al_reg_write32_masked(regs->axi.pcie_global.conf,  in al_pcie_port_memory_shutdown_set()
1676 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_config()  local
1702 		uint32_t global_conf = al_reg_read32(regs->axi.pcie_global.conf);  in al_pcie_port_config()
1739 		al_reg_write32_masked(regs->core_space[i].pcie_dev_ctrl_status,  in al_pcie_port_config()
1751 			al_reg_write32_masked(regs->core_space[i].tph_cap_base,  in al_pcie_port_config()
1795 		al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_port_config()
1801 		al_reg_write32_masked(&regs->port_regs->axi_slave_err_resp,  in al_pcie_port_config()
1820 		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_target_bus,  in al_pcie_port_config()
1823 		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_control,  in al_pcie_port_config()
1834 			(uint16_t __iomem *)(&regs->core_space[0].config_header[0] + (0x4 >> 2)),  in al_pcie_port_config()
1842 			(uint32_t __iomem *)(&regs->core_space[0].config_header[0]  in al_pcie_port_config()
1861 		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_target_bus,  in al_pcie_port_config()
1909 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_link_start()  local
1920 			regs->app.global_ctrl.port_init,  in al_pcie_link_start()
1931 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_link_stop()  local
1941 			regs->app.global_ctrl.port_init,  in al_pcie_link_stop()
1951 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_is_link_started()  local
1953 	uint32_t port_init = al_reg_read32(regs->app.global_ctrl.port_init);  in al_pcie_is_link_started()
1988 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_link_status()  local
2010 …pcie_lnksta = al_reg_read16((uint16_t __iomem *)regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LN…  in al_pcie_link_status()
2041 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_lane_status_get()  local
2051 	reg_ptr = regs->axi.status.lane[lane];  in al_pcie_lane_status_get()
2068 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_link_hot_reset()  local
2083 	events_gen = al_reg_read32(regs->app.global_ctrl.events_gen[0]);  in al_pcie_link_hot_reset()
2096 		al_reg_write32_masked(regs->app.global_ctrl.events_gen[0],  in al_pcie_link_hot_reset()
2108 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_link_disable()  local
2123 	pcie_lnkctl = al_reg_read32(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1));  in al_pcie_link_disable()
2135 	al_reg_write32_masked(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1),  in al_pcie_link_disable()
2145 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_link_retrain()  local
2159 	al_reg_write32_masked(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1),  in al_pcie_link_retrain()
2170 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_link_change_speed()  local
2181 	al_reg_write32_masked(&regs->port_regs->gen2_ctrl,  in al_pcie_link_change_speed()
2206 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_snoop_config()  local
2213 		al_reg_write32_masked(regs->axi.ctrl.master_arctl,  in al_pcie_port_snoop_config()
2217 		al_reg_write32_masked(regs->axi.ctrl.master_awctl,  in al_pcie_port_snoop_config()
2221 		al_reg_write32_masked(regs->axi.ctrl.master_arctl,  in al_pcie_port_snoop_config()
2225 		al_reg_write32_masked(regs->axi.ctrl.master_awctl,  in al_pcie_port_snoop_config()
2239 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_config_space_get()  local
2241 	*addr = (uint8_t __iomem *)&regs->core_space[pcie_pf->pf_num].config_header[0];  in al_pcie_config_space_get()
2251 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_local_cfg_space_read()  local
2254 	data = al_reg_read32(&regs->core_space[pcie_pf->pf_num].config_header[reg_offset]);  in al_pcie_local_cfg_space_read()
2269 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_local_cfg_space_write()  local
2271 	uint32_t *offset = &regs->core_space[pf_num].config_header[reg_offset];  in al_pcie_local_cfg_space_write()
2292 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_target_bus_set()  local
2295 	reg = al_reg_read32(regs->axi.ob_ctrl.cfg_target_bus);  in al_pcie_target_bus_set()
2302 	al_reg_write32(regs->axi.ob_ctrl.cfg_target_bus, reg);  in al_pcie_target_bus_set()
2313 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_target_bus_get()  local
2319 	reg = al_reg_read32(regs->axi.ob_ctrl.cfg_target_bus);  in al_pcie_target_bus_get()
2334 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_secondary_bus_set()  local
2340 		regs->axi.ob_ctrl.cfg_control,  in al_pcie_secondary_bus_set()
2350 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_subordinary_bus_set()  local
2356 		regs->axi.ob_ctrl.cfg_control,  in al_pcie_subordinary_bus_set()
2368 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_app_req_retry_set()  local
2373 	al_reg_write32_masked(regs->app.global_ctrl.pm_control,  in al_pcie_app_req_retry_set()
2380 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_app_req_retry_get_status()  local
2386 	pm_control = al_reg_read32(regs->app.global_ctrl.pm_control);  in al_pcie_app_req_retry_get_status()
2398 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_atu_region_set()  local
2435 	al_reg_write32(&regs->port_regs->iatu.index, reg);  in al_pcie_atu_region_set()
2437 	al_reg_write32(&regs->port_regs->iatu.lower_base_addr,  in al_pcie_atu_region_set()
2439 	al_reg_write32(&regs->port_regs->iatu.upper_base_addr,  in al_pcie_atu_region_set()
2441 	al_reg_write32(&regs->port_regs->iatu.lower_target_addr,  in al_pcie_atu_region_set()
2443 	al_reg_write32(&regs->port_regs->iatu.upper_target_addr,  in al_pcie_atu_region_set()
2451 			&regs->app.atu.out_mask_pair[atu_region->index / 2] :  in al_pcie_atu_region_set()
2452 			&regs->app.atu.in_mask_pair[atu_region->index / 2];  in al_pcie_atu_region_set()
2479 		al_reg_write32(&regs->port_regs->iatu.limit_addr,  in al_pcie_atu_region_set()
2502 			al_reg_write32_masked(regs->app.atu.reg_out_mask,  in al_pcie_atu_region_set()
2508 				&regs->app.atu.out_mask_pair[atu_region->index / 2] :  in al_pcie_atu_region_set()
2509 				&regs->app.atu.in_mask_pair[atu_region->index / 2];  in al_pcie_atu_region_set()
2540 	al_reg_write32(&regs->port_regs->iatu.cr1, reg);  in al_pcie_atu_region_set()
2565 	al_reg_write32(&regs->port_regs->iatu.cr2, reg);  in al_pcie_atu_region_set()
2577 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_atu_region_get_fields()  local
2583 	al_reg_write32(&regs->port_regs->iatu.index, reg);  in al_pcie_atu_region_get_fields()
2585 	*base_addr = al_reg_read32(&regs->port_regs->iatu.lower_base_addr);  in al_pcie_atu_region_get_fields()
2586 	high_addr = al_reg_read32(&regs->port_regs->iatu.upper_base_addr);  in al_pcie_atu_region_get_fields()
2590 	*target_addr = al_reg_read32(&regs->port_regs->iatu.lower_target_addr);  in al_pcie_atu_region_get_fields()
2591 	high_addr = al_reg_read32(&regs->port_regs->iatu.upper_target_addr);  in al_pcie_atu_region_get_fields()
2595 	reg = al_reg_read32(&regs->port_regs->iatu.cr1);  in al_pcie_atu_region_get_fields()
2605 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_axi_io_config()  local
2607 	al_reg_write32(regs->axi.ob_ctrl.io_start_h,  in al_pcie_axi_io_config()
2610 	al_reg_write32(regs->axi.ob_ctrl.io_start_l,  in al_pcie_axi_io_config()
2613 	al_reg_write32(regs->axi.ob_ctrl.io_limit_h,  in al_pcie_axi_io_config()
2616 	al_reg_write32(regs->axi.ob_ctrl.io_limit_l,  in al_pcie_axi_io_config()
2619 	al_reg_write32_masked(regs->axi.ctrl.slv_ctl,  in al_pcie_axi_io_config()
2628 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_pf_flr_done_gen()  local
2631 	al_reg_write32_masked(regs->app.global_ctrl.events_gen[pf_num],  in al_pcie_pf_flr_done_gen()
2635 	al_reg_write32_masked(regs->app.global_ctrl.events_gen[pf_num],  in al_pcie_pf_flr_done_gen()
2648 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_legacy_int_gen()  local
2653 	reg = al_reg_read32(regs->app.global_ctrl.events_gen[pf_num]);  in al_pcie_legacy_int_gen()
2655 	al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);  in al_pcie_legacy_int_gen()
2664 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_msi_int_gen()  local
2669 	reg = al_reg_read32(regs->app.global_ctrl.events_gen[pf_num]);  in al_pcie_msi_int_gen()
2675 	al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);  in al_pcie_msi_int_gen()
2678 	al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);  in al_pcie_msi_int_gen()
2689 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_msix_config()  local
2695 	msix_reg0 = al_reg_read32(regs->core_space[pf_num].msix_cap_base);  in al_pcie_msix_config()
2700 	al_reg_write32(regs->core_space[pf_num].msix_cap_base, msix_reg0);  in al_pcie_msix_config()
2703 	al_reg_write32(regs->core_space[pf_num].msix_cap_base + (AL_PCI_MSIX_TABLE >> 2),  in al_pcie_msix_config()
2707 	al_reg_write32(regs->core_space[pf_num].msix_cap_base + (AL_PCI_MSIX_PBA >> 2),  in al_pcie_msix_config()
2720 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_msix_enabled()  local
2721 	uint32_t msix_reg0 = al_reg_read32(regs->core_space[pcie_pf->pf_num].msix_cap_base);  in al_pcie_msix_enabled()
2732 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_msix_masked()  local
2733 	uint32_t msix_reg0 = al_reg_read32(regs->core_space[pcie_pf->pf_num].msix_cap_base);  in al_pcie_msix_masked()
2749 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_aer_config_aux()  local
2750 	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;  in al_pcie_aer_config_aux()
2791 		regs->core_space[pf_num].pcie_dev_ctrl_status,  in al_pcie_aer_config_aux()
2818 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_aer_uncorr_get_and_clear_aux()  local
2819 	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;  in al_pcie_aer_uncorr_get_and_clear_aux()
2834 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_aer_corr_get_and_clear_aux()  local
2835 	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;  in al_pcie_aer_corr_get_and_clear_aux()
2855 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_aer_err_tlp_hdr_get_aux()  local
2856 	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;  in al_pcie_aer_err_tlp_hdr_get_aux()
2972 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_local_pipe_loopback_enter()  local
2976 	al_reg_write32_masked(&regs->port_regs->pipe_loopback_ctrl,  in al_pcie_local_pipe_loopback_enter()
2980 	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_local_pipe_loopback_enter()
2996 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_local_pipe_loopback_exit()  local
3000 	al_reg_write32_masked(&regs->port_regs->pipe_loopback_ctrl,  in al_pcie_local_pipe_loopback_exit()
3004 	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_local_pipe_loopback_exit()
3014 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_remote_loopback_enter()  local
3018 	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_remote_loopback_enter()
3034 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_remote_loopback_exit()  local
3038 	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_remote_loopback_exit()