1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
72 /** RC - Revisions 1/2 */
77 /** EP - Revisions 1/2 */
82 /** RC - Revision 3 */
87 /** EP - Revision 3 */
96 #define AL_PCIE_PARSE_LANES(v)		(((1 << v) - 1) << \
113 	al_reg_write32(&pcie_port->regs->port_regs->rd_only_wr_en,  in al_pcie_port_wr_to_ro_set()
131 		(pcie_port->rev_id == AL_PCIE_REV_ID_3) ? 0x4000 : 0x1000;  in al_reg_write32_dbi_cs2()
154 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_link_speed_ctrl_set()
161 			(uint32_t __iomem *)(regs->core_space[0].pcie_link_cap_base),  in al_pcie_port_link_speed_ctrl_set()
164 			(uint32_t __iomem *)(regs->core_space[0].pcie_cap_base  in al_pcie_port_link_speed_ctrl_set()
177 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_link_config()
178 	uint8_t max_lanes = pcie_port->max_lanes;  in al_pcie_port_link_config()
180 	if ((link_params->max_payload_size != AL_PCIE_MPS_DEFAULT)	&&  in al_pcie_port_link_config()
181 	    (link_params->max_payload_size != AL_PCIE_MPS_128)		&&  in al_pcie_port_link_config()
182 	    (link_params->max_payload_size != AL_PCIE_MPS_256)) {  in al_pcie_port_link_config()
183 		al_err("PCIe %d: unsupported Max Payload Size (%u)\n",  in al_pcie_port_link_config()
184 		       pcie_port->port_id, link_params->max_payload_size);  in al_pcie_port_link_config()
185 		return -EINVAL;  in al_pcie_port_link_config()
188 	al_pcie_port_link_speed_ctrl_set(pcie_port, link_params->max_speed);  in al_pcie_port_link_config()
193 	if (link_params->max_payload_size != AL_PCIE_MPS_DEFAULT)  in al_pcie_port_link_config()
194 		al_reg_write32_masked(regs->core_space[0].pcie_dev_ctrl_status,  in al_pcie_port_link_config()
196 				      link_params->max_payload_size <<  in al_pcie_port_link_config()
199 	/** Snap from PCIe core spec:  in al_pcie_port_link_config()
213 	al_reg_write32_masked(&regs->port_regs->gen2_ctrl,  in al_pcie_port_link_config()
216 	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_port_link_config()
218 				(max_lanes + (max_lanes-1))  in al_pcie_port_link_config()
229 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_ram_parity_int_config()
231 	al_reg_write32(&regs->app.parity->en_core,  in al_pcie_port_ram_parity_int_config()
234 	al_reg_write32_masked(&regs->app.int_grp_b->mask,  in al_pcie_port_ram_parity_int_config()
246 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_axi_parity_int_config()
258 	if (pcie_port->rev_id >= AL_PCIE_REV_ID_3)  in al_pcie_port_axi_parity_int_config()
261 	al_reg_write32(regs->axi.parity.en_axi,  in al_pcie_port_axi_parity_int_config()
264 	if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {  in al_pcie_port_axi_parity_int_config()
265 		al_reg_write32_masked(regs->axi.ctrl.global,  in al_pcie_port_axi_parity_int_config()
277 		al_reg_write32_masked(regs->axi.ctrl.global,  in al_pcie_port_axi_parity_int_config()
290 	al_reg_write32_masked(&regs->axi.int_grp_a->mask,  in al_pcie_port_axi_parity_int_config()
309 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_relaxed_pcie_ordering_config()
313 	 *  - RC: Rx relaxed ordering only  in al_pcie_port_relaxed_pcie_ordering_config()
314 	 *  - EP: TX relaxed ordering only  in al_pcie_port_relaxed_pcie_ordering_config()
320 		tx_relaxed_ordering = relaxed_ordering_params->enable_tx_relaxed_ordering;  in al_pcie_port_relaxed_pcie_ordering_config()
321 		rx_relaxed_ordering = relaxed_ordering_params->enable_rx_relaxed_ordering;  in al_pcie_port_relaxed_pcie_ordering_config()
324 	/** PCIe ordering:  in al_pcie_port_relaxed_pcie_ordering_config()
325 	 *  - disable outbound completion must be stalled behind outbound write  in al_pcie_port_relaxed_pcie_ordering_config()
326 	 *    ordering rule enforcement is disabled for root-port  in al_pcie_port_relaxed_pcie_ordering_config()
327 	 *  - disables read completion on the master port push slave writes for end-point  in al_pcie_port_relaxed_pcie_ordering_config()
330 		regs->axi.ordering.pos_cntl,  in al_pcie_port_relaxed_pcie_ordering_config()
354 	chip_id = al_reg_read32(&pbs_regs->unit.chip_id);  in al_pcie_rev_id_get()
366 		dev_id = al_reg_read32(&regs->axi.device_id.device_rev_id) &  in al_pcie_rev_id_get()
375 			return -EINVAL;  in al_pcie_rev_id_get()
380 		return -EINVAL;  in al_pcie_rev_id_get()
390 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_lat_rply_timers_config()
393 	AL_REG_FIELD_SET(reg, 0xFFFF, 0, lat_rply_timers->round_trip_lat_limit);  in al_pcie_port_lat_rply_timers_config()
394 	AL_REG_FIELD_SET(reg, 0xFFFF0000, 16, lat_rply_timers->replay_timer_limit);  in al_pcie_port_lat_rply_timers_config()
396 	al_reg_write32(&regs->port_regs->ack_lat_rply_timer, reg);  in al_pcie_port_lat_rply_timers_config()
409 		if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {  in al_pcie_ib_hcrd_os_ob_reads_config_default()
431 		if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {  in al_pcie_ib_hcrd_os_ob_reads_config_default()
453 …al_err("PCIe %d: outstanding outbound transactions could not be configured - unknown operating mod…  in al_pcie_ib_hcrd_os_ob_reads_config_default()
454 			pcie_port->port_id);  in al_pcie_ib_hcrd_os_ob_reads_config_default()
467 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_check_link()
471 	info_0 = al_reg_read32(&regs->app.debug->info_0);  in al_pcie_check_link()
477 	al_dbg("PCIe %d: Port Debug 0: 0x%08x. LTSSM state :0x%x\n",  in al_pcie_check_link()
478 		pcie_port->port_id, info_0, ltssm_state);  in al_pcie_check_link()
493 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_gen2_params_config()
496 	al_dbg("PCIe %d: Gen2 params config: Tx Swing %s, interrupt on link Eq %s, set Deemphasis %s\n",  in al_pcie_port_gen2_params_config()
497 	       pcie_port->port_id,  in al_pcie_port_gen2_params_config()
498 	       gen2_params->tx_swing_low ? "Low" : "Full",  in al_pcie_port_gen2_params_config()
499 	       gen2_params->tx_compliance_receive_enable? "enable" : "disable",  in al_pcie_port_gen2_params_config()
500 	       gen2_params->set_deemphasis? "enable" : "disable");  in al_pcie_port_gen2_params_config()
502 	gen2_ctrl = al_reg_read32(&regs->port_regs->gen2_ctrl);  in al_pcie_port_gen2_params_config()
504 	if (gen2_params->tx_swing_low)  in al_pcie_port_gen2_params_config()
509 	if (gen2_params->tx_compliance_receive_enable)  in al_pcie_port_gen2_params_config()
514 	if (gen2_params->set_deemphasis)  in al_pcie_port_gen2_params_config()
519 	al_reg_write32(&regs->port_regs->gen2_ctrl, gen2_ctrl);  in al_pcie_port_gen2_params_config()
530 	eq_control = eq_params->downstream_port_transmitter_preset & 0xF;  in gen3_lane_eq_param_to_val()
531 	eq_control |= (eq_params->downstream_port_receiver_preset_hint & 0x7) << 4;  in gen3_lane_eq_param_to_val()
532 	eq_control |= (eq_params->upstream_port_transmitter_preset & 0xF) << 8;  in gen3_lane_eq_param_to_val()
533 	eq_control |= (eq_params->upstream_port_receiver_preset_hint & 0x7) << 12;  in gen3_lane_eq_param_to_val()
542 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_gen3_params_config()
544 …uint16_t __iomem *lanes_eq_base = (uint16_t __iomem *)(regs->core_space[0].pcie_sec_ext_cap_base +…  in al_pcie_port_gen3_params_config()
547 	al_dbg("PCIe %d: Gen3 params config: Equalization %s, interrupt on link Eq %s\n",  in al_pcie_port_gen3_params_config()
548 	       pcie_port->port_id,  in al_pcie_port_gen3_params_config()
549 	       gen3_params->perform_eq ? "enable" : "disable",  in al_pcie_port_gen3_params_config()
550 	       gen3_params->interrupt_enable_on_link_eq_request? "enable" : "disable");  in al_pcie_port_gen3_params_config()
552 	if (gen3_params->perform_eq)  in al_pcie_port_gen3_params_config()
554 	if (gen3_params->interrupt_enable_on_link_eq_request)  in al_pcie_port_gen3_params_config()
557 	al_reg_write32(regs->core_space[0].pcie_sec_ext_cap_base + (4 >> 2),  in al_pcie_port_gen3_params_config()
562 	for (i = 0; i < gen3_params->eq_params_elements; i += 2) {  in al_pcie_port_gen3_params_config()
564 			(uint32_t)gen3_lane_eq_param_to_val(gen3_params->eq_params + i) |  in al_pcie_port_gen3_params_config()
565 			(uint32_t)gen3_lane_eq_param_to_val(gen3_params->eq_params + i + 1) << 16;  in al_pcie_port_gen3_params_config()
567 		al_dbg("PCIe %d: Set EQ (0x%08x) for lane %d, %d\n", pcie_port->port_id, eq_control, i, i + 1);  in al_pcie_port_gen3_params_config()
573 	reg = al_reg_read32(&regs->port_regs->gen3_ctrl);  in al_pcie_port_gen3_params_config()
574 	if (gen3_params->eq_disable)  in al_pcie_port_gen3_params_config()
579 	if (gen3_params->eq_phase2_3_disable)  in al_pcie_port_gen3_params_config()
584 	al_reg_write32(&regs->port_regs->gen3_ctrl, reg);  in al_pcie_port_gen3_params_config()
589 			 gen3_params->local_lf);  in al_pcie_port_gen3_params_config()
592 			 gen3_params->local_fs);  in al_pcie_port_gen3_params_config()
594 	al_reg_write32(&regs->port_regs->gen3_eq_fs_lf, reg);  in al_pcie_port_gen3_params_config()
599 			 gen3_params->local_lf);  in al_pcie_port_gen3_params_config()
602 			 gen3_params->local_fs);  in al_pcie_port_gen3_params_config()
603 	al_reg_write32(regs->axi.conf.zero_lane0, reg);  in al_pcie_port_gen3_params_config()
604 	al_reg_write32(regs->axi.conf.zero_lane1, reg);  in al_pcie_port_gen3_params_config()
605 	al_reg_write32(regs->axi.conf.zero_lane2, reg);  in al_pcie_port_gen3_params_config()
606 	al_reg_write32(regs->axi.conf.zero_lane3, reg);  in al_pcie_port_gen3_params_config()
607 	if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {  in al_pcie_port_gen3_params_config()
608 		al_reg_write32(regs->axi.conf.zero_lane4, reg);  in al_pcie_port_gen3_params_config()
609 		al_reg_write32(regs->axi.conf.zero_lane5, reg);  in al_pcie_port_gen3_params_config()
610 		al_reg_write32(regs->axi.conf.zero_lane6, reg);  in al_pcie_port_gen3_params_config()
611 		al_reg_write32(regs->axi.conf.zero_lane7, reg);  in al_pcie_port_gen3_params_config()
616 	 * - Preset Request Vector - request 9  in al_pcie_port_gen3_params_config()
617 	 * - Behavior After 24 ms Timeout (when optimal settings are not  in al_pcie_port_gen3_params_config()
619 	 * - Phase2_3 2 ms Timeout Disable  in al_pcie_port_gen3_params_config()
620 	 * - Feedback Mode - Figure Of Merit  in al_pcie_port_gen3_params_config()
623 	al_reg_write32(&regs->port_regs->gen3_eq_ctrl, reg);  in al_pcie_port_gen3_params_config()
632 	struct al_pcie_port *pcie_port = pcie_pf->pcie_port;  in al_pcie_port_pf_params_config()
633 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_pf_params_config()
634 	unsigned int pf_num = pcie_pf->pf_num;  in al_pcie_port_pf_params_config()
641 	if (pf_params->cap_d1_d3hot_dis)  in al_pcie_port_pf_params_config()
643 			regs->core_space[pf_num].pcie_pm_cap_base,  in al_pcie_port_pf_params_config()
647 	if (pf_params->cap_flr_dis)  in al_pcie_port_pf_params_config()
649 			regs->core_space[pf_num].pcie_dev_cap_base,  in al_pcie_port_pf_params_config()
653 			regs->core_space[pcie_pf->pf_num].pcie_dev_cap_base,  in al_pcie_port_pf_params_config()
657 	if (pf_params->cap_aspm_dis) {  in al_pcie_port_pf_params_config()
659 			regs->core_space[pf_num].pcie_cap_base + (AL_PCI_EXP_LNKCAP >> 2),  in al_pcie_port_pf_params_config()
663 	if (!pf_params->bar_params_valid) {  in al_pcie_port_pf_params_config()
669 		const struct al_pcie_ep_bar_params *params = pf_params->bar_params + bar_idx;  in al_pcie_port_pf_params_config()
672 …uint32_t __iomem *bar_addr = &regs->core_space[pf_num].config_header[(AL_PCI_BASE_ADDRESS_0 >> 2) …  in al_pcie_port_pf_params_config()
674 		if (params->enable) {  in al_pcie_port_pf_params_config()
675 			uint64_t size = params->size;  in al_pcie_port_pf_params_config()
677 			if (params->memory_64_bit) {  in al_pcie_port_pf_params_config()
681 					ret = -EINVAL;  in al_pcie_port_pf_params_config()
686 				if (next_params->enable) {  in al_pcie_port_pf_params_config()
687 					ret = -EINVAL;  in al_pcie_port_pf_params_config()
692 				if (!params->memory_space) {  in al_pcie_port_pf_params_config()
693 					ret = -EINVAL;  in al_pcie_port_pf_params_config()
698 					return -EINVAL;  in al_pcie_port_pf_params_config()
700 				if (params->memory_is_prefetchable) {  in al_pcie_port_pf_params_config()
701 					ret = -EINVAL;  in al_pcie_port_pf_params_config()
706 			if (params->memory_space) {  in al_pcie_port_pf_params_config()
708 					al_err("PCIe %d: memory BAR %d: size (0x%jx) less that minimal allowed value\n",  in al_pcie_port_pf_params_config()
709 						pcie_port->port_id, bar_idx,  in al_pcie_port_pf_params_config()
711 					ret = -EINVAL;  in al_pcie_port_pf_params_config()
716 				if (params->memory_is_prefetchable) {  in al_pcie_port_pf_params_config()
717 					ret = -EINVAL;  in al_pcie_port_pf_params_config()
722 					al_err("PCIe %d: IO BAR %d: size (0x%jx) less that minimal allowed value\n",  in al_pcie_port_pf_params_config()
723 						pcie_port->port_id, bar_idx,  in al_pcie_port_pf_params_config()
725 					ret = -EINVAL;  in al_pcie_port_pf_params_config()
731 			if (size & (size - 1)) {  in al_pcie_port_pf_params_config()
732 				al_err("PCIe %d: BAR %d:size (0x%jx) must be "  in al_pcie_port_pf_params_config()
734 					pcie_port->port_id, bar_idx, (uintmax_t)size);  in al_pcie_port_pf_params_config()
735 				ret = -EINVAL;  in al_pcie_port_pf_params_config()
739 			/* If BAR is 64-bit, disable the next BAR before  in al_pcie_port_pf_params_config()
742 			if (params->memory_64_bit)  in al_pcie_port_pf_params_config()
746 			mask |= (params->size - 1) & 0xFFFFFFFF;  in al_pcie_port_pf_params_config()
750 			if (params->memory_space == AL_FALSE)  in al_pcie_port_pf_params_config()
752 			if (params->memory_64_bit)  in al_pcie_port_pf_params_config()
754 			if (params->memory_is_prefetchable)  in al_pcie_port_pf_params_config()
758 			if (params->memory_64_bit) {  in al_pcie_port_pf_params_config()
759 				mask = ((params->size - 1) >> 32) & 0xFFFFFFFF;  in al_pcie_port_pf_params_config()
766 		if (params->enable && params->memory_64_bit)  in al_pcie_port_pf_params_config()
772 	if (pf_params->exp_bar_params.enable) {  in al_pcie_port_pf_params_config()
773 		if (pcie_port->rev_id != AL_PCIE_REV_ID_3) {  in al_pcie_port_pf_params_config()
774 			al_err("PCIe %d: Expansion BAR enable not supported\n", pcie_port->port_id);  in al_pcie_port_pf_params_config()
775 			ret = -ENOSYS;  in al_pcie_port_pf_params_config()
780 			&regs->core_space[pf_num].config_header[AL_PCI_EXP_ROM_BASE_ADDRESS >> 2];  in al_pcie_port_pf_params_config()
782 			mask |= (pf_params->exp_bar_params.size - 1) & 0xFFFFFFFF;  in al_pcie_port_pf_params_config()
785 	} else if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {  in al_pcie_port_pf_params_config()
788 			&regs->core_space[pf_num].config_header[AL_PCI_EXP_ROM_BASE_ADDRESS >> 2];  in al_pcie_port_pf_params_config()
792 	/* Open CPU generated msi and legacy interrupts in pcie wrapper logic */  in al_pcie_port_pf_params_config()
793 	if (pcie_port->rev_id == AL_PCIE_REV_ID_1) {  in al_pcie_port_pf_params_config()
794 		al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_0, (1 << 21));  in al_pcie_port_pf_params_config()
795 	} else if ((pcie_port->rev_id == AL_PCIE_REV_ID_2) ||  in al_pcie_port_pf_params_config()
796 		(pcie_port->rev_id == AL_PCIE_REV_ID_3)) {  in al_pcie_port_pf_params_config()
797 		al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_3, (1 << 18));  in al_pcie_port_pf_params_config()
800 		ret = -ENOSYS;  in al_pcie_port_pf_params_config()
819 	if (pcie_port->rev_id == AL_PCIE_REV_ID_1) {  in al_pcie_port_pf_params_config()
820 		al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22));  in al_pcie_port_pf_params_config()
821 	} else if ((pcie_port->rev_id == AL_PCIE_REV_ID_2) ||  in al_pcie_port_pf_params_config()
822 		(pcie_port->rev_id == AL_PCIE_REV_ID_3)) {  in al_pcie_port_pf_params_config()
823 		al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_3, (1 << 19));  in al_pcie_port_pf_params_config()
826 		ret = -ENOSYS;  in al_pcie_port_pf_params_config()
845 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_sris_config()
847 	if (sris_params->use_defaults) {  in al_pcie_port_sris_config()
848 		sris_params->kp_counter_gen3 = (pcie_port->rev_id > AL_PCIE_REV_ID_1) ?  in al_pcie_port_sris_config()
850 		sris_params->kp_counter_gen21 = PCIE_SRIS_KP_COUNTER_GEN21_DEFAULT_VAL;  in al_pcie_port_sris_config()
852 		al_dbg("PCIe %d: configuring SRIS with default values kp_gen3[%d] kp_gen21[%d]\n",  in al_pcie_port_sris_config()
853 			pcie_port->port_id,  in al_pcie_port_sris_config()
854 			sris_params->kp_counter_gen3,  in al_pcie_port_sris_config()
855 			sris_params->kp_counter_gen21);  in al_pcie_port_sris_config()
858 	switch (pcie_port->rev_id) {  in al_pcie_port_sris_config()
860 		al_reg_write32_masked(&regs->app.cfg_func_ext->cfg,  in al_pcie_port_sris_config()
864 		al_reg_write32_masked(regs->app.global_ctrl.sris_kp_counter,  in al_pcie_port_sris_config()
868 			(sris_params->kp_counter_gen3 <<  in al_pcie_port_sris_config()
870 			(sris_params->kp_counter_gen21 <<  in al_pcie_port_sris_config()
876 		if ((link_speed == AL_PCIE_LINK_SPEED_GEN3) && (sris_params->kp_counter_gen3)) {  in al_pcie_port_sris_config()
877 			al_err("PCIe %d: cannot config Gen%d SRIS with rev_id[%d]\n",  in al_pcie_port_sris_config()
878 				pcie_port->port_id, al_pcie_speed_gen_code(link_speed),  in al_pcie_port_sris_config()
879 				pcie_port->rev_id);  in al_pcie_port_sris_config()
880 			return -EINVAL;  in al_pcie_port_sris_config()
883 		al_reg_write32_masked(&regs->port_regs->filter_mask_reg_1,  in al_pcie_port_sris_config()
885 			sris_params->kp_counter_gen21);  in al_pcie_port_sris_config()
889 		al_err("PCIe %d: SRIS config is not supported in rev_id[%d]\n",  in al_pcie_port_sris_config()
890 			pcie_port->port_id, pcie_port->rev_id);  in al_pcie_port_sris_config()
892 		return -EINVAL;  in al_pcie_port_sris_config()
901 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_ib_hcrd_config()
904 		&regs->port_regs->vc0_posted_rcv_q_ctrl,  in al_pcie_port_ib_hcrd_config()
906 		(pcie_port->ib_hcrd_config.nof_p_hdr - 1)  in al_pcie_port_ib_hcrd_config()
910 		&regs->port_regs->vc0_non_posted_rcv_q_ctrl,  in al_pcie_port_ib_hcrd_config()
912 		(pcie_port->ib_hcrd_config.nof_np_hdr - 1)  in al_pcie_port_ib_hcrd_config()
919 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_max_num_of_pfs_get()
927 	if ((pcie_port->rev_id == AL_PCIE_REV_ID_3)  in al_pcie_port_max_num_of_pfs_get()
929 		max_func_num = al_reg_read32(&regs->port_regs->timer_ctrl_max_func_num);  in al_pcie_port_max_num_of_pfs_get()
939 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_ecrc_gen_ob_atu_enable()
940 	int max_ob_atu = (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?  in al_pcie_ecrc_gen_ob_atu_enable()
949 		al_reg_write32(&regs->port_regs->iatu.index, reg);  in al_pcie_ecrc_gen_ob_atu_enable()
950 		reg = al_reg_read32(&regs->port_regs->iatu.cr2);  in al_pcie_ecrc_gen_ob_atu_enable()
952 		reg = al_reg_read32(&regs->port_regs->iatu.cr1);  in al_pcie_ecrc_gen_ob_atu_enable()
959 			al_reg_write32(&regs->port_regs->iatu.cr1, reg);  in al_pcie_ecrc_gen_ob_atu_enable()
968 /*************************** PCIe Initialization API **************************/
971  * Initializes a PCIe port handle structure
984 	pcie_port->pcie_reg_base = pcie_reg_base;  in al_pcie_port_handle_init()
985 	pcie_port->regs = &pcie_port->regs_ptrs;  in al_pcie_port_handle_init()
986 	pcie_port->ex_regs = NULL;  in al_pcie_port_handle_init()
987 	pcie_port->pbs_regs = pbs_reg_base;  in al_pcie_port_handle_init()
988 	pcie_port->port_id = port_id;  in al_pcie_port_handle_init()
989 	pcie_port->max_lanes = 0;  in al_pcie_port_handle_init()
995 	pcie_port->rev_id = ret;  in al_pcie_port_handle_init()
998 	al_memset(pcie_port->regs, 0, sizeof(struct al_pcie_regs));  in al_pcie_port_handle_init()
1000 	if (pcie_port->rev_id == AL_PCIE_REV_ID_1) {  in al_pcie_port_handle_init()
1004 		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;  in al_pcie_port_handle_init()
1005 		pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;  in al_pcie_port_handle_init()
1006 		pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;  in al_pcie_port_handle_init()
1007 		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;  in al_pcie_port_handle_init()
1008 		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;  in al_pcie_port_handle_init()
1009 		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;  in al_pcie_port_handle_init()
1010 		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;  in al_pcie_port_handle_init()
1011 		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;  in al_pcie_port_handle_init()
1012 		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;  in al_pcie_port_handle_init()
1013 		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;  in al_pcie_port_handle_init()
1014 		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;  in al_pcie_port_handle_init()
1015 		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;  in al_pcie_port_handle_init()
1016 		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;  in al_pcie_port_handle_init()
1017 		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;  in al_pcie_port_handle_init()
1018 		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;  in al_pcie_port_handle_init()
1019 		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;  in al_pcie_port_handle_init()
1020 		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;  in al_pcie_port_handle_init()
1021 		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;  in al_pcie_port_handle_init()
1022 		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;  in al_pcie_port_handle_init()
1023 		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;  in al_pcie_port_handle_init()
1024 		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;  in al_pcie_port_handle_init()
1025 		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;  in al_pcie_port_handle_init()
1026 		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;  in al_pcie_port_handle_init()
1027 …pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_se…  in al_pcie_port_handle_init()
1028 		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;  in al_pcie_port_handle_init()
1029 		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;  in al_pcie_port_handle_init()
1031 		pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;  in al_pcie_port_handle_init()
1032 		pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;  in al_pcie_port_handle_init()
1033 		pcie_port->regs->app.global_ctrl.events_gen[0] = &regs->app.global_ctrl.events_gen;  in al_pcie_port_handle_init()
1034 		pcie_port->regs->app.debug = &regs->app.debug;  in al_pcie_port_handle_init()
1035 		pcie_port->regs->app.soc_int[0].status_0 = &regs->app.soc_int.status_0;  in al_pcie_port_handle_init()
1036 		pcie_port->regs->app.soc_int[0].status_1 = &regs->app.soc_int.status_1;  in al_pcie_port_handle_init()
1037 		pcie_port->regs->app.soc_int[0].status_2 = &regs->app.soc_int.status_2;  in al_pcie_port_handle_init()
1038 		pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = &regs->app.soc_int.mask_inta_leg_0;  in al_pcie_port_handle_init()
1039 		pcie_port->regs->app.soc_int[0].mask_inta_leg_1 = &regs->app.soc_int.mask_inta_leg_1;  in al_pcie_port_handle_init()
1040 		pcie_port->regs->app.soc_int[0].mask_inta_leg_2 = &regs->app.soc_int.mask_inta_leg_2;  in al_pcie_port_handle_init()
1041 		pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = &regs->app.soc_int.mask_msi_leg_0;  in al_pcie_port_handle_init()
1042 		pcie_port->regs->app.soc_int[0].mask_msi_leg_1 = &regs->app.soc_int.mask_msi_leg_1;  in al_pcie_port_handle_init()
1043 		pcie_port->regs->app.soc_int[0].mask_msi_leg_2 = &regs->app.soc_int.mask_msi_leg_2;  in al_pcie_port_handle_init()
1044 		pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;  in al_pcie_port_handle_init()
1045 		pcie_port->regs->app.parity = &regs->app.parity;  in al_pcie_port_handle_init()
1046 		pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;  in al_pcie_port_handle_init()
1047 		pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;  in al_pcie_port_handle_init()
1048 		pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;  in al_pcie_port_handle_init()
1049 		pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;  in al_pcie_port_handle_init()
1051 		pcie_port->regs->core_space[0].config_header = regs->core_space.config_header;  in al_pcie_port_handle_init()
1052 		pcie_port->regs->core_space[0].pcie_pm_cap_base = &regs->core_space.pcie_pm_cap_base;  in al_pcie_port_handle_init()
1053 		pcie_port->regs->core_space[0].pcie_cap_base = &regs->core_space.pcie_cap_base;  in al_pcie_port_handle_init()
1054 		pcie_port->regs->core_space[0].pcie_dev_cap_base = &regs->core_space.pcie_dev_cap_base;  in al_pcie_port_handle_init()
1055 		pcie_port->regs->core_space[0].pcie_dev_ctrl_status = &regs->core_space.pcie_dev_ctrl_status;  in al_pcie_port_handle_init()
1056 		pcie_port->regs->core_space[0].pcie_link_cap_base = &regs->core_space.pcie_link_cap_base;  in al_pcie_port_handle_init()
1057 		pcie_port->regs->core_space[0].msix_cap_base = &regs->core_space.msix_cap_base;  in al_pcie_port_handle_init()
1058 		pcie_port->regs->core_space[0].aer = &regs->core_space.aer;  in al_pcie_port_handle_init()
1059 		pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.pcie_sec_ext_cap_base;  in al_pcie_port_handle_init()
1061 		pcie_port->regs->port_regs = &regs->core_space.port_regs;  in al_pcie_port_handle_init()
1063 	} else if (pcie_port->rev_id == AL_PCIE_REV_ID_2) {  in al_pcie_port_handle_init()
1067 		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;  in al_pcie_port_handle_init()
1068 		pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;  in al_pcie_port_handle_init()
1069 		pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;  in al_pcie_port_handle_init()
1070 		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;  in al_pcie_port_handle_init()
1071 		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;  in al_pcie_port_handle_init()
1072 		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;  in al_pcie_port_handle_init()
1073 		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;  in al_pcie_port_handle_init()
1074 		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;  in al_pcie_port_handle_init()
1075 		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;  in al_pcie_port_handle_init()
1076 		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;  in al_pcie_port_handle_init()
1077 		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;  in al_pcie_port_handle_init()
1078 		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;  in al_pcie_port_handle_init()
1079 		pcie_port->regs->axi.ob_ctrl.tgtid_reg_ovrd = &regs->axi.ob_ctrl.tgtid_reg_ovrd;  in al_pcie_port_handle_init()
1080 		pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_sel = &regs->axi.ob_ctrl.addr_high_reg_ovrd_sel;  in al_pcie_port_handle_init()
1081 …pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_value = &regs->axi.ob_ctrl.addr_high_reg_ovrd_valu…  in al_pcie_port_handle_init()
1082 		pcie_port->regs->axi.ob_ctrl.addr_size_replace = &regs->axi.ob_ctrl.addr_size_replace;  in al_pcie_port_handle_init()
1083 		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;  in al_pcie_port_handle_init()
1084 		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;  in al_pcie_port_handle_init()
1085 		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;  in al_pcie_port_handle_init()
1086 		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;  in al_pcie_port_handle_init()
1087 		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;  in al_pcie_port_handle_init()
1088 		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;  in al_pcie_port_handle_init()
1089 		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;  in al_pcie_port_handle_init()
1090 		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;  in al_pcie_port_handle_init()
1091 		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;  in al_pcie_port_handle_init()
1092 		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;  in al_pcie_port_handle_init()
1093 		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;  in al_pcie_port_handle_init()
1094 …pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_se…  in al_pcie_port_handle_init()
1095 		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;  in al_pcie_port_handle_init()
1096 		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;  in al_pcie_port_handle_init()
1098 		pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;  in al_pcie_port_handle_init()
1099 		pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;  in al_pcie_port_handle_init()
1100 		pcie_port->regs->app.global_ctrl.events_gen[0] = &regs->app.global_ctrl.events_gen;  in al_pcie_port_handle_init()
1101 …pcie_port->regs->app.global_ctrl.corr_err_sts_int = &regs->app.global_ctrl.pended_corr_err_sts_int;  in al_pcie_port_handle_init()
1102 …pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = &regs->app.global_ctrl.pended_uncorr_err_sts…  in al_pcie_port_handle_init()
1103 		pcie_port->regs->app.global_ctrl.sris_kp_counter = &regs->app.global_ctrl.sris_kp_counter_value;  in al_pcie_port_handle_init()
1104 		pcie_port->regs->app.debug = &regs->app.debug;  in al_pcie_port_handle_init()
1105 		pcie_port->regs->app.ap_user_send_msg = &regs->app.ap_user_send_msg;  in al_pcie_port_handle_init()
1106 		pcie_port->regs->app.soc_int[0].status_0 = &regs->app.soc_int.status_0;  in al_pcie_port_handle_init()
1107 		pcie_port->regs->app.soc_int[0].status_1 = &regs->app.soc_int.status_1;  in al_pcie_port_handle_init()
1108 		pcie_port->regs->app.soc_int[0].status_2 = &regs->app.soc_int.status_2;  in al_pcie_port_handle_init()
1109 		pcie_port->regs->app.soc_int[0].status_3 = &regs->app.soc_int.status_3;  in al_pcie_port_handle_init()
1110 		pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = &regs->app.soc_int.mask_inta_leg_0;  in al_pcie_port_handle_init()
1111 		pcie_port->regs->app.soc_int[0].mask_inta_leg_1 = &regs->app.soc_int.mask_inta_leg_1;  in al_pcie_port_handle_init()
1112 		pcie_port->regs->app.soc_int[0].mask_inta_leg_2 = &regs->app.soc_int.mask_inta_leg_2;  in al_pcie_port_handle_init()
1113 		pcie_port->regs->app.soc_int[0].mask_inta_leg_3 = &regs->app.soc_int.mask_inta_leg_3;  in al_pcie_port_handle_init()
1114 		pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = &regs->app.soc_int.mask_msi_leg_0;  in al_pcie_port_handle_init()
1115 		pcie_port->regs->app.soc_int[0].mask_msi_leg_1 = &regs->app.soc_int.mask_msi_leg_1;  in al_pcie_port_handle_init()
1116 		pcie_port->regs->app.soc_int[0].mask_msi_leg_2 = &regs->app.soc_int.mask_msi_leg_2;  in al_pcie_port_handle_init()
1117 		pcie_port->regs->app.soc_int[0].mask_msi_leg_3 = &regs->app.soc_int.mask_msi_leg_3;  in al_pcie_port_handle_init()
1118 		pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;  in al_pcie_port_handle_init()
1119 		pcie_port->regs->app.parity = &regs->app.parity;  in al_pcie_port_handle_init()
1120 		pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;  in al_pcie_port_handle_init()
1121 		pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;  in al_pcie_port_handle_init()
1122 		pcie_port->regs->app.status_per_func[0] = &regs->app.status_per_func;  in al_pcie_port_handle_init()
1123 		pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;  in al_pcie_port_handle_init()
1124 		pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;  in al_pcie_port_handle_init()
1126 		pcie_port->regs->core_space[0].config_header = regs->core_space.config_header;  in al_pcie_port_handle_init()
1127 		pcie_port->regs->core_space[0].pcie_pm_cap_base = &regs->core_space.pcie_pm_cap_base;  in al_pcie_port_handle_init()
1128 		pcie_port->regs->core_space[0].pcie_cap_base = &regs->core_space.pcie_cap_base;  in al_pcie_port_handle_init()
1129 		pcie_port->regs->core_space[0].pcie_dev_cap_base = &regs->core_space.pcie_dev_cap_base;  in al_pcie_port_handle_init()
1130 		pcie_port->regs->core_space[0].pcie_dev_ctrl_status = &regs->core_space.pcie_dev_ctrl_status;  in al_pcie_port_handle_init()
1131 		pcie_port->regs->core_space[0].pcie_link_cap_base = &regs->core_space.pcie_link_cap_base;  in al_pcie_port_handle_init()
1132 		pcie_port->regs->core_space[0].msix_cap_base = &regs->core_space.msix_cap_base;  in al_pcie_port_handle_init()
1133 		pcie_port->regs->core_space[0].aer = &regs->core_space.aer;  in al_pcie_port_handle_init()
1134 		pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.pcie_sec_ext_cap_base;  in al_pcie_port_handle_init()
1136 		pcie_port->regs->port_regs = &regs->core_space.port_regs;  in al_pcie_port_handle_init()
1138 	} else if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {  in al_pcie_port_handle_init()
1141 		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;  in al_pcie_port_handle_init()
1142 		pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;  in al_pcie_port_handle_init()
1143 		pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;  in al_pcie_port_handle_init()
1144 		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;  in al_pcie_port_handle_init()
1145 		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;  in al_pcie_port_handle_init()
1146 		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;  in al_pcie_port_handle_init()
1147 		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;  in al_pcie_port_handle_init()
1148 		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;  in al_pcie_port_handle_init()
1149 		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;  in al_pcie_port_handle_init()
1150 		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;  in al_pcie_port_handle_init()
1151 		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;  in al_pcie_port_handle_init()
1152 		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;  in al_pcie_port_handle_init()
1153 		pcie_port->regs->axi.ob_ctrl.io_addr_mask_h = &regs->axi.ob_ctrl.io_addr_mask_h;  in al_pcie_port_handle_init()
1154 		pcie_port->regs->axi.ob_ctrl.ar_msg_addr_mask_h = &regs->axi.ob_ctrl.ar_msg_addr_mask_h;  in al_pcie_port_handle_init()
1155 		pcie_port->regs->axi.ob_ctrl.aw_msg_addr_mask_h = &regs->axi.ob_ctrl.aw_msg_addr_mask_h;  in al_pcie_port_handle_init()
1156 		pcie_port->regs->axi.ob_ctrl.tgtid_reg_ovrd = &regs->axi.ob_ctrl.tgtid_reg_ovrd;  in al_pcie_port_handle_init()
1157 		pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_sel = &regs->axi.ob_ctrl.addr_high_reg_ovrd_sel;  in al_pcie_port_handle_init()
1158 …pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_value = &regs->axi.ob_ctrl.addr_high_reg_ovrd_valu…  in al_pcie_port_handle_init()
1159 		pcie_port->regs->axi.ob_ctrl.addr_size_replace = &regs->axi.ob_ctrl.addr_size_replace;  in al_pcie_port_handle_init()
1160 		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;  in al_pcie_port_handle_init()
1161 		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;  in al_pcie_port_handle_init()
1162 		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;  in al_pcie_port_handle_init()
1163 		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;  in al_pcie_port_handle_init()
1164 		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;  in al_pcie_port_handle_init()
1165 		pcie_port->regs->axi.conf.zero_lane4 = &regs->axi.conf.zero_lane4;  in al_pcie_port_handle_init()
1166 		pcie_port->regs->axi.conf.zero_lane5 = &regs->axi.conf.zero_lane5;  in al_pcie_port_handle_init()
1167 		pcie_port->regs->axi.conf.zero_lane6 = &regs->axi.conf.zero_lane6;  in al_pcie_port_handle_init()
1168 		pcie_port->regs->axi.conf.zero_lane7 = &regs->axi.conf.zero_lane7;  in al_pcie_port_handle_init()
1169 		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;  in al_pcie_port_handle_init()
1170 		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;  in al_pcie_port_handle_init()
1171 		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;  in al_pcie_port_handle_init()
1172 		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;  in al_pcie_port_handle_init()
1173 		pcie_port->regs->axi.status.lane[4] = &regs->axi.status.lane4;  in al_pcie_port_handle_init()
1174 		pcie_port->regs->axi.status.lane[5] = &regs->axi.status.lane5;  in al_pcie_port_handle_init()
1175 		pcie_port->regs->axi.status.lane[6] = &regs->axi.status.lane6;  in al_pcie_port_handle_init()
1176 		pcie_port->regs->axi.status.lane[7] = &regs->axi.status.lane7;  in al_pcie_port_handle_init()
1177 		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;  in al_pcie_port_handle_init()
1178 		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;  in al_pcie_port_handle_init()
1179 …pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_se…  in al_pcie_port_handle_init()
1180 		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;  in al_pcie_port_handle_init()
1181 		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;  in al_pcie_port_handle_init()
1182 		pcie_port->regs->axi.axi_attr_ovrd.write_msg_ctrl_0 = &regs->axi.axi_attr_ovrd.write_msg_ctrl_0;  in al_pcie_port_handle_init()
1183 		pcie_port->regs->axi.axi_attr_ovrd.write_msg_ctrl_1 = &regs->axi.axi_attr_ovrd.write_msg_ctrl_1;  in al_pcie_port_handle_init()
1184 		pcie_port->regs->axi.axi_attr_ovrd.pf_sel = &regs->axi.axi_attr_ovrd.pf_sel;  in al_pcie_port_handle_init()
1187 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_0 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_0;  in al_pcie_port_handle_init()
1188 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_1 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_1;  in al_pcie_port_handle_init()
1189 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_2 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_2;  in al_pcie_port_handle_init()
1190 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_3 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_3;  in al_pcie_port_handle_init()
1191 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_4 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_4;  in al_pcie_port_handle_init()
1192 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_5 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_5;  in al_pcie_port_handle_init()
1193 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_6 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_6;  in al_pcie_port_handle_init()
1194 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_7 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_7;  in al_pcie_port_handle_init()
1195 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_8 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_8;  in al_pcie_port_handle_init()
1196 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_9 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_9;  in al_pcie_port_handle_init()
1199 		pcie_port->regs->axi.msg_attr_axuser_table.entry_vec = &regs->axi.msg_attr_axuser_table.entry_vec;  in al_pcie_port_handle_init()
1201 		pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;  in al_pcie_port_handle_init()
1202 		pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;  in al_pcie_port_handle_init()
1203 …pcie_port->regs->app.global_ctrl.corr_err_sts_int = &regs->app.global_ctrl.pended_corr_err_sts_int;  in al_pcie_port_handle_init()
1204 …pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = &regs->app.global_ctrl.pended_uncorr_err_sts…  in al_pcie_port_handle_init()
1207 			pcie_port->regs->app.global_ctrl.events_gen[i] = &regs->app.events_gen_per_func[i].events_gen;  in al_pcie_port_handle_init()
1210 		pcie_port->regs->app.global_ctrl.sris_kp_counter = &regs->app.global_ctrl.sris_kp_counter_value;  in al_pcie_port_handle_init()
1211 		pcie_port->regs->app.debug = &regs->app.debug;  in al_pcie_port_handle_init()
1214 			pcie_port->regs->app.soc_int[i].status_0 = &regs->app.soc_int_per_func[i].status_0;  in al_pcie_port_handle_init()
1215 			pcie_port->regs->app.soc_int[i].status_1 = &regs->app.soc_int_per_func[i].status_1;  in al_pcie_port_handle_init()
1216 			pcie_port->regs->app.soc_int[i].status_2 = &regs->app.soc_int_per_func[i].status_2;  in al_pcie_port_handle_init()
1217 			pcie_port->regs->app.soc_int[i].status_3 = &regs->app.soc_int_per_func[i].status_3;  in al_pcie_port_handle_init()
1218 			pcie_port->regs->app.soc_int[i].mask_inta_leg_0 = &regs->app.soc_int_per_func[i].mask_inta_leg_0;  in al_pcie_port_handle_init()
1219 			pcie_port->regs->app.soc_int[i].mask_inta_leg_1 = &regs->app.soc_int_per_func[i].mask_inta_leg_1;  in al_pcie_port_handle_init()
1220 			pcie_port->regs->app.soc_int[i].mask_inta_leg_2 = &regs->app.soc_int_per_func[i].mask_inta_leg_2;  in al_pcie_port_handle_init()
1221 			pcie_port->regs->app.soc_int[i].mask_inta_leg_3 = &regs->app.soc_int_per_func[i].mask_inta_leg_3;  in al_pcie_port_handle_init()
1222 			pcie_port->regs->app.soc_int[i].mask_msi_leg_0 = &regs->app.soc_int_per_func[i].mask_msi_leg_0;  in al_pcie_port_handle_init()
1223 			pcie_port->regs->app.soc_int[i].mask_msi_leg_1 = &regs->app.soc_int_per_func[i].mask_msi_leg_1;  in al_pcie_port_handle_init()
1224 			pcie_port->regs->app.soc_int[i].mask_msi_leg_2 = &regs->app.soc_int_per_func[i].mask_msi_leg_2;  in al_pcie_port_handle_init()
1225 			pcie_port->regs->app.soc_int[i].mask_msi_leg_3 = &regs->app.soc_int_per_func[i].mask_msi_leg_3;  in al_pcie_port_handle_init()
1228 		pcie_port->regs->app.ap_user_send_msg = &regs->app.ap_user_send_msg;  in al_pcie_port_handle_init()
1229 		pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;  in al_pcie_port_handle_init()
1230 		pcie_port->regs->app.parity = &regs->app.parity;  in al_pcie_port_handle_init()
1231 		pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;  in al_pcie_port_handle_init()
1232 		pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;  in al_pcie_port_handle_init()
1233 		pcie_port->regs->app.cfg_func_ext = &regs->app.cfg_func_ext;  in al_pcie_port_handle_init()
1236 			pcie_port->regs->app.status_per_func[i] = &regs->app.status_per_func[i];  in al_pcie_port_handle_init()
1238 		pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;  in al_pcie_port_handle_init()
1239 		pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;  in al_pcie_port_handle_init()
1240 		pcie_port->regs->app.int_grp_c = &regs->app.int_grp_c;  in al_pcie_port_handle_init()
1241 		pcie_port->regs->app.int_grp_d = &regs->app.int_grp_d;  in al_pcie_port_handle_init()
1244 			pcie_port->regs->core_space[i].config_header = regs->core_space.func[i].config_header;  in al_pcie_port_handle_init()
1245 			pcie_port->regs->core_space[i].pcie_pm_cap_base = &regs->core_space.func[i].pcie_pm_cap_base;  in al_pcie_port_handle_init()
1246 			pcie_port->regs->core_space[i].pcie_cap_base = &regs->core_space.func[i].pcie_cap_base;  in al_pcie_port_handle_init()
1247 			pcie_port->regs->core_space[i].pcie_dev_cap_base = &regs->core_space.func[i].pcie_dev_cap_base;  in al_pcie_port_handle_init()
1248 …pcie_port->regs->core_space[i].pcie_dev_ctrl_status = &regs->core_space.func[i].pcie_dev_ctrl_stat…  in al_pcie_port_handle_init()
1249 			pcie_port->regs->core_space[i].pcie_link_cap_base = &regs->core_space.func[i].pcie_link_cap_base;  in al_pcie_port_handle_init()
1250 			pcie_port->regs->core_space[i].msix_cap_base = &regs->core_space.func[i].msix_cap_base;  in al_pcie_port_handle_init()
1251 			pcie_port->regs->core_space[i].aer = &regs->core_space.func[i].aer;  in al_pcie_port_handle_init()
1252 			pcie_port->regs->core_space[i].tph_cap_base = &regs->core_space.func[i].tph_cap_base;  in al_pcie_port_handle_init()
1257 …pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.func[0].pcie_sec_ext_cap_…  in al_pcie_port_handle_init()
1259 		pcie_port->regs->port_regs = &regs->core_space.func[0].port_regs;  in al_pcie_port_handle_init()
1264 		return -EINVAL;  in al_pcie_port_handle_init()
1268 	pcie_port->max_num_of_pfs = al_pcie_port_max_num_of_pfs_get(pcie_port);  in al_pcie_port_handle_init()
1271 	pcie_port->ib_hcrd_config.nof_np_hdr = 0;  in al_pcie_port_handle_init()
1272 	pcie_port->ib_hcrd_config.nof_p_hdr = 0;  in al_pcie_port_handle_init()
1274 	al_dbg("pcie port handle initialized. port id: %d, rev_id %d, regs base %p\n",  in al_pcie_port_handle_init()
1275 	       port_id, pcie_port->rev_id, pcie_reg_base);  in al_pcie_port_handle_init()
1280  * Initializes a PCIe Physical function handle structure
1291 	al_assert(pf_num < pcie_port->max_num_of_pfs);  in al_pcie_pf_handle_init()
1294 		al_err("PCIe %d: can't init PF handle with operating mode [%d]\n",  in al_pcie_pf_handle_init()
1295 			pcie_port->port_id, op_mode);  in al_pcie_pf_handle_init()
1296 		return -EINVAL;  in al_pcie_pf_handle_init()
1299 	pcie_pf->pf_num = pf_num;  in al_pcie_pf_handle_init()
1300 	pcie_pf->pcie_port = pcie_port;  in al_pcie_pf_handle_init()
1302 	al_dbg("PCIe %d: pf handle initialized. pf number: %d, rev_id %d, regs %p\n",  in al_pcie_pf_handle_init()
1303 	       pcie_port->port_id, pcie_pf->pf_num, pcie_port->rev_id,  in al_pcie_pf_handle_init()
1304 	       pcie_port->regs);  in al_pcie_pf_handle_init()
1311 	return pcie_port->rev_id;  in al_pcie_port_rev_id_get()
1314 /************************** Pre PCIe Port Enable API **************************/
1316 /** configure pcie operating mode (root complex or endpoint) */
1322 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_operating_mode_config()
1326 		al_err("PCIe %d: already enabled, cannot set operating mode\n",  in al_pcie_port_operating_mode_config()
1327 			pcie_port->port_id);  in al_pcie_port_operating_mode_config()
1328 		return -EINVAL;  in al_pcie_port_operating_mode_config()
1331 	reg = al_reg_read32(regs->axi.pcie_global.conf);  in al_pcie_port_operating_mode_config()
1341 		if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {  in al_pcie_port_operating_mode_config()
1343 			al_reg_write32_masked(regs->axi.axi_attr_ovrd.pf_sel,  in al_pcie_port_operating_mode_config()
1356 		al_err("PCIe %d: unknown operating mode: %d\n", pcie_port->port_id, mode);  in al_pcie_port_operating_mode_config()
1357 		return -EINVAL;  in al_pcie_port_operating_mode_config()
1361 		al_dbg("PCIe %d: operating mode already set to %s\n",  in al_pcie_port_operating_mode_config()
1362 		       pcie_port->port_id, (mode == AL_PCIE_OPERATING_MODE_EP) ?  in al_pcie_port_operating_mode_config()
1366 	al_dbg("PCIe %d: set operating mode to %s\n",  in al_pcie_port_operating_mode_config()
1367 		pcie_port->port_id, (mode == AL_PCIE_OPERATING_MODE_EP) ?  in al_pcie_port_operating_mode_config()
1373 	al_reg_write32(regs->axi.pcie_global.conf, reg);  in al_pcie_port_operating_mode_config()
1381 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_max_lanes_set()
1385 		al_err("PCIe %d: already enabled, cannot set max lanes\n",  in al_pcie_port_max_lanes_set()
1386 			pcie_port->port_id);  in al_pcie_port_max_lanes_set()
1387 		return -EINVAL;  in al_pcie_port_max_lanes_set()
1390 	/* convert to bitmask format (4 ->'b1111, 2 ->'b11, 1 -> 'b1) */  in al_pcie_port_max_lanes_set()
1393 	al_reg_write32_masked(regs->axi.pcie_global.conf,  in al_pcie_port_max_lanes_set()
1394 		(pcie_port->rev_id == AL_PCIE_REV_ID_3) ?  in al_pcie_port_max_lanes_set()
1399 	pcie_port->max_lanes = lanes;  in al_pcie_port_max_lanes_set()
1408 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_max_num_of_pfs_set()
1410 	if (pcie_port->rev_id == AL_PCIE_REV_ID_3)  in al_pcie_port_max_num_of_pfs_set()
1415 	pcie_port->max_num_of_pfs = max_num_of_pfs;  in al_pcie_port_max_num_of_pfs_set()
1417 	if (al_pcie_port_is_enabled(pcie_port) && (pcie_port->rev_id == AL_PCIE_REV_ID_3)) {  in al_pcie_port_max_num_of_pfs_set()
1421 			((op_mode == AL_PCIE_OPERATING_MODE_EP) && (pcie_port->max_num_of_pfs > 1));  in al_pcie_port_max_num_of_pfs_set()
1425 			&regs->port_regs->timer_ctrl_max_func_num,  in al_pcie_port_max_num_of_pfs_set()
1427 			pcie_port->max_num_of_pfs - 1);  in al_pcie_port_max_num_of_pfs_set()
1433 		 * multi-pf support so the host scan all PFs  in al_pcie_port_max_num_of_pfs_set()
1436 			(&regs->core_space[0].config_header[0] +  in al_pcie_port_max_num_of_pfs_set()
1453 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1456 		al_err("PCIe %d: already enabled, cannot configure IB credits and OB OS reads\n",  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1457 			pcie_port->port_id);  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1458 		return -EINVAL;  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1461 	al_assert(ib_hcrd_os_ob_reads_config->nof_np_hdr > 0);  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1463 	al_assert(ib_hcrd_os_ob_reads_config->nof_p_hdr > 0);  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1465 	al_assert(ib_hcrd_os_ob_reads_config->nof_cpl_hdr > 0);  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1467 	if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1469 			(ib_hcrd_os_ob_reads_config->nof_cpl_hdr +  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1470 			ib_hcrd_os_ob_reads_config->nof_np_hdr +  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1471 			ib_hcrd_os_ob_reads_config->nof_p_hdr) ==  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1475 			regs->axi.init_fc.cfg,  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1479 			(ib_hcrd_os_ob_reads_config->nof_p_hdr <<  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1481 			(ib_hcrd_os_ob_reads_config->nof_np_hdr <<  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1483 			(ib_hcrd_os_ob_reads_config->nof_cpl_hdr <<  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1487 			(ib_hcrd_os_ob_reads_config->nof_cpl_hdr +  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1488 			ib_hcrd_os_ob_reads_config->nof_np_hdr +  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1489 			ib_hcrd_os_ob_reads_config->nof_p_hdr) ==  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1493 			regs->axi.init_fc.cfg,  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1497 			(ib_hcrd_os_ob_reads_config->nof_p_hdr <<  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1499 			(ib_hcrd_os_ob_reads_config->nof_np_hdr <<  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1501 			(ib_hcrd_os_ob_reads_config->nof_cpl_hdr <<  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1506 		regs->axi.pre_configuration.pcie_core_setup,  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1508 		ib_hcrd_os_ob_reads_config->nof_outstanding_ob_reads <<  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1512 	pcie_port->ib_hcrd_config.nof_np_hdr =  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1513 		ib_hcrd_os_ob_reads_config->nof_np_hdr;  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1514 	pcie_port->ib_hcrd_config.nof_p_hdr =  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1515 		ib_hcrd_os_ob_reads_config->nof_p_hdr;  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1524 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_operating_mode_get()
1529 	reg = al_reg_read32(regs->axi.pcie_global.conf);  in al_pcie_operating_mode_get()
1541 		al_err("PCIe %d: unknown device type (%d) in global conf register.\n",  in al_pcie_operating_mode_get()
1542 			pcie_port->port_id, device_type);  in al_pcie_operating_mode_get()
1547 /* PCIe AXI quality of service configuration */
1553 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_axi_qos_config()
1560 		regs->axi.ctrl.master_arctl,  in al_pcie_axi_qos_config()
1564 		regs->axi.ctrl.master_awctl,  in al_pcie_axi_qos_config()
1569 /**************************** PCIe Port Enable API ****************************/
1571 /** Enable PCIe port (deassert reset) */
1576 				(struct al_pbs_regs *)pcie_port->pbs_regs;  in al_pcie_port_enable()
1577 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_enable()
1578 	unsigned int port_id = pcie_port->port_id;  in al_pcie_port_enable()
1580 	/* pre-port-enable default functionality should be here */  in al_pcie_port_enable()
1587 	if ((pcie_port->ib_hcrd_config.nof_np_hdr == 0) ||  in al_pcie_port_enable()
1588 			(pcie_port->ib_hcrd_config.nof_p_hdr == 0))  in al_pcie_port_enable()
1593 	 * - must be done before core reset deasserted  in al_pcie_port_enable()
1594 	 * - rev_id 0 - no effect, but no harm  in al_pcie_port_enable()
1596 	if ((pcie_port->rev_id == AL_PCIE_REV_ID_1) ||  in al_pcie_port_enable()
1597 		(pcie_port->rev_id == AL_PCIE_REV_ID_2)) {  in al_pcie_port_enable()
1599 			regs->axi.ordering.pos_cntl,  in al_pcie_port_enable()
1606 		&pbs_reg_base->unit.pcie_conf_1,  in al_pcie_port_enable()
1613 /** Disable PCIe port (assert reset) */
1618 				(struct al_pbs_regs *)pcie_port->pbs_regs;  in al_pcie_port_disable()
1619 	unsigned int port_id = pcie_port->port_id;  in al_pcie_port_disable()
1622 		al_warn("PCIe %d: trying to disable a non-enabled port\n",  in al_pcie_port_disable()
1623 			pcie_port->port_id);  in al_pcie_port_disable()
1628 		&pbs_reg_base->unit.pcie_conf_1,  in al_pcie_port_disable()
1638 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_memory_shutdown_set()
1639 	uint32_t mask = (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?  in al_pcie_port_memory_shutdown_set()
1644 		al_err("PCIe %d: not enabled, cannot shutdown memory\n",  in al_pcie_port_memory_shutdown_set()
1645 			pcie_port->port_id);  in al_pcie_port_memory_shutdown_set()
1646 		return -EINVAL;  in al_pcie_port_memory_shutdown_set()
1649 	al_reg_write32_masked(regs->axi.pcie_global.conf,  in al_pcie_port_memory_shutdown_set()
1658 	struct al_pbs_regs *pbs_reg_base = (struct al_pbs_regs *)pcie_port->pbs_regs;  in al_pcie_port_is_enabled()
1659 	uint32_t pcie_exist = al_reg_read32(&pbs_reg_base->unit.pcie_conf_1);  in al_pcie_port_is_enabled()
1665 	return (AL_REG_FIELD_GET(ports_enabled, AL_BIT(pcie_port->port_id),  in al_pcie_port_is_enabled()
1666 		pcie_port->port_id) == 1);  in al_pcie_port_is_enabled()
1669 /*************************** PCIe Configuration API ***************************/
1671 /** configure pcie port (link params, etc..) */
1676 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_config()
1682 		al_err("PCIe %d: port not enabled, cannot configure port\n",  in al_pcie_port_config()
1683 			pcie_port->port_id);  in al_pcie_port_config()
1684 		return -EINVAL;  in al_pcie_port_config()
1688 		al_err("PCIe %d: link already started, cannot configure port\n",  in al_pcie_port_config()
1689 			pcie_port->port_id);  in al_pcie_port_config()
1690 		return -EINVAL;  in al_pcie_port_config()
1696 	al_dbg("PCIe %d: port config\n", pcie_port->port_id);  in al_pcie_port_config()
1701 	if (pcie_port->max_lanes == 0) {  in al_pcie_port_config()
1702 		uint32_t global_conf = al_reg_read32(regs->axi.pcie_global.conf);  in al_pcie_port_config()
1704 			(pcie_port->rev_id == AL_PCIE_REV_ID_3) ?  in al_pcie_port_config()
1711 			pcie_port->max_lanes = 1;  in al_pcie_port_config()
1714 			pcie_port->max_lanes = 2;  in al_pcie_port_config()
1717 			pcie_port->max_lanes = 4;  in al_pcie_port_config()
1720 			pcie_port->max_lanes = 8;  in al_pcie_port_config()
1723 			pcie_port->max_lanes = 0;  in al_pcie_port_config()
1724 			al_err("PCIe %d: invalid max lanes val (0x%x)\n", pcie_port->port_id, act_lanes);  in al_pcie_port_config()
1729 	if (params->link_params)  in al_pcie_port_config()
1730 		status = al_pcie_port_link_config(pcie_port, params->link_params);  in al_pcie_port_config()
1735 	 * Max Payload Size is remained untouched- it is the responsibility of  in al_pcie_port_config()
1739 		al_reg_write32_masked(regs->core_space[i].pcie_dev_ctrl_status,  in al_pcie_port_config()
1742 		if (pcie_port->rev_id != AL_PCIE_REV_ID_3)  in al_pcie_port_config()
1746 	if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {  in al_pcie_port_config()
1751 			al_reg_write32_masked(regs->core_space[i].tph_cap_base,  in al_pcie_port_config()
1759 	status = al_pcie_port_snoop_config(pcie_port, params->enable_axi_snoop);  in al_pcie_port_config()
1763 	al_pcie_port_max_num_of_pfs_set(pcie_port, pcie_port->max_num_of_pfs);  in al_pcie_port_config()
1765 	al_pcie_port_ram_parity_int_config(pcie_port, params->enable_ram_parity_int);  in al_pcie_port_config()
1767 	al_pcie_port_axi_parity_int_config(pcie_port, params->enable_axi_parity_int);  in al_pcie_port_config()
1769 	al_pcie_port_relaxed_pcie_ordering_config(pcie_port, params->relaxed_ordering_params);  in al_pcie_port_config()
1771 	if (params->lat_rply_timers)  in al_pcie_port_config()
1772 		status = al_pcie_port_lat_rply_timers_config(pcie_port, params->lat_rply_timers);  in al_pcie_port_config()
1776 	if (params->gen2_params)  in al_pcie_port_config()
1777 		status = al_pcie_port_gen2_params_config(pcie_port, params->gen2_params);  in al_pcie_port_config()
1781 	if (params->gen3_params)  in al_pcie_port_config()
1782 		status = al_pcie_port_gen3_params_config(pcie_port, params->gen3_params);  in al_pcie_port_config()
1786 	if (params->sris_params)  in al_pcie_port_config()
1787 		status = al_pcie_port_sris_config(pcie_port, params->sris_params,  in al_pcie_port_config()
1788 						params->link_params->max_speed);  in al_pcie_port_config()
1794 	if (params->fast_link_mode) {  in al_pcie_port_config()
1795 		al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_port_config()
1800 	if (params->enable_axi_slave_err_resp)  in al_pcie_port_config()
1801 		al_reg_write32_masked(&regs->port_regs->axi_slave_err_resp,  in al_pcie_port_config()
1809 	 * address-decoder logic performs sub-target decoding even for transactions  in al_pcie_port_config()
1811 	 * inside any ECAM bar, the sub-target decoding will be set to ECAM, which  in al_pcie_port_config()
1812 	 * causes wrong handling by PCIe unit  in al_pcie_port_config()
1815 	 * on EP mode only, turning on the iATU-enable bit (with the relevant mask  in al_pcie_port_config()
1816 	 * below) allows the PCIe unit to discard the ECAM bit which was asserted  in al_pcie_port_config()
1817 	 * by-mistake in the address-decoder  in al_pcie_port_config()
1820 		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_target_bus,  in al_pcie_port_config()
1823 		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_control,  in al_pcie_port_config()
1834 			(uint16_t __iomem *)(&regs->core_space[0].config_header[0] + (0x4 >> 2)),  in al_pcie_port_config()
1842 			(uint32_t __iomem *)(&regs->core_space[0].config_header[0]  in al_pcie_port_config()
1858 		 * on RC mode only, set target-bus value to 0xFF to prevent this  in al_pcie_port_config()
1861 		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_target_bus,  in al_pcie_port_config()
1866 	al_dbg("PCIe %d: port config %s\n", pcie_port->port_id, status? "failed": "done");  in al_pcie_port_config()
1882 	pcie_port = pcie_pf->pcie_port;  in al_pcie_pf_config()
1885 		al_err("PCIe %d: port not enabled, cannot configure port\n", pcie_port->port_id);  in al_pcie_pf_config()
1886 		return -EINVAL;  in al_pcie_pf_config()
1889 	al_dbg("PCIe %d: pf %d config\n", pcie_port->port_id, pcie_pf->pf_num);  in al_pcie_pf_config()
1897 	al_dbg("PCIe %d: pf %d config %s\n",  in al_pcie_pf_config()
1898 		pcie_port->port_id, pcie_pf->pf_num, status ? "failed" : "done");  in al_pcie_pf_config()
1903 /************************** PCIe Link Operations API **************************/
1905 /* start pcie link */
1909 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_link_start()
1912 		al_err("PCIe %d: port not enabled, cannot start link\n",  in al_pcie_link_start()
1913 			pcie_port->port_id);  in al_pcie_link_start()
1914 		return -EINVAL;  in al_pcie_link_start()
1917 	al_dbg("PCIe_%d: start port link.\n", pcie_port->port_id);  in al_pcie_link_start()
1920 			regs->app.global_ctrl.port_init,  in al_pcie_link_start()
1927 /* stop pcie link */
1931 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_link_stop()
1934 		al_warn("PCIe %d: trying to stop a non-started link\n",  in al_pcie_link_stop()
1935 			pcie_port->port_id);  in al_pcie_link_stop()
1938 	al_dbg("PCIe_%d: stop port link.\n", pcie_port->port_id);  in al_pcie_link_stop()
1941 			regs->app.global_ctrl.port_init,  in al_pcie_link_stop()
1951 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_is_link_started()
1953 	uint32_t port_init = al_reg_read32(regs->app.global_ctrl.port_init);  in al_pcie_is_link_started()
1967 	while (wait_count-- > 0)	{  in al_pcie_link_up_wait()
1969 			al_dbg("PCIe_%d: <<<<<<<<< Link up >>>>>>>>>\n", pcie_port->port_id);  in al_pcie_link_up_wait()
1973 				pcie_port->port_id, wait_count);  in al_pcie_link_up_wait()
1978 				pcie_port->port_id);  in al_pcie_link_up_wait()
1988 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_link_status()
1994 		al_dbg("PCIe %d: port not enabled, no link.\n", pcie_port->port_id);  in al_pcie_link_status()
1995 		status->link_up = AL_FALSE;  in al_pcie_link_status()
1996 		status->speed = AL_PCIE_LINK_SPEED_DEFAULT;  in al_pcie_link_status()
1997 		status->lanes = 0;  in al_pcie_link_status()
1998 		status->ltssm_state = 0;  in al_pcie_link_status()
2002 	status->link_up = al_pcie_check_link(pcie_port, &status->ltssm_state);  in al_pcie_link_status()
2004 	if (!status->link_up) {  in al_pcie_link_status()
2005 		status->speed = AL_PCIE_LINK_SPEED_DEFAULT;  in al_pcie_link_status()
2006 		status->lanes = 0;  in al_pcie_link_status()
2010 …pcie_lnksta = al_reg_read16((uint16_t __iomem *)regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LN…  in al_pcie_link_status()
2014 			status->speed = AL_PCIE_LINK_SPEED_GEN1;  in al_pcie_link_status()
2017 			status->speed = AL_PCIE_LINK_SPEED_GEN2;  in al_pcie_link_status()
2020 			status->speed = AL_PCIE_LINK_SPEED_GEN3;  in al_pcie_link_status()
2023 			status->speed = AL_PCIE_LINK_SPEED_DEFAULT;  in al_pcie_link_status()
2024 			al_err("PCIe %d: unknown link speed indication. PCIE LINK STATUS %x\n",  in al_pcie_link_status()
2025 				pcie_port->port_id, pcie_lnksta);  in al_pcie_link_status()
2027 	status->lanes = (pcie_lnksta & AL_PCI_EXP_LNKSTA_NLW) >> AL_PCI_EXP_LNKSTA_NLW_SHIFT;  in al_pcie_link_status()
2028 	al_dbg("PCIe %d: Link up. speed gen%d negotiated width %d\n",  in al_pcie_link_status()
2029 		pcie_port->port_id, status->speed, status->lanes);  in al_pcie_link_status()
2041 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_lane_status_get()
2047 	al_assert((pcie_port->rev_id != AL_PCIE_REV_ID_1) || (lane < REV1_2_MAX_NUM_LANES));  in al_pcie_lane_status_get()
2048 	al_assert((pcie_port->rev_id != AL_PCIE_REV_ID_2) || (lane < REV1_2_MAX_NUM_LANES));  in al_pcie_lane_status_get()
2049 	al_assert((pcie_port->rev_id != AL_PCIE_REV_ID_3) || (lane < REV3_MAX_NUM_LANES));  in al_pcie_lane_status_get()
2051 	reg_ptr = regs->axi.status.lane[lane];  in al_pcie_lane_status_get()
2056 		status->is_reset = !!(lane_status & PCIE_AXI_STATUS_LANE_IS_RESET);  in al_pcie_lane_status_get()
2057 	} while (status->is_reset != (!!(al_reg_read32(reg_ptr) & PCIE_AXI_STATUS_LANE_IS_RESET)));  in al_pcie_lane_status_get()
2059 	status->requested_speed =  in al_pcie_lane_status_get()
2068 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_link_hot_reset()
2074 		al_err("PCIe %d: hot-reset is applicable only for RC mode\n", pcie_port->port_id);  in al_pcie_link_hot_reset()
2075 		return -EINVAL;  in al_pcie_link_hot_reset()
2079 		al_err("PCIe %d: link not started, cannot trigger hot-reset\n", pcie_port->port_id);  in al_pcie_link_hot_reset()
2080 		return -EINVAL;  in al_pcie_link_hot_reset()
2083 	events_gen = al_reg_read32(regs->app.global_ctrl.events_gen[0]);  in al_pcie_link_hot_reset()
2087 		al_err("PCIe %d: link is already in hot-reset state\n", pcie_port->port_id);  in al_pcie_link_hot_reset()
2088 		return -EINVAL;  in al_pcie_link_hot_reset()
2090 		al_err("PCIe %d: link is already in non-hot-reset state\n", pcie_port->port_id);  in al_pcie_link_hot_reset()
2091 		return -EINVAL;  in al_pcie_link_hot_reset()
2093 		al_dbg("PCIe %d: %s hot-reset\n", pcie_port->port_id,  in al_pcie_link_hot_reset()
2095 		/* hot-reset functionality is implemented only for function 0 */  in al_pcie_link_hot_reset()
2096 		al_reg_write32_masked(regs->app.global_ctrl.events_gen[0],  in al_pcie_link_hot_reset()
2108 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_link_disable()
2114 		al_err("PCIe %d: hot-reset is applicable only for RC mode\n", pcie_port->port_id);  in al_pcie_link_disable()
2115 		return -EINVAL;  in al_pcie_link_disable()
2119 		al_err("PCIe %d: link not started, cannot disable link\n", pcie_port->port_id);  in al_pcie_link_disable()
2120 		return -EINVAL;  in al_pcie_link_disable()
2123 	pcie_lnkctl = al_reg_read32(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1));  in al_pcie_link_disable()
2127 		al_err("PCIe %d: link is already in disable state\n", pcie_port->port_id);  in al_pcie_link_disable()
2128 		return -EINVAL;  in al_pcie_link_disable()
2130 		al_err("PCIe %d: link is already in enable state\n", pcie_port->port_id);  in al_pcie_link_disable()
2131 		return -EINVAL;  in al_pcie_link_disable()
2134 	al_dbg("PCIe %d: %s port\n", pcie_port->port_id, (disable ? "disabling" : "enabling"));  in al_pcie_link_disable()
2135 	al_reg_write32_masked(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1),  in al_pcie_link_disable()
2145 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_link_retrain()
2149 		al_err("PCIe %d: link-retrain is applicable only for RC mode\n",  in al_pcie_link_retrain()
2150 			pcie_port->port_id);  in al_pcie_link_retrain()
2151 		return -EINVAL;  in al_pcie_link_retrain()
2155 		al_err("PCIe %d: link not started, cannot link-retrain\n", pcie_port->port_id);  in al_pcie_link_retrain()
2156 		return -EINVAL;  in al_pcie_link_retrain()
2159 	al_reg_write32_masked(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1),  in al_pcie_link_retrain()
2170 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_link_change_speed()
2173 		al_err("PCIe %d: link not started, cannot change speed\n", pcie_port->port_id);  in al_pcie_link_change_speed()
2174 		return -EINVAL;  in al_pcie_link_change_speed()
2177 	al_dbg("PCIe %d: changing speed to %d\n", pcie_port->port_id, new_speed);  in al_pcie_link_change_speed()
2181 	al_reg_write32_masked(&regs->port_regs->gen2_ctrl,  in al_pcie_link_change_speed()
2193 	al_err("PCIe %d: link change width not implemented\n",  in al_pcie_link_change_width()
2194 		pcie_port->port_id);  in al_pcie_link_change_width()
2196 	return -ENOSYS;  in al_pcie_link_change_width()
2206 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_port_snoop_config()
2210 			pcie_port->port_id, enable_axi_snoop ? "enable" : "disable");  in al_pcie_port_snoop_config()
2213 		al_reg_write32_masked(regs->axi.ctrl.master_arctl,  in al_pcie_port_snoop_config()
2217 		al_reg_write32_masked(regs->axi.ctrl.master_awctl,  in al_pcie_port_snoop_config()
2221 		al_reg_write32_masked(regs->axi.ctrl.master_arctl,  in al_pcie_port_snoop_config()
2225 		al_reg_write32_masked(regs->axi.ctrl.master_awctl,  in al_pcie_port_snoop_config()
2239 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_config_space_get()
2241 	*addr = (uint8_t __iomem *)&regs->core_space[pcie_pf->pf_num].config_header[0];  in al_pcie_config_space_get()
2251 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_local_cfg_space_read()
2254 	data = al_reg_read32(&regs->core_space[pcie_pf->pf_num].config_header[reg_offset]);  in al_pcie_local_cfg_space_read()
2268 	struct al_pcie_port *pcie_port = pcie_pf->pcie_port;  in al_pcie_local_cfg_space_write()
2269 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_local_cfg_space_write()
2270 	unsigned int pf_num = pcie_pf->pf_num;  in al_pcie_local_cfg_space_write()
2271 	uint32_t *offset = &regs->core_space[pf_num].config_header[reg_offset];  in al_pcie_local_cfg_space_write()
2292 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_target_bus_set()
2295 	reg = al_reg_read32(regs->axi.ob_ctrl.cfg_target_bus);  in al_pcie_target_bus_set()
2302 	al_reg_write32(regs->axi.ob_ctrl.cfg_target_bus, reg);  in al_pcie_target_bus_set()
2313 	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;  in al_pcie_target_bus_get()
2319 	reg = al_reg_read32(regs->axi.ob_ctrl.cfg_target_bus);  in al_pcie_target_bus_get()
2334 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_secondary_bus_set()
2340 		regs->axi.ob_ctrl.cfg_control,  in al_pcie_secondary_bus_set()
2346 /** Set sub-ordinary bus number */
2350 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_subordinary_bus_set()
2356 		regs->axi.ob_ctrl.cfg_control,  in al_pcie_subordinary_bus_set()
2368 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_app_req_retry_set()
2369 	uint32_t mask = (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?  in al_pcie_app_req_retry_set()
2373 	al_reg_write32_masked(regs->app.global_ctrl.pm_control,  in al_pcie_app_req_retry_set()
2380 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_app_req_retry_get_status()
2382 	uint32_t mask = (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?  in al_pcie_app_req_retry_get_status()
2386 	pm_control = al_reg_read32(regs->app.global_ctrl.pm_control);  in al_pcie_app_req_retry_get_status()
2398 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_atu_region_set()
2408 	 * (hresetn or slv_aclk) is asynchronous to the PCIe native core clock  in al_pcie_atu_region_set()
2419 	if ((atu_region->direction == AL_PCIE_ATU_DIR_OUTBOUND)  in al_pcie_atu_region_set()
2421 		if (!atu_region->enforce_ob_atu_region_set) {  in al_pcie_atu_region_set()
2422 			al_err("PCIe %d: setting OB iATU after link is started is not allowed\n",  in al_pcie_atu_region_set()
2423 				pcie_port->port_id);  in al_pcie_atu_region_set()
2425 			return -EINVAL;  in al_pcie_atu_region_set()
2427 			al_info("PCIe %d: setting OB iATU even after link is started\n",  in al_pcie_atu_region_set()
2428 				pcie_port->port_id);  in al_pcie_atu_region_set()
2433 	AL_REG_FIELD_SET(reg, 0xF, 0, atu_region->index);  in al_pcie_atu_region_set()
2434 	AL_REG_BIT_VAL_SET(reg, 31, atu_region->direction);  in al_pcie_atu_region_set()
2435 	al_reg_write32(&regs->port_regs->iatu.index, reg);  in al_pcie_atu_region_set()
2437 	al_reg_write32(&regs->port_regs->iatu.lower_base_addr,  in al_pcie_atu_region_set()
2438 			(uint32_t)(atu_region->base_addr & 0xFFFFFFFF));  in al_pcie_atu_region_set()
2439 	al_reg_write32(&regs->port_regs->iatu.upper_base_addr,  in al_pcie_atu_region_set()
2440 			(uint32_t)((atu_region->base_addr >> 32)& 0xFFFFFFFF));  in al_pcie_atu_region_set()
2441 	al_reg_write32(&regs->port_regs->iatu.lower_target_addr,  in al_pcie_atu_region_set()
2442 			(uint32_t)(atu_region->target_addr & 0xFFFFFFFF));  in al_pcie_atu_region_set()
2443 	al_reg_write32(&regs->port_regs->iatu.upper_target_addr,  in al_pcie_atu_region_set()
2444 			(uint32_t)((atu_region->target_addr >> 32)& 0xFFFFFFFF));  in al_pcie_atu_region_set()
2447 	if (atu_region->match_mode == 0) {  in al_pcie_atu_region_set()
2450 			(atu_region->direction == AL_PCIE_ATU_DIR_OUTBOUND) ?  in al_pcie_atu_region_set()
2451 			&regs->app.atu.out_mask_pair[atu_region->index / 2] :  in al_pcie_atu_region_set()
2452 			&regs->app.atu.in_mask_pair[atu_region->index / 2];  in al_pcie_atu_region_set()
2454 			(atu_region->index % 2) ?  in al_pcie_atu_region_set()
2458 			(atu_region->index % 2) ?  in al_pcie_atu_region_set()
2462 			atu_region->limit - atu_region->base_addr;  in al_pcie_atu_region_set()
2470 			limit_reg_val = (uint32_t)(atu_region->limit &  in al_pcie_atu_region_set()
2479 		al_reg_write32(&regs->port_regs->iatu.limit_addr,  in al_pcie_atu_region_set()
2488 	* Bug in SNPS IP (versions 4.21 , 4.10a-ea02)  in al_pcie_atu_region_set()
2492 	* Those bits are currently reserved ,bit might be non-resv. in future generations .  in al_pcie_atu_region_set()
2499 	if ((atu_region->cfg_shift_mode == AL_TRUE) &&  in al_pcie_atu_region_set()
2500 		(atu_region->direction == AL_PCIE_ATU_DIR_OUTBOUND)) {  in al_pcie_atu_region_set()
2501 		if (pcie_port->rev_id > AL_PCIE_REV_ID_2) {  in al_pcie_atu_region_set()
2502 			al_reg_write32_masked(regs->app.atu.reg_out_mask,  in al_pcie_atu_region_set()
2503 			1 << (atu_region->index) ,  in al_pcie_atu_region_set()
2504 			1 << (atu_region->index));  in al_pcie_atu_region_set()
2507 				(atu_region->direction == AL_PCIE_ATU_DIR_OUTBOUND) ?  in al_pcie_atu_region_set()
2508 				&regs->app.atu.out_mask_pair[atu_region->index / 2] :  in al_pcie_atu_region_set()
2509 				&regs->app.atu.in_mask_pair[atu_region->index / 2];  in al_pcie_atu_region_set()
2511 				(atu_region->index % 2) ?  in al_pcie_atu_region_set()
2515 				(atu_region->index % 2) ?  in al_pcie_atu_region_set()
2527 	AL_REG_FIELD_SET(reg, 0x1F, 0, atu_region->tlp_type);  in al_pcie_atu_region_set()
2528 	AL_REG_FIELD_SET(reg, 0x3 << 9, 9, atu_region->attr);  in al_pcie_atu_region_set()
2531 	if ((pcie_port->rev_id == AL_PCIE_REV_ID_3)  in al_pcie_atu_region_set()
2533 		&& (atu_region->function_match_bypass_mode)) {  in al_pcie_atu_region_set()
2537 			atu_region->function_match_bypass_mode_number);  in al_pcie_atu_region_set()
2540 	al_reg_write32(&regs->port_regs->iatu.cr1, reg);  in al_pcie_atu_region_set()
2544 	AL_REG_FIELD_SET(reg, 0xFF, 0, atu_region->msg_code);  in al_pcie_atu_region_set()
2545 	AL_REG_FIELD_SET(reg, 0x700, 8, atu_region->bar_number);  in al_pcie_atu_region_set()
2546 	AL_REG_FIELD_SET(reg, 0x3 << 24, 24, atu_region->response);  in al_pcie_atu_region_set()
2547 	AL_REG_BIT_VAL_SET(reg, 16, atu_region->enable_attr_match_mode == AL_TRUE);  in al_pcie_atu_region_set()
2548 	AL_REG_BIT_VAL_SET(reg, 21, atu_region->enable_msg_match_mode == AL_TRUE);  in al_pcie_atu_region_set()
2549 	AL_REG_BIT_VAL_SET(reg, 28, atu_region->cfg_shift_mode == AL_TRUE);  in al_pcie_atu_region_set()
2550 	AL_REG_BIT_VAL_SET(reg, 29, atu_region->invert_matching == AL_TRUE);  in al_pcie_atu_region_set()
2551 	if (atu_region->tlp_type == AL_PCIE_TLP_TYPE_MEM || atu_region->tlp_type == AL_PCIE_TLP_TYPE_IO)  in al_pcie_atu_region_set()
2552 		AL_REG_BIT_VAL_SET(reg, 30, !!atu_region->match_mode);  in al_pcie_atu_region_set()
2553 	AL_REG_BIT_VAL_SET(reg, 31, !!atu_region->enable);  in al_pcie_atu_region_set()
2557 	 * Note: this is the same bit, has different meanings in ob/ib ATUs  in al_pcie_atu_region_set()
2563 			atu_region->function_match_bypass_mode ? 0x1 : 0x0);  in al_pcie_atu_region_set()
2565 	al_reg_write32(&regs->port_regs->iatu.cr2, reg);  in al_pcie_atu_region_set()
2577 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_atu_region_get_fields()
2583 	al_reg_write32(&regs->port_regs->iatu.index, reg);  in al_pcie_atu_region_get_fields()
2585 	*base_addr = al_reg_read32(&regs->port_regs->iatu.lower_base_addr);  in al_pcie_atu_region_get_fields()
2586 	high_addr = al_reg_read32(&regs->port_regs->iatu.upper_base_addr);  in al_pcie_atu_region_get_fields()
2590 	*target_addr = al_reg_read32(&regs->port_regs->iatu.lower_target_addr);  in al_pcie_atu_region_get_fields()
2591 	high_addr = al_reg_read32(&regs->port_regs->iatu.upper_target_addr);  in al_pcie_atu_region_get_fields()
2595 	reg = al_reg_read32(&regs->port_regs->iatu.cr1);  in al_pcie_atu_region_get_fields()
2605 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_axi_io_config()
2607 	al_reg_write32(regs->axi.ob_ctrl.io_start_h,  in al_pcie_axi_io_config()
2610 	al_reg_write32(regs->axi.ob_ctrl.io_start_l,  in al_pcie_axi_io_config()
2613 	al_reg_write32(regs->axi.ob_ctrl.io_limit_h,  in al_pcie_axi_io_config()
2616 	al_reg_write32(regs->axi.ob_ctrl.io_limit_l,  in al_pcie_axi_io_config()
2619 	al_reg_write32_masked(regs->axi.ctrl.slv_ctl,  in al_pcie_axi_io_config()
2628 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_pf_flr_done_gen()
2629 	unsigned int pf_num = pcie_pf->pf_num;  in al_pcie_pf_flr_done_gen()
2631 	al_reg_write32_masked(regs->app.global_ctrl.events_gen[pf_num],  in al_pcie_pf_flr_done_gen()
2635 	al_reg_write32_masked(regs->app.global_ctrl.events_gen[pf_num],  in al_pcie_pf_flr_done_gen()
2648 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_legacy_int_gen()
2649 	unsigned int pf_num = pcie_pf->pf_num;  in al_pcie_legacy_int_gen()
2653 	reg = al_reg_read32(regs->app.global_ctrl.events_gen[pf_num]);  in al_pcie_legacy_int_gen()
2655 	al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);  in al_pcie_legacy_int_gen()
2664 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_msi_int_gen()
2665 	unsigned int pf_num = pcie_pf->pf_num;  in al_pcie_msi_int_gen()
2669 	reg = al_reg_read32(regs->app.global_ctrl.events_gen[pf_num]);  in al_pcie_msi_int_gen()
2675 	al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);  in al_pcie_msi_int_gen()
2678 	al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);  in al_pcie_msi_int_gen()
2689 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_msix_config()
2690 	unsigned int pf_num = pcie_pf->pf_num;  in al_pcie_msix_config()
2693 	al_pcie_port_wr_to_ro_set(pcie_pf->pcie_port, AL_TRUE);  in al_pcie_msix_config()
2695 	msix_reg0 = al_reg_read32(regs->core_space[pf_num].msix_cap_base);  in al_pcie_msix_config()
2698 	msix_reg0 |= ((msix_params->table_size - 1) & AL_PCI_MSIX_MSGCTRL_TBL_SIZE) <<  in al_pcie_msix_config()
2700 	al_reg_write32(regs->core_space[pf_num].msix_cap_base, msix_reg0);  in al_pcie_msix_config()
2703 	al_reg_write32(regs->core_space[pf_num].msix_cap_base + (AL_PCI_MSIX_TABLE >> 2),  in al_pcie_msix_config()
2704 		       (msix_params->table_offset & AL_PCI_MSIX_TABLE_OFFSET) |  in al_pcie_msix_config()
2705 			       (msix_params->table_bar & AL_PCI_MSIX_TABLE_BAR));  in al_pcie_msix_config()
2707 	al_reg_write32(regs->core_space[pf_num].msix_cap_base + (AL_PCI_MSIX_PBA >> 2),  in al_pcie_msix_config()
2708 		       (msix_params->pba_offset & AL_PCI_MSIX_PBA_OFFSET) |  in al_pcie_msix_config()
2709 			       (msix_params->pba_bar & AL_PCI_MSIX_PBA_BAR));  in al_pcie_msix_config()
2711 	al_pcie_port_wr_to_ro_set(pcie_pf->pcie_port, AL_FALSE);  in al_pcie_msix_config()
2720 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_msix_enabled()
2721 	uint32_t msix_reg0 = al_reg_read32(regs->core_space[pcie_pf->pf_num].msix_cap_base);  in al_pcie_msix_enabled()
2732 	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;  in al_pcie_msix_masked()
2733 	uint32_t msix_reg0 = al_reg_read32(regs->core_space[pcie_pf->pf_num].msix_cap_base);  in al_pcie_msix_masked()
2749 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_aer_config_aux()
2750 	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;  in al_pcie_aer_config_aux()
2753 	reg_val = al_reg_read32(&aer_regs->header);  in al_pcie_aer_config_aux()
2757 		return -EIO;  in al_pcie_aer_config_aux()
2761 		return -EIO;  in al_pcie_aer_config_aux()
2763 	al_reg_write32(&aer_regs->corr_err_mask, ~params->enabled_corr_err);  in al_pcie_aer_config_aux()
2765 	al_reg_write32(&aer_regs->uncorr_err_mask,  in al_pcie_aer_config_aux()
2766 		(~params->enabled_uncorr_non_fatal_err) |  in al_pcie_aer_config_aux()
2767 		(~params->enabled_uncorr_fatal_err));  in al_pcie_aer_config_aux()
2769 	al_reg_write32(&aer_regs->uncorr_err_severity,  in al_pcie_aer_config_aux()
2770 		params->enabled_uncorr_fatal_err);  in al_pcie_aer_config_aux()
2772 	al_reg_write32(&aer_regs->cap_and_ctrl,  in al_pcie_aer_config_aux()
2773 		(params->ecrc_gen_en ? PCIE_AER_CTRL_STAT_ECRC_GEN_EN : 0) |  in al_pcie_aer_config_aux()
2774 		(params->ecrc_chk_en ? PCIE_AER_CTRL_STAT_ECRC_CHK_EN : 0));  in al_pcie_aer_config_aux()
2786 	if (params->ecrc_gen_en == AL_TRUE) {  in al_pcie_aer_config_aux()
2791 		regs->core_space[pf_num].pcie_dev_ctrl_status,  in al_pcie_aer_config_aux()
2796 		(params->enabled_corr_err ?  in al_pcie_aer_config_aux()
2798 		(params->enabled_uncorr_non_fatal_err ?  in al_pcie_aer_config_aux()
2800 		(params->enabled_uncorr_fatal_err ?  in al_pcie_aer_config_aux()
2802 		((params->enabled_uncorr_non_fatal_err &  in al_pcie_aer_config_aux()
2805 		((params->enabled_uncorr_fatal_err &  in al_pcie_aer_config_aux()
2818 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_aer_uncorr_get_and_clear_aux()
2819 	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;  in al_pcie_aer_uncorr_get_and_clear_aux()
2822 	reg_val = al_reg_read32(&aer_regs->uncorr_err_stat);  in al_pcie_aer_uncorr_get_and_clear_aux()
2823 	al_reg_write32(&aer_regs->uncorr_err_stat, reg_val);  in al_pcie_aer_uncorr_get_and_clear_aux()
2834 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_aer_corr_get_and_clear_aux()
2835 	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;  in al_pcie_aer_corr_get_and_clear_aux()
2838 	reg_val = al_reg_read32(&aer_regs->corr_err_stat);  in al_pcie_aer_corr_get_and_clear_aux()
2839 	al_reg_write32(&aer_regs->corr_err_stat, reg_val);  in al_pcie_aer_corr_get_and_clear_aux()
2855 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_aer_err_tlp_hdr_get_aux()
2856 	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;  in al_pcie_aer_err_tlp_hdr_get_aux()
2860 		hdr[i] = al_reg_read32(&aer_regs->header_log[i]);  in al_pcie_aer_err_tlp_hdr_get_aux()
2873 			pcie_pf->pcie_port, pcie_pf->pf_num, params);  in al_pcie_aer_config()
2882 			pcie_pf->pcie_port, pcie_pf->pf_num);  in al_pcie_aer_uncorr_get_and_clear()
2891 			pcie_pf->pcie_port, pcie_pf->pf_num);  in al_pcie_aer_corr_get_and_clear()
2906 			pcie_pf->pcie_port, pcie_pf->pf_num, hdr);  in al_pcie_aer_err_tlp_hdr_get()
2972 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_local_pipe_loopback_enter()
2974 	al_dbg("PCIe %d: Enter LOCAL PIPE Loopback mode", pcie_port->port_id);  in al_pcie_local_pipe_loopback_enter()
2976 	al_reg_write32_masked(&regs->port_regs->pipe_loopback_ctrl,  in al_pcie_local_pipe_loopback_enter()
2980 	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_local_pipe_loopback_enter()
2990  * @param pcie_port	pcie port handle
2996 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_local_pipe_loopback_exit()
2998 	al_dbg("PCIe %d: Exit LOCAL PIPE Loopback mode", pcie_port->port_id);  in al_pcie_local_pipe_loopback_exit()
3000 	al_reg_write32_masked(&regs->port_regs->pipe_loopback_ctrl,  in al_pcie_local_pipe_loopback_exit()
3004 	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_local_pipe_loopback_exit()
3014 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_remote_loopback_enter()
3016 	al_dbg("PCIe %d: Enter REMOTE Loopback mode", pcie_port->port_id);  in al_pcie_remote_loopback_enter()
3018 	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_remote_loopback_enter()
3028  * @param   pcie_port pcie port handle
3034 	struct al_pcie_regs *regs = pcie_port->regs;  in al_pcie_remote_loopback_exit()
3036 	al_dbg("PCIe %d: Exit REMOTE Loopback mode", pcie_port->port_id);  in al_pcie_remote_loopback_exit()
3038 	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,  in al_pcie_remote_loopback_exit()