Lines Matching refs:uint32_t
61 uint32_t cpus_config;
63 uint32_t cpus_secure;
65 uint32_t cpus_init_control;
67 uint32_t cpus_init_status;
69 uint32_t nb_int_cause;
71 uint32_t sev_int_cause;
73 uint32_t pmus_int_cause;
75 uint32_t sev_mask;
77 uint32_t cpus_hold_reset;
79 uint32_t cpus_software_reset;
81 uint32_t wd_timer0_reset;
83 uint32_t wd_timer1_reset;
85 uint32_t wd_timer2_reset;
87 uint32_t wd_timer3_reset;
89 uint32_t ddrc_hold_reset;
91 uint32_t fabric_software_reset;
93 uint32_t cpus_power_ctrl;
94 uint32_t rsrvd_0[7];
96 uint32_t acf_base_high;
98 uint32_t acf_base_low;
100 uint32_t acf_control_override;
102 uint32_t lgic_base_high;
104 uint32_t lgic_base_low;
106 uint32_t iogic_base_high;
108 uint32_t iogic_base_low;
110 uint32_t io_wr_split_control;
112 uint32_t io_rd_rob_control;
114 uint32_t sb_pos_error_log_1;
116 uint32_t sb_pos_error_log_0;
118 uint32_t c2swb_config;
120 uint32_t msix_error_log;
122 uint32_t error_cause;
124 uint32_t error_mask;
125 uint32_t rsrvd_1;
127 uint32_t qos_peak_control;
129 uint32_t qos_set_control;
131 uint32_t ddr_qos;
132 uint32_t rsrvd_2[9];
134 uint32_t acf_misc;
136 uint32_t config_bus_control;
137 uint32_t rsrvd_3[2];
139 uint32_t pos_id_match;
140 uint32_t rsrvd_4[3];
142 uint32_t sb_sel_override_awuser;
144 uint32_t sb_override_awuser;
146 uint32_t sb_sel_override_aruser;
148 uint32_t sb_override_aruser;
150 uint32_t cpu_max_pd_timer;
152 uint32_t cpu_max_pu_timer;
153 uint32_t rsrvd_5[2];
155 uint32_t auto_ddr_self_refresh_counter;
156 uint32_t rsrvd_6[3];
158 uint32_t coresight_pd;
160 uint32_t coresight_internal_0;
162 uint32_t coresight_dbgromaddr;
164 uint32_t coresight_dbgselfaddr;
166 uint32_t coresght_targetid;
168 uint32_t coresght_targetid0;
169 uint32_t rsrvd_7[10];
171 uint32_t sb_force_same_id_cfg_0;
173 uint32_t sb_mstr_force_same_id_sel_0;
175 uint32_t sb_force_same_id_cfg_1;
177 uint32_t sb_mstr_force_same_id_sel_1;
178 uint32_t rsrvd[932];
182 uint32_t cnt_control;
184 uint32_t cnt_base_freq;
186 uint32_t cnt_low;
188 uint32_t cnt_high;
190 uint32_t cnt_init_low;
192 uint32_t cnt_init_high;
193 uint32_t rsrvd[58];
197 uint32_t ca15_rf_misc;
198 uint32_t rsrvd_0;
200 uint32_t nb_rf_misc;
201 uint32_t rsrvd[61];
205 uint32_t rf_0;
207 uint32_t rf_1;
209 uint32_t rf_2;
210 uint32_t rsrvd;
214 uint32_t lockn;
218 uint32_t ca15_outputs_1;
220 uint32_t ca15_outputs_2;
221 uint32_t rsrvd_0[2];
223 uint32_t cpu_msg[4];
225 uint32_t rsv0_config;
227 uint32_t rsv1_config;
228 uint32_t rsrvd_1[2];
230 uint32_t rsv0_status;
232 uint32_t rsv1_status;
233 uint32_t rsrvd_2[2];
235 uint32_t ddrc;
237 uint32_t ddrc_phy_smode_control;
239 uint32_t ddrc_phy_smode_status;
240 uint32_t rsrvd_3[5];
242 uint32_t pmc;
243 uint32_t rsrvd_4[3];
245 uint32_t cpus_general;
247 uint32_t cpus_general_1;
248 uint32_t rsrvd_5[2];
250 uint32_t cpus_int_out;
251 uint32_t rsrvd_6[3];
253 uint32_t latch_pc_req;
254 uint32_t rsrvd_7;
256 uint32_t latch_pc_low;
258 uint32_t latch_pc_high;
259 uint32_t rsrvd_8[24];
261 uint32_t track_dump_ctrl;
263 uint32_t track_dump_rdata_0;
265 uint32_t track_dump_rdata_1;
266 uint32_t rsrvd_9[5];
268 uint32_t track_events;
269 uint32_t rsrvd_10[3];
271 uint32_t pos_track_dump_ctrl;
273 uint32_t pos_track_dump_rdata_0;
275 uint32_t pos_track_dump_rdata_1;
276 uint32_t rsrvd_11;
278 uint32_t c2swb_track_dump_ctrl;
280 uint32_t c2swb_track_dump_rdata_0;
282 uint32_t c2swb_track_dump_rdata_1;
283 uint32_t rsrvd_12;
285 uint32_t cpus_track_dump_ctrl;
287 uint32_t cpus_track_dump_rdata_0;
289 uint32_t cpus_track_dump_rdata_1;
290 uint32_t rsrvd_13;
292 uint32_t c2swb_bar_ovrd_high;
294 uint32_t c2swb_bar_ovrd_low;
295 uint32_t rsrvd[38];
299 uint32_t config;
301 uint32_t config_aarch64;
303 uint32_t local_cause_mask;
304 uint32_t rsrvd_0;
306 uint32_t pmus_cause_mask;
308 uint32_t sei_cause_mask;
309 uint32_t rsrvd_1[2];
311 uint32_t power_ctrl;
313 uint32_t power_status;
315 uint32_t resume_addr_l;
317 uint32_t resume_addr_h;
318 uint32_t rsrvd_2[4];
320 uint32_t warm_rst_ctl;
321 uint32_t rsrvd_3;
323 uint32_t rvbar_low;
325 uint32_t rvbar_high;
327 uint32_t pmu_snapshot;
328 uint32_t rsrvd_4[3];
330 uint32_t cpu_msg_in;
331 uint32_t rsrvd[39];
335 uint32_t pmu_control;
337 uint32_t overflow;
338 uint32_t rsrvd[62];
342 uint32_t cfg;
344 uint32_t cntl;
346 uint32_t low;
348 uint32_t high;
349 uint32_t rsrvd[4];
353 uint32_t version;
354 uint32_t rsrvd;
358 uint32_t cpu_tgtid[4];
359 uint32_t rsrvd[4];
363 uint32_t dram_0_control;
364 uint32_t rsrvd_0;
366 uint32_t dram_0_status;
367 uint32_t rsrvd_1;
369 uint32_t ddr_int_cause;
370 uint32_t rsrvd_2;
372 uint32_t ddr_cause_mask;
373 uint32_t rsrvd_3;
375 uint32_t address_map;
376 uint32_t rsrvd_4[3];
378 uint32_t reorder_id_mask_0;
380 uint32_t reorder_id_value_0;
382 uint32_t reorder_id_mask_1;
384 uint32_t reorder_id_value_1;
386 uint32_t reorder_id_mask_2;
388 uint32_t reorder_id_value_2;
390 uint32_t reorder_id_mask_3;
392 uint32_t reorder_id_value_3;
394 uint32_t mrr_control_status;
395 uint32_t rsrvd[43];
399 uint32_t val;
403 uint32_t pp_config;
404 uint32_t rsrvd_0[3];
406 uint32_t pp_ext_attr;
407 uint32_t rsrvd_1[3];
409 uint32_t pp_base_low;
411 uint32_t pp_base_high;
412 uint32_t rsrvd_2[2];
414 uint32_t pp_sel_attr;
415 uint32_t rsrvd[51];
423 uint32_t rsrvd_0[108];
425 uint32_t rsrvd_1[320];
427 uint32_t rsrvd_2[256];
429 uint32_t rsrvd_3[1792];
432 uint32_t rsrvd_4[160];
434 uint32_t rsrvd_5[126];
436 uint32_t rsrvd_6[120];
439 uint32_t rsrvd_7[439];
440 uint32_t rsrvd_8[1024]; /* [0x5000] */