Lines Matching full:individual
621 /* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
624 /* Individual CPU core and VFP/NEON logic reset.
628 /* Individual CPU por-on-reset.
641 0x0 - cpu_core: Individual CPU core reset.
642 0x1 - cpu_poreset: Individual CPU power-on-reset.
643 0x2 - cpu_dbg: Individual CPU debug reset.
649 /* Individual CPU core reset. */
652 /* Individual CPU power-on-reset. */
655 /* Individual CPU debug reset. */
680 /* Individual CPU debug PTM, watchpoint and breakpoint logic reset */
683 /* Individual CPU core and VFP/NEON logic reset */
686 /* Individual CPU por-on-reset */
695 /* Individual CPU debug PTM, watchpoint and breakpoint logic reset */
698 /* Individual CPU core and VFP/NEON logic reset */
701 /* Individual CPU por-on-reset */
710 /* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
713 /* Individual CPU core and VFP/NEON logic reset */
716 /* Individual CPU por-on-reset */
725 /* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
728 /* Individual CPU core and VFP/NEON logic reset */
731 /* Individual CPU por-on-reset */
1446 /* Individual processor control of the endianness configuration at reset. It sets the initial value…
1450 /* Individual processor control of the default exception handling state. It sets the initial value …
1454 /* Individual processor control of the location of the exception vectors at reset. It sets the init…
1459 /* Individual processor control to disable write access to some secure CP15 registers
1468 /* Individual processor register width state. The register width states are:
1474 /* Individual processor Cryptography engine disable:
1481 /* Individual CPU power mode transition request
1515 /* Read-only bits that reflect the individual CPU power mode status.