Lines Matching +full:cpu +full:- +full:read
1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
310 /* [0x20] Specifies the state of the CPU with reference to power modes. */
463 /* Defines the internal CPU GIC operating frequency ratio with the main CPU clock.
472 /* Disables the GIC CPU interface logic and routes the legacy nIRQ, nFIQ, nVIRQ, and nVFIQ
474 0 Enable the GIC CPU interface logic.
475 1 Disable the GIC CPU interface logic.
480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
485 /* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity
510 /* CPU Init Done
512 By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other…
513 …d for a specific CPU, setting it by primary CPU as part of the initialization process will initiat…
517 When CPU does not exist, its DBGPWRDNREQ must be asserted.
521 /* Force CPU init power-on-reset exit.
540 * Level IRQ indices: 12-13, 23, 24, 26-29
552 /* Reserved, read undefined must write as zeros. */
556 /* Error indicator for: L2 RAM double-bit ECC error, illegal writes to the GIC memory-map region. */
572 /* Received msix is not mapped to local GIC or IO-GIC spin */
578 /* SMMU 0/1 global non-secure fault interrupt */
581 /* SMMU 0/1 non-secure context interrupt */
584 /* SMMU0/1 Non-secure configuration access fault interrupt */
587 /* Reserved. Read undefined; must write as zeros. */
590 /* Reserved. Read undefined; must write as zeros. */
608 /* Reserved. Read undefined; must write as zeros. */
621 /* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
624 /* Individual CPU core and VFP/NEON logic reset.
625 Reset is applied only when specific CPU is in STNDBYWFI state. */
628 /* Individual CPU por-on-reset.
629 Reset is applied only when specific CPU is in STNDBYWFI state. */
633 If set, reset is applied without waiting for the specified CPU's STNDBYWFI state. */
641 0x0 - cpu_core: Individual CPU core reset.
642 0x1 - cpu_poreset: Individual CPU power-on-reset.
643 0x2 - cpu_dbg: Individual CPU debug reset.
644 0x3 - cluster_no_dbg: A Cluster reset puts each core into core reset (no dbg) and also resets the i…
645 0x4 - cluster: A Cluster reset puts each core into power-on-reset and also resets the interrupt con…
646 0x5 - cluster_poreset: A Cluster power-on-reset puts each core into power-on-reset and also resets …
649 /* Individual CPU core reset. */
652 /* Individual CPU power-on-reset. */
655 /* Individual CPU debug reset. */
661 /* A Cluster reset puts each core into power-on-reset and also r ... */
664 /* A Cluster power-on-reset puts each core into power-on-reset a ... */
671 Defines which CPU WFI indication to wait for before applying the software reset. */
680 /* Individual CPU debug PTM, watchpoint and breakpoint logic reset */
683 /* Individual CPU core and VFP/NEON logic reset */
686 /* Individual CPU por-on-reset */
695 /* Individual CPU debug PTM, watchpoint and breakpoint logic reset */
698 /* Individual CPU core and VFP/NEON logic reset */
701 /* Individual CPU por-on-reset */
710 /* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
713 /* Individual CPU core and VFP/NEON logic reset */
716 /* Individual CPU por-on-reset */
725 /* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
728 /* Individual CPU core and VFP/NEON logic reset */
731 /* Individual CPU por-on-reset */
737 0 - Reset is deasserted.
738 1 - Reset is asserted (active). */
741 0 - Reset is deasserted.
742 1 - Reset is asserted.
746 0 - Reset is deasserted.
747 1 - Reset is asserted.
751 0 - Reset is deasserted.
752 1 - Reset is asserted.
756 0 - Reset is deasserted.
757 1 - Reset is asserted.
761 0 - Reset is deasserted.
762 1 - Reset is asserted. */
771 0x0 - fabric: Fabric reset
772 0x1 - gic: GIC reset
773 0x2 - smmu: SMMU reset */
786 Defines which CPU WFI indication to wait before applying the software reset. */
792 When all the processors are in WFI mode or powered-down, the shared L2 memory system Power Manageme…
803 /* CPU state condition to enable L2 RAM power down
804 0 - Power down
805 1 - WFI
809 /* Enable external debugger over power-down.
816 /* Force wakeup the CPU in L2RAM power down
833 non-bufferable. One bit exists for each master interface.
848 Enables 4k hazard of post-barrier vs pre-barrier transactions. Otherwise, 64B hazard granularity is…
878 If store and forward is disabled, splitter does not check non-active BE in the middle of a transact…
885 /* Write splitters unsplit non-coherent access.
886 Disables splitting of non-coherent access to cache-line chunks. */
905 /* Read ROB Bypass
910 /* Read ROB in order.
914 /* Read ROB response rate
915 When enabled drops one cycle from back to back read responses */
918 /* Read splitter rate limit */
921 /* Read splitter rate limit */
947 /* Received msix is not mapped to local GIC or IO-GIC spin */
955 /* Read data parity error from SB slaves. */
965 /* Error indicator for: L2 RAM double-bit ECC error, illegal writes to the GIC memory-map region. */
971 /* Peak Read Low Threshold
972 When the number of outstanding read transactions from SB masters is below this value, the CPU is as…
975 /* Peak Read High Threshold
976 When the number of outstanding read transactions from SB masters exceeds this value, the CPU is ass…
980 …nding write transactions from SB masters is below this value, the CPU is assigned high-priority Qo…
984 …anding write transactions from SB masters exceeds this value, the CPU is assigned high-priority Qo…
989 /* CPU Low priority Read QoS */
992 /* CPU High priority Read QoS */
995 /* CPU Low priority Write QoS */
998 /* CPU High priority Write QoS */
1001 /* SB Low priority Read QoS */
1004 /* SB Low-priority Write QoS */
1009 /* High Priority Read Threshold
1021 Performance optimization feature to chop non-active data beats to the DDR. */
1023 /* Disable SB-2-SB path through NB fabric. */
1025 /* Disable ETR tracing to non-DDR. */
1027 /* Disable ETR tracing to non-DDR. */
1029 /* Disable CPU generation of MSIx
1030 By default, the CPU can set any MSIx message results by setting any SPIn bit in the local and IO-GI…
1033 By default, an MSIx transaction is downgraded to non-coherent. */
1038 SO read forces flushing of all prior writes */
1043 On DSB from CPU, PoS blocks the progress of post-barrier reads and writes until all pre-barrier wri…
1046 On DMB from CPU, the PoS blocks the progress of post-barrier non-buffereable reads or writes when t…
1047 Other access types are hazard check against the pre-barrier requests. */
1051 /* Disable write after read stall when accessing IO fabric slaves. */
1053 /* Disable write after read stall when accessing DDR */
1061 /* Override the address parity calucation for write transactions going to IO-fabric */
1063 /* Override the data parity calucation for write transactions going to IO-fabric */
1065 /* Override the address parity calucation for read transactions going to IO-fabric */
1067 /* Halts CPU AXI interface (Ar/Aw channels), not allowing the CPU to send additional transactions */
1071 /* Enable wire interrupts connectivity to IO-GIC IRQs */
1077 /* Alpine V2 only: remap CPU address above 40 bits to Slave Error
1080 /* Enable CPU WriteUnique to WriteNoSnoop trasform */
1092 /* Read slave error enable */
1094 /* Read decode error enable */
1123 …ransaction aruser or sb_override_aruser value for aruser field on outgoing read transactions to SB.
1170 …the ROM table physical address to the physical address where the debug registers are memory-mapped.
1174 …the ROM table physical address to the physical address where the debug registers are memory-mapped.
1229 CPU reads it:
1230 If current value ==0, return 0 to CPU but set bit to 1. (CPU knows it captured the semaphore.)
1231 If current value ==1, return 1 to CPU. (CPU knows it is already used and waits.)
1232 CPU writes 0 to it to release the semaphore. */
1276 /* Indicates for each CPU if coherency is enabled
1296 /* Signals a single CPU is done. */
1348 /* target CPU id to latch its execution PC */
1354 Clear on read latch_pc_high */
1370 Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering …
1388 Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering …
1406 Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering …
1418 [3:2] Target queue - 0:ASI, 1: AMI
1419 [1:0]: Target Processor Cluster - 0: Cluster0, 1: Cluster1 */
1426 Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering …
1437 /* Read barrier is progressed downstream when not terminated in the CCI.
1447 little - 0x0: Little endian
1448 bit - 0x1: Bit endian */
1456 low - 0x0: Exception vectors start at address 0x00000000.
1457 high - 0x1: Exception vectors start at address 0xFFFF0000. */
1481 /* Individual CPU power mode transition request
1482 If requested to enter power mode other than normal mode, low power state is resumed whenever CPU re…
1485 poweredoff: 0x3: Powered-off power mode */
1494 /* Powered-off power mode */
1501 If set, the entire power down sequence is applied, but the CPU is placed in soft reset instead of h…
1503 /* Disable wakeup from Local--GIC FIQ. */
1505 /* Disable wakeup from Local-GIC IRQ. */
1507 /* Disable wakeup from IO-GIC FIQ. */
1509 /* Disable wakeup from IO-GIC IRQ. */
1511 /* Disable scheduling of interrrupts in GIC(500) to non-active CPU */
1515 /* Read-only bits that reflect the individual CPU power mode status.
1516 Default value for non-exist CPU is 2b11:
1517 normal - 0x0: Normal mode
1518 por - 0x1: por on reset mode
1519 deep_idle - 0x2: Dormant power mode state
1520 poweredoff - 0x3: Powered-off power mode */
1532 /* Powered-off power mode */
1541 /* Disable CPU Warm Reset when warmrstreq is asserted
1543 When the Reset Request bit in the RMR or RMR_EL3 register is set to 1 in the CPU Core , the process…
1547 /* CPU Core AARach64 reset vector bar
1553 /* CPU Core AARach64 reset vector bar high bits
1568 /* CPU read this register to receive input (char) from simulation. */
1572 Cleared on read */
1583 disable - 0x0: Disable interrupt on overflow.
1584 enable - 0x1: Enable interrupt on overflow. */
1599 disable - 0x0: Disable setting.
1600 enable - 0x1: Enable setting. */
1603 disable - 0x0: Disable setting.
1604 enable - 0x1: Enable setting. */
1607 disable - 0x0: Disable pause.
1608 enable - 0x1: Enable pause. */
1612 disable - 0x0: Disable trigger out.
1613 enable - 0x1: Enable trigger out. */
1617 0x0: 1 - Trigger out on every event occurrence.
1618 0x1: 2 - Trigger out on every two events.
1620 0xn: 2^(n-1) - Trigger out on event 2^(n-1) events.
1626 …r counter <i>, current counter pauses counting when counter<i> is overflowed, including self-pause.
1635 0x0 - disable: Disable counter.
1636 0x1 - enable: Enable counter.
1637 0x3 - pause: Pause counter. */
1679 /* Target-ID */
1687 /* Disable clear exclusive monitor request from DDR controller to CPU
1694 /* Number of available AXI transactions (used positions) in the DDR controller read address FIFO. */
1700 /* Number of available Low priority read CAM slots (free positions) in the DDR controller.
1704 /* Number of available High priority read CAM slots (free positions) in the DDR controller.
1720 /* On-Chip Write data parity error interrupt on output */
1726 /* AXI Read address parity error interrupt.
1727 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI read add…
1729 /* AXI Read data parity error interrupt.
1730 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI read dat…
1733 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI write ad…
1736 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI write da…
1757 When set, addrmap_row_b2-5 are used inside DDR controler instead of the built in address mapping re…
1761 /* DDR Read Reorder buffer ID mask.
1762 If incoming read transaction ID ANDed with mask is equal Reorder_ID_Value, then the transaction is …
1768 /* DDR Read Reorder buffer ID value
1769 If incoming read transaction ID ANDed with Reorder_ID_Mask is equal to this register, then the tran…
1774 /* DDR4 Mode Register Read Data Valid */