Lines Matching +full:0 +full:x0000003c
60 /* [0x0] */
62 /* [0x4] */
64 /* [0x8] Force init reset. */
66 /* [0xc] Force init reset per DECEI mode. */
68 /* [0x10] */
70 /* [0x14] */
72 /* [0x18] */
74 /* [0x1c] */
76 /* [0x20] */
78 /* [0x24] */
80 /* [0x28] */
82 /* [0x2c] */
84 /* [0x30] */
86 /* [0x34] */
88 /* [0x38] */
90 /* [0x3c] */
92 /* [0x40] */
95 /* [0x60] */
97 /* [0x64] */
99 /* [0x68] */
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
109 /* [0x7c] */
111 /* [0x80] */
113 /* [0x84] */
115 /* [0x88] */
117 /* [0x8c] */
119 /* [0x90] */
121 /* [0x94] */
123 /* [0x98] */
126 /* [0xa0] */
128 /* [0xa4] */
130 /* [0xa8] */
133 /* [0xd0] */
135 /* [0xd4] */
138 /* [0xe0] */
141 /* [0xf0] */
143 /* [0xf4] */
145 /* [0xf8] */
147 /* [0xfc] */
149 /* [0x100] */
151 /* [0x104] */
154 /* [0x110] */
157 /* [0x120] */
159 /* [0x124] */
161 /* [0x128] */
163 /* [0x12c] */
165 /* [0x130] */
167 /* [0x134] */
170 /* [0x160] */
172 /* [0x164] */
174 /* [0x168] */
176 /* [0x16c] */
181 /* [0x0] */
183 /* [0x4] */
185 /* [0x8] */
187 /* [0xc] */
189 /* [0x10] */
191 /* [0x14] */
196 /* [0x0] */
199 /* [0x8] */
204 /* [0x0] */
206 /* [0x4] */
208 /* [0x8] */
213 /* [0x0] This configuration is only sampled during reset of the processor */
217 /* [0x0] */
219 /* [0x4] */
222 /* [0x10] */
224 /* [0x20] */
226 /* [0x24] */
229 /* [0x30] */
231 /* [0x34] */
234 /* [0x40] */
236 /* [0x44] */
238 /* [0x48] */
241 /* [0x60] */
244 /* [0x70] */
246 /* [0x74] */
249 /* [0x80] */
252 /* [0x90] */
255 /* [0x98] */
257 /* [0x9c] */
260 /* [0x100] */
262 /* [0x104] */
264 /* [0x108] */
267 /* [0x120] */
270 /* [0x130] */
272 /* [0x134] */
274 /* [0x138] */
277 /* [0x140] */
279 /* [0x144] */
281 /* [0x148] */
284 /* [0x150] */
286 /* [0x154] */
288 /* [0x158] */
291 /* [0x160] */
293 /* [0x164] */
298 /* [0x0] This configuration is only sampled during reset of the processor. */
300 /* [0x4] This configuration is only sampled during reset of the processor. */
302 /* [0x8] */
305 /* [0x10] */
307 /* [0x14] */
310 /* [0x20] Specifies the state of the CPU with reference to power modes. */
312 /* [0x24] */
314 /* [0x28] */
316 /* [0x2c] */
319 /* [0x40] */
322 /* [0x48] */
324 /* [0x4c] */
326 /* [0x50] */
329 /* [0x60] */
334 /* [0x0] PMU Global Control Register */
336 /* [0x4] PMU Global Control Register */
341 /* [0x0] Counter Configuration Register */
343 /* [0x4] Counter Control Register */
345 /* [0x8] Counter Control Register */
347 /* [0xc] Counter Control Register */
352 /* [0x0] Northbridge Revision */
357 /* [0x0] */
362 /* [0x0] */
365 /* [0x8] */
368 /* [0x10] */
371 /* [0x18] */
374 /* [0x20] */
377 /* [0x30] */
379 /* [0x34] */
381 /* [0x38] */
383 /* [0x3c] */
385 /* [0x40] */
387 /* [0x44] */
389 /* [0x48] */
391 /* [0x4c] */
393 /* [0x50] */
398 /* [0x0] Counter Configuration Register */
402 /* [0x0] */
405 /* [0x10] */
408 /* [0x20] */
410 /* [0x24] */
413 /* [0x30] */
419 struct al_nb_global global; /* [0x0] */
420 struct al_nb_system_counter system_counter; /* [0x1000] */
421 struct al_nb_rams_control_misc rams_control_misc; /* [0x1100] */
422 struct al_nb_ca15_rams_control ca15_rams_control[5]; /* [0x1200] */
424 struct al_nb_semaphores semaphores[64]; /* [0x1400] */
426 struct al_nb_debug debug; /* [0x1a00] */
428 struct al_nb_cpun_config_status cpun_config_status[4]; /* [0x2000] */
430 struct al_nb_mc_pmu mc_pmu; /* [0x4000] */
431 struct al_nb_mc_pmu_counters mc_pmu_counters[4]; /* [0x4100] */
433 struct al_nb_nb_version nb_version; /* [0x4400] */
435 struct al_nb_sriov sriov; /* [0x4600] */
437 struct al_nb_dram_channels dram_channels; /* [0x4800] */
438 struct al_nb_ddr_0_mrr ddr_0_mrr[9]; /* [0x4900] */
440 uint32_t rsrvd_8[1024]; /* [0x5000] */
441 struct al_nb_push_packet push_packet; /* [0x6000] */
453 #define NB_GLOBAL_CPUS_CONFIG_SYSBARDISABLE (1 << 0)
464 0x0: 1:1
465 0x1: 1:2
466 0x2: 1:3
467 0x3: 1:4
470 #define NB_GLOBAL_CPUS_CONFIG_PERIPHCLKEN_MASK 0x00000030
474 0 Enable the GIC CPU interface logic.
483 #define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF1_MASK 0x00FF0000
488 #define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF2_MASK 0xFF000000
494 #define NB_GLOBAL_CPUS_SECURE_DBGEN (1 << 0)
514 #define NB_GLOBAL_CPUS_INIT_CONTROL_CPUS_INITDONE_MASK 0x0000000F
515 #define NB_GLOBAL_CPUS_INIT_CONTROL_CPUS_INITDONE_SHIFT 0
519 #define NB_GLOBAL_CPUS_INIT_CONTROL_DBGPWRDNREQ_MASK_MASK 0x000000F0
523 #define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_CPUPOR_MASK 0x00000F00
527 #define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_DBGPWRDUP_MASK 0x0000F000
532 sample at rst_cpus_exist[3:0] reset strap. */
533 #define NB_GLOBAL_CPUS_INIT_STATUS_CPUS_EXIST_MASK 0x0000000F
534 #define NB_GLOBAL_CPUS_INIT_STATUS_CPUS_EXIST_SHIFT 0
539 * value is 1 for level irq, 0 for trigger irq
542 #define NB_GLOBAL_NB_INT_CAUSE_LEVEL_IRQ_MASK 0x3D803000
544 #define NB_GLOBAL_NB_INT_CAUSE_NCTIIRQ_MASK 0x0000000F
545 #define NB_GLOBAL_NB_INT_CAUSE_NCTIIRQ_SHIFT 0
547 #define NB_GLOBAL_NB_INT_CAUSE_COMMRX_MASK 0x000000F0
550 #define NB_GLOBAL_NB_INT_CAUSE_COMMTX_MASK 0x00000F00
554 /* Error indicator for AXI write transactions with a BRESP error condition. Writing 0 to bit[29] of…
578 /* SMMU 0/1 global non-secure fault interrupt */
579 #define NB_GLOBAL_SEV_INT_CAUSE_SMMU_GBL_FLT_IRPT_NS_MASK 0x00000003
580 #define NB_GLOBAL_SEV_INT_CAUSE_SMMU_GBL_FLT_IRPT_NS_SHIFT 0
581 /* SMMU 0/1 non-secure context interrupt */
582 #define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CXT_IRPT_NS_MASK 0x0000000C
585 #define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CFG_FLT_IRPT_S_MASK 0x00000030
588 #define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_11_6_MASK 0x00000FC0
591 #define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_31_20_MASK 0xFFF00000
596 #define NB_GLOBAL_PMUS_INT_CAUSE_CPUS_OVFL_MASK 0x0000000F
597 #define NB_GLOBAL_PMUS_INT_CAUSE_CPUS_OVFL_SHIFT 0
603 #define NB_GLOBAL_PMUS_INT_CAUSE_CCI_OVFL_MASK 0x000007C0
606 #define NB_GLOBAL_PMUS_INT_CAUSE_SMMU_OVFL_MASK 0x00001800
609 #define NB_GLOBAL_PMUS_INT_CAUSE_RESERVED_23_13_MASK 0x00FFE000
612 #define NB_GLOBAL_PMUS_INT_CAUSE_SB_PMUS_OVFL_MASK 0xFF000000
618 #define NB_GLOBAL_CPUS_HOLD_RESET_L2RESET (1 << 0)
622 #define NB_GLOBAL_CPUS_HOLD_RESET_CPU_DBGRESET_MASK 0x000000F0
626 #define NB_GLOBAL_CPUS_HOLD_RESET_CPU_CORERESET_MASK 0x00000F00
630 #define NB_GLOBAL_CPUS_HOLD_RESET_CPU_PORESET_MASK 0x0000F000
634 #define NB_GLOBAL_CPUS_HOLD_RESET_WFI_MASK_MASK 0x000F0000
639 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_SWRESET_REQ (1 << 0)
641 0x0 - cpu_core: Individual CPU core reset.
642 0x1 - cpu_poreset: Individual CPU power-on-reset.
643 0x2 - cpu_dbg: Individual CPU debug reset.
644 0x3 - cluster_no_dbg: A Cluster reset puts each core into core reset (no dbg) and also resets the i…
645 0x4 - cluster: A Cluster reset puts each core into power-on-reset and also resets the interrupt con…
646 0x5 - cluster_poreset: A Cluster power-on-reset puts each core into power-on-reset and also resets …
647 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_MASK 0x0000000E
651 (0x0 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
654 (0x1 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
657 (0x2 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
660 (0x3 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
663 (0x4 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
666 (0x5 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
668 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_CORES_MASK 0x000000F0
672 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_WFI_MASK_MASK 0x000F0000
677 #define NB_GLOBAL_WD_TIMER0_RESET_L2RESET (1 << 0)
681 #define NB_GLOBAL_WD_TIMER0_RESET_CPU_DBGRESET_MASK 0x000000F0
684 #define NB_GLOBAL_WD_TIMER0_RESET_CPU_CORERESET_MASK 0x00000F00
687 #define NB_GLOBAL_WD_TIMER0_RESET_CPU_PORESET_MASK 0x0000F000
692 #define NB_GLOBAL_WD_TIMER1_RESET_L2RESET (1 << 0)
696 #define NB_GLOBAL_WD_TIMER1_RESET_CPU_DBGRESET_MASK 0x000000F0
699 #define NB_GLOBAL_WD_TIMER1_RESET_CPU_CORERESET_MASK 0x00000F00
702 #define NB_GLOBAL_WD_TIMER1_RESET_CPU_PORESET_MASK 0x0000F000
707 #define NB_GLOBAL_WD_TIMER2_RESET_L2RESET (1 << 0)
711 #define NB_GLOBAL_WD_TIMER2_RESET_CPU_DBGRESET_MASK 0x000000F0
714 #define NB_GLOBAL_WD_TIMER2_RESET_CPU_CORERESET_MASK 0x00000F00
717 #define NB_GLOBAL_WD_TIMER2_RESET_CPU_PORESET_MASK 0x0000F000
722 #define NB_GLOBAL_WD_TIMER3_RESET_L2RESET (1 << 0)
726 #define NB_GLOBAL_WD_TIMER3_RESET_CPU_DBGRESET_MASK 0x000000F0
729 #define NB_GLOBAL_WD_TIMER3_RESET_CPU_CORERESET_MASK 0x00000F00
732 #define NB_GLOBAL_WD_TIMER3_RESET_CPU_PORESET_MASK 0x0000F000
737 0 - Reset is deasserted.
739 #define NB_GLOBAL_DDRC_HOLD_RESET_APB_SYNC_RESET (1 << 0)
741 0 - Reset is deasserted.
743 This field must be set to 0 to start the initialization process after configuring the DDR Controlle…
746 0 - Reset is deasserted.
748 This field must not be set to 0 while core_sync_reset is set to 1. */
751 0 - Reset is deasserted.
753 This field must be set to 0 to start the initialization process after configuring the PUB Controlle…
756 0 - Reset is deasserted.
758 This field must be set to 0 to start the initialization process after configuring the PUB Controlle…
761 0 - Reset is deasserted.
769 #define NB_GLOBAL_FABRIC_SOFTWARE_RESET_SWRESET_REQ (1 << 0)
771 0x0 - fabric: Fabric reset
772 0x1 - gic: GIC reset
773 0x2 - smmu: SMMU reset */
774 #define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_MASK 0x0000000E
778 (0x0 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT)
781 (0x1 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT)
784 (0x2 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT)
787 #define NB_GLOBAL_FABRIC_SOFTWARE_RESET_WFI_MASK_MASK 0x000F0000
795 #define NB_GLOBAL_CPUS_POWER_CTRL_L2WFI_EN (1 << 0)
804 0 - Power down
807 #define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_CPUS_STATE_MASK 0x000000F0
813 0 L2 hardware flush request is not asserted. flush is performed by SW
820 #define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_SM_STATUS_MASK 0xF0000000
825 #define NB_GLOBAL_ACF_BASE_HIGH_BASE_39_32_MASK 0x000000FF
826 #define NB_GLOBAL_ACF_BASE_HIGH_BASE_39_32_SHIFT 0
828 #define NB_GLOBAL_ACF_BASE_LOW_BASED_31_15_MASK 0xFFFF8000
832 /* Override the AWCACHE[0] and ARCACHE[0] outputs to be
834 Connected to BUFFERABLEOVERRIDE[2:0] */
835 #define NB_GLOBAL_ACF_CONTROL_OVERRIDE_BUFFOVRD_MASK 0x00000007
836 #define NB_GLOBAL_ACF_CONTROL_OVERRIDE_BUFFOVRD_SHIFT 0
839 Connected to QOSOVERRIDE[4:0] */
840 #define NB_GLOBAL_ACF_CONTROL_OVERRIDE_QOSOVRD_MASK 0x000000F8
844 Connected to ACCHANNELEN[4:0]. */
845 #define NB_GLOBAL_ACF_CONTROL_OVERRIDE_ACE_CH_EN_MASK 0x00001F00
854 #define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_MASK 0x000000FF
855 #define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_SHIFT 0
856 #define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_MASK_ALPINE_V2 0x00000FFF
857 #define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_SHIFT_ALPINE_V2 0
860 #define NB_GLOBAL_LGIC_BASE_LOW_BASED_31_15_MASK 0xFFFF8000
865 #define NB_GLOBAL_IOGIC_BASE_HIGH_BASE_39_32_MASK 0x000000FF
866 #define NB_GLOBAL_IOGIC_BASE_HIGH_BASE_39_32_SHIFT 0
868 #define NB_GLOBAL_IOGIC_BASE_LOW_BASED_31_15_MASK 0xFFFF8000
873 [0] Splitter 0 bypass enable
875 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_BYPASS_MASK 0x00000003
876 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_BYPASS_SHIFT 0
879 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_ST_FW_MASK 0x0000000C
883 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNMODIFY_SNP_MASK 0x00000030
887 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNSPLIT_NOSNP_MASK 0x000000C0
890 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR0_SPLT_RATE_LIMIT_MASK 0x00001F00
893 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR1_SPLT_RATE_LIMIT_MASK 0x0003E000
897 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_REMAP_64BIT_EN_MASK 0x000C0000
901 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_CLEAR_MASK 0xC0000000
906 [0] Rd ROB 0 bypass enable.
908 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_BYPASS_MASK 0x00000003
909 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_BYPASS_SHIFT 0
912 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_INORDER_MASK 0x0000000C
916 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_RSP_RATE_MASK 0x00000030
919 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD0_ROB_RATE_LIMIT_MASK 0x00001F00
922 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD1_ROB_RATE_LIMIT_MASK 0x0003E000
927 [7:0] address_high
930 #define NB_GLOBAL_SB_POS_ERROR_LOG_1_ERR_LOG_MASK 0x7FFFFFFF
931 #define NB_GLOBAL_SB_POS_ERROR_LOG_1_ERR_LOG_SHIFT 0
940 Corresponds to MSIx address message [30:0]. */
941 #define NB_GLOBAL_MSIX_ERROR_LOG_ERR_LOG_MASK 0x7FFFFFFF
942 #define NB_GLOBAL_MSIX_ERROR_LOG_ERR_LOG_SHIFT 0
951 /* Write data parity error from SB channel 0. */
963 /* Error indicator for AXI write transactions with a BRESP error condition. Writing 0 to bit[29] of…
973 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_L_THRESHOLD_MASK 0x0000007F
974 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_L_THRESHOLD_SHIFT 0
977 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_H_THRESHOLD_MASK 0x00007F00
981 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_L_THRESHOLD_MASK 0x007F0000
985 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_H_THRESHOLD_MASK 0x7F000000
990 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_ARQOS_MASK 0x0000000F
991 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_ARQOS_SHIFT 0
993 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_ARQOS_MASK 0x000000F0
996 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_AWQOS_MASK 0x00000F00
999 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_AWQOS_MASK 0x0000F000
1002 #define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_ARQOS_MASK 0x000F0000
1005 #define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_AWQOS_MASK 0x00F00000
1012 #define NB_GLOBAL_DDR_QOS_HIGH_PRIO_THRESHOLD_MASK 0x0000007F
1013 #define NB_GLOBAL_DDR_QOS_HIGH_PRIO_THRESHOLD_SHIFT 0
1016 #define NB_GLOBAL_DDR_QOS_LP_QOS_MASK 0x00000F00
1022 #define NB_GLOBAL_ACF_MISC_DDR_WR_CHOP_DIS (1 << 0)
1089 #define NB_GLOBAL_CONFIG_BUS_CONTROL_WR_SLV_ERR_EN (1 << 0)
1099 #define NB_GLOBAL_CONFIG_BUS_CONTROL_TIMEOUT_LIMIT_MASK 0xFFFFFF00
1104 #define NB_GLOBAL_POS_ID_MATCH_ENABLE (1 << 0)
1107 #define NB_GLOBAL_POS_ID_MATCH_MASK_MASK 0xFFFF0000
1113 #define NB_GLOBAL_SB_SEL_OVERRIDE_AWUSER_SEL_MASK 0x03FFFFFF
1114 #define NB_GLOBAL_SB_SEL_OVERRIDE_AWUSER_SEL_SHIFT 0
1119 #define NB_GLOBAL_SB_OVERRIDE_AWUSER_AWUSER_MASK 0x03FFFFFF
1120 #define NB_GLOBAL_SB_OVERRIDE_AWUSER_AWUSER_SHIFT 0
1125 #define NB_GLOBAL_SB_SEL_OVERRIDE_ARUSER_SEL_MASK 0x03FFFFFF
1126 #define NB_GLOBAL_SB_SEL_OVERRIDE_ARUSER_SEL_SHIFT 0
1131 #define NB_GLOBAL_SB_OVERRIDE_ARUSER_ARUSER_MASK 0x03FFFFFF
1132 #define NB_GLOBAL_SB_OVERRIDE_ARUSER_ARUSER_SHIFT 0
1136 #define NB_GLOBAL_CORESIGHT_PD_ETF0_RAM_FORCE_PD (1 << 0)
1150 #define NB_GLOBAL_CORESIGHT_INTERNAL_0_CTIAPBSBYPASS (1 << 0)
1155 #define NB_GLOBAL_CORESIGHT_INTERNAL_0_CIHSBYPASS_MASK 0x0000003C
1161 #define NB_GLOBAL_CORESIGHT_DBGROMADDR_VALID (1 << 0)
1163 #define NB_GLOBAL_CORESIGHT_DBGROMADDR_ADDR_39_12_MASK 0x3FFFFFFC
1169 #define NB_GLOBAL_CORESIGHT_DBGSELFADDR_VALID (1 << 0)
1171 Note: The CA15 debug unit starts at offset 0x1 within the Coresight cluster. */
1172 #define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_18_17_MASK 0x00000180
1175 Note: The CA15 debug unit starts at offset 0x1 within the Coresight cluster, so this offset if fixe…
1176 #define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_39_19_MASK 0x3FFFFE00
1180 /* Enables force same id mechanism for SB port 0 */
1181 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_FORCE_SAME_ID_EN (1 << 0)
1182 /* Enables MSIx stall when write transactions from same ID mechanism are in progress for SB port 0 …
1185 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_SB_MSTR_ID_MASK_MASK 0x000000F8
1190 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_FORCE_SAME_ID_EN (1 << 0)
1194 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_SB_MSTR_ID_MASK_MASK 0x000000F8
1200 #define NB_SYSTEM_COUNTER_CNT_CONTROL_EN (1 << 0)
1203 Transition from 0 to 1 reloads the register. */
1208 …he Northbridge clock, e.g., the counter is incremented every 16 NB cycles if programmed to 0x0f. */
1209 #define NB_SYSTEM_COUNTER_CNT_CONTROL_SCALE_MASK 0x0000FF00
1214 #define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_NONECPU_RF_MISC_MASK 0x0000000F
1215 #define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_NONECPU_RF_MISC_SHIFT 0
1217 #define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_CPU_RF_MISC_MASK 0x00FFFF00
1220 #define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_PWR_UP_PAUSE_MASK 0xF8000000
1225 #define NB_RAMS_CONTROL_MISC_NB_RF_MISC_SMMU_RAM_FORCE_PD (1 << 0)
1230 If current value ==0, return 0 to CPU but set bit to 1. (CPU knows it captured the semaphore.)
1232 CPU writes 0 to it to release the semaphore. */
1233 #define NB_SEMAPHORES_LOCKN_LOCK (1 << 0)
1238 #define NB_DEBUG_CA15_OUTPUTS_1_STANDBYWFI_MASK 0x0000000F
1239 #define NB_DEBUG_CA15_OUTPUTS_1_STANDBYWFI_SHIFT 0
1242 #define NB_DEBUG_CA15_OUTPUTS_1_CPU_PWR_DN_ACK_MASK 0x000000F0
1246 #define NB_DEBUG_CA15_OUTPUTS_1_IRQOUT_N_MASK 0x00000F00
1250 #define NB_DEBUG_CA15_OUTPUTS_1_FIQOUT_N_MASK 0x0000F000
1254 #define NB_DEBUG_CA15_OUTPUTS_1_CNTHPIRQ_N_MASK 0x000F0000
1258 #define NB_DEBUG_CA15_OUTPUTS_1_NCNTPNSIRQ_N_MASK 0x00F00000
1262 #define NB_DEBUG_CA15_OUTPUTS_1_NCNTPSIRQ_N_MASK 0x0F000000
1266 #define NB_DEBUG_CA15_OUTPUTS_1_NCNTVIRQ_N_MASK 0xF0000000
1272 #define NB_DEBUG_CA15_OUTPUTS_2_STANDBYWFIL2 (1 << 0)
1278 #define NB_DEBUG_CA15_OUTPUTS_2_SMPEN_MASK 0x0000003C
1283 #define NB_DEBUG_CPU_MSG_STATUS_MASK 0x000000FF
1284 #define NB_DEBUG_CPU_MSG_STATUS_SHIFT 0
1290 #define NB_DEBUG_CPU_MSG_RESERVED_11_10_MASK 0x00000C00
1303 #define NB_DEBUG_DDRC_DLL_CALIB_EXT_REQ (1 << 0)
1307 #define NB_DEBUG_DDRC_RANK_REFRESH_EXT_REQ_MASK 0x0000003C
1312 #define NB_DEBUG_DDRC_PHY_SMODE_CONTROL_CTL_MASK 0x0000FFFF
1313 #define NB_DEBUG_DDRC_PHY_SMODE_CONTROL_CTL_SHIFT 0
1317 #define NB_DEBUG_DDRC_PHY_SMODE_STATUS_STT_MASK 0x0000FFFF
1318 #define NB_DEBUG_DDRC_PHY_SMODE_STATUS_STT_SHIFT 0
1322 #define NB_DEBUG_PMC_SYS_EN (1 << 0)
1324 #define NB_DEBUG_PMC_HVT35_VAL_14_0_MASK 0x0000FFFE
1327 #define NB_DEBUG_PMC_SVT31_VAL_14_0_MASK 0x7FFF0000
1336 #define NB_DEBUG_CPUS_INT_OUT_FIQ_EN_MASK 0x0000000F
1337 #define NB_DEBUG_CPUS_INT_OUT_FIQ_EN_SHIFT 0
1338 /* Defines which CPUs' IRQ will be triggered out through the cpus_int_out[0] pinout. */
1339 #define NB_DEBUG_CPUS_INT_OUT_IRQ_EN_MASK 0x000000F0
1341 /* Defines which CPUs' SEI will be triggered out through the cpus_int_out[0] pinout. */
1342 #define NB_DEBUG_CPUS_INT_OUT_IRQ_SEI_EN_MASK 0x00000F00
1347 #define NB_DEBUG_LATCH_PC_REQ_EN (1 << 0)
1349 #define NB_DEBUG_LATCH_PC_REQ_CPU_ID_MASK 0x000000F0
1355 #define NB_DEBUG_LATCH_PC_LOW_VALID (1 << 0)
1357 #define NB_DEBUG_LATCH_PC_LOW_VAL_MASK 0xFFFFFFFE
1363 [1:0]: CCI target master: 2'b00: M0, 2'b01: M1, 2'b10: M2 */
1364 #define NB_DEBUG_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
1365 #define NB_DEBUG_TRACK_DUMP_CTRL_PTR_SHIFT 0
1375 #define NB_DEBUG_TRACK_DUMP_RDATA_0_VALID (1 << 0)
1377 #define NB_DEBUG_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
1382 #define NB_DEBUG_POS_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
1383 #define NB_DEBUG_POS_TRACK_DUMP_CTRL_PTR_SHIFT 0
1393 #define NB_DEBUG_POS_TRACK_DUMP_RDATA_0_VALID (1 << 0)
1395 #define NB_DEBUG_POS_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
1400 #define NB_DEBUG_C2SWB_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
1401 #define NB_DEBUG_C2SWB_TRACK_DUMP_CTRL_PTR_SHIFT 0
1411 #define NB_DEBUG_C2SWB_TRACK_DUMP_RDATA_0_VALID (1 << 0)
1413 #define NB_DEBUG_C2SWB_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
1418 [3:2] Target queue - 0:ASI, 1: AMI
1419 [1:0]: Target Processor Cluster - 0: Cluster0, 1: Cluster1 */
1420 #define NB_DEBUG_CPUS_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
1421 #define NB_DEBUG_CPUS_TRACK_DUMP_CTRL_PTR_SHIFT 0
1431 #define NB_DEBUG_CPUS_TRACK_DUMP_RDATA_0_VALID (1 << 0)
1433 #define NB_DEBUG_CPUS_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
1438 By specification, barrier address is 0x0.
1440 #define NB_DEBUG_C2SWB_BAR_OVRD_HIGH_RD_ADDR_OVRD_EN (1 << 0)
1442 #define NB_DEBUG_C2SWB_BAR_OVRD_HIGH_ADDR_39_32_MASK 0x00FF0000
1447 little - 0x0: Little endian
1448 bit - 0x1: Bit endian */
1449 #define NB_CPUN_CONFIG_STATUS_CONFIG_ENDIAN (1 << 0)
1451 arm: 0x0: Exception operates ARM code.
1452 Thumb: 0x1: Exception operates Thumb code. */
1456 low - 0x0: Exception vectors start at address 0x00000000.
1457 high - 0x1: Exception vectors start at address 0xFFFF0000. */
1469 0 AArch32.
1473 #define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_AA64_NAA32 (1 << 0)
1475 0 Enable the Cryptography engine.
1483 normal: 0x0: normal power state
1484 deep_idle: 0x2: Dormant power mode state
1485 poweredoff: 0x3: Powered-off power mode */
1486 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_MASK 0x00000003
1487 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT 0
1490 (0x0 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT)
1493 (0x2 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT)
1496 (0x3 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT)
1517 normal - 0x0: Normal mode
1518 por - 0x1: por on reset mode
1519 deep_idle - 0x2: Dormant power mode state
1520 poweredoff - 0x3: Powered-off power mode */
1521 #define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_MASK 0x00000003
1522 #define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT 0
1525 (0x0 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
1528 (0x1 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
1531 (0x2 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
1534 (0x3 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
1544 #define NB_CPUN_CONFIG_STATUS_WARM_RST_CTL_REQ_DIS (1 << 0)
1549 #define NB_CPUN_CONFIG_STATUS_RVBAR_LOW_ADDR_31_2_MASK 0xFFFFFFFC
1555 #define NB_CPUN_CONFIG_STATUS_RVBAR_HIGH_ADDR_43_32_MASK 0x00000FFF
1556 #define NB_CPUN_CONFIG_STATUS_RVBAR_HIGH_ADDR_43_32_SHIFT 0
1560 #define NB_CPUN_CONFIG_STATUS_PMU_SNAPSHOT_REQ (1 << 0)
1561 /* 0: HW deassert requests when received ack
1569 #define NB_CPUN_CONFIG_STATUS_CPU_MSG_IN_DATA_MASK 0x000000FF
1570 #define NB_CPUN_CONFIG_STATUS_CPU_MSG_IN_DATA_SHIFT 0
1578 #define NB_MC_PMU_PMU_CONTROL_DISABLE_ALL (1 << 0)
1583 disable - 0x0: Disable interrupt on overflow.
1584 enable - 0x1: Enable interrupt on overflow. */
1587 #define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_MASK 0x00FC0000
1591 #define NB_MC_PMU_PMU_CONTROL_NUM_OF_CNTS_MASK 0x0F000000
1596 #define NB_MC_PMU_COUNTERS_CFG_EVENT_SEL_MASK 0x0000003F
1597 #define NB_MC_PMU_COUNTERS_CFG_EVENT_SEL_SHIFT 0
1599 disable - 0x0: Disable setting.
1600 enable - 0x1: Enable setting. */
1603 disable - 0x0: Disable setting.
1604 enable - 0x1: Enable setting. */
1607 disable - 0x0: Disable pause.
1608 enable - 0x1: Enable pause. */
1612 disable - 0x0: Disable trigger out.
1613 enable - 0x1: Enable trigger out. */
1617 0x0: 1 - Trigger out on every event occurrence.
1618 0x1: 2 - Trigger out on every two events.
1620 0xn: 2^(n-1) - Trigger out on event 2^(n-1) events.
1622 0x1F: 2^31 */
1623 #define NB_MC_PMU_COUNTERS_CFG_TRIGOUT_GRANULA_MASK 0x00007C00
1627 Bit [16]: counter 0
1630 #define NB_MC_PMU_COUNTERS_CFG_PAUSE_ON_OVRF_BITMASK_MASK 0x000F0000
1635 0x0 - disable: Disable counter.
1636 0x1 - enable: Enable counter.
1637 0x3 - pause: Pause counter. */
1638 #define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_MASK 0x00000003
1639 #define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT 0
1642 (0x0 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT)
1645 (0x1 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT)
1648 (0x3 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT)
1652 #define NB_MC_PMU_COUNTERS_HIGH_COUNTER_MASK 0x0000FFFF
1653 #define NB_MC_PMU_COUNTERS_HIGH_COUNTER_SHIFT 0
1657 #define NB_NB_VERSION_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
1658 #define NB_NB_VERSION_VERSION_RELEASE_NUM_MINOR_SHIFT 0
1660 #define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
1666 #define NB_NB_VERSION_VERSION_DATE_DAY_MASK 0x001F0000
1669 #define NB_NB_VERSION_VERSION_DATA_MONTH_MASK 0x01E00000
1672 #define NB_NB_VERSION_VERSION_DATE_YEAR_MASK 0x3E000000
1675 #define NB_NB_VERSION_VERSION_RESERVED_MASK 0xC0000000
1680 #define NB_SRIOV_CPU_TGTID_VAL_MASK 0x000000FF
1681 #define NB_SRIOV_CPU_TGTID_VAL_SHIFT 0
1686 #define NB_DRAM_CHANNELS_DRAM_0_CONTROL_DDR_PHY_CTL_IDLE (1 << 0)
1693 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_DDR_PHY_BYP_MODE (1 << 0)
1695 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_RAQ_WCOUNT_MASK 0x00000030
1698 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_WAQ_WCOUNT_0_MASK 0x000000C0
1702 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_LPR_CREDIT_CNT_MASK 0x00007F00
1706 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_HPR_CREDIT_CNT_MASK 0x003F8000
1710 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_WR_CREDIT_CNT_MASK 0x1FC00000
1715 #define NB_DRAM_CHANNELS_DDR_INT_CAUSE_ECC_CORRECTED_ERR (1 << 0)
1742 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B2_MASK 0x0000000F
1743 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B2_SHIFT 0
1746 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B3_MASK 0x000003C0
1750 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B4_MASK 0x0000F000
1754 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B5_MASK 0x003C0000
1763 Setting this register to 0 will disable the check */
1764 #define NB_DRAM_CHANNELS_REORDER_ID_MASK_MASK_MASK 0x003FFFFF
1765 #define NB_DRAM_CHANNELS_REORDER_ID_MASK_MASK_SHIFT 0
1770 #define NB_DRAM_CHANNELS_REORDER_ID_VALUE_VALUE_MASK 0x003FFFFF
1771 #define NB_DRAM_CHANNELS_REORDER_ID_VALUE_VALUE_SHIFT 0
1775 #define NB_DRAM_CHANNELS_MRR_CONTROL_STATUS_MRR_VLD (1 << 0)
1776 …ted it clears the mrr_val indication and ready to load new MRR data. Write 1 to clear and then 0 */
1781 #define NB_PUSH_PACKET_PP_CONFIG_FM_BYPASS (1 << 0)
1799 #define NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE_MASK 0x00030000
1809 #define NB_PUSH_PACKET_PP_EXT_AWUSER_AWUSER_MASK 0x03FFFFFF
1810 #define NB_PUSH_PACKET_PP_EXT_AWUSER_AWUSER_SHIFT 0
1815 #define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_MASK 0x0000FFFF
1816 #define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_SHIFT 0