Lines Matching +full:0 +full:x40e
57 #define X86BIOS_MEM_SIZE 0x00100000 /* 1M */
61 " (ax=0x%04x bx=0x%04x cx=0x%04x dx=0x%04x es=0x%04x di=0x%04x)\n",\
64 } while (0)
71 SYSCTL_INT(_debug_x86bios, OID_AUTO, call, CTLFLAG_RWTUN, &x86bios_trace_call, 0,
74 SYSCTL_INT(_debug_x86bios, OID_AUTO, int, CTLFLAG_RWTUN, &x86bios_trace_int, 0,
122 if (offset == NULL || size == 0)
124 vaddr = contigmalloc(size, M_DEVBUF, flags, 0, X86BIOS_MEM_SIZE,
125 PAGE_SIZE, 0);
129 for (i = 0; i < atop(round_page(size)); i++)
144 if (addr == NULL || size == 0)
147 if (paddr >= X86BIOS_MEM_SIZE || (paddr & PAGE_MASK) != 0)
150 for (i = 0; i < x86bios_vmc.npages; i++)
161 while (--i >= 0 && x86bios_vmc.pmap[i].kva == 0)
181 X86BIOS_TRACE(Calling 0x%06x, (seg << 4) + off, regs);
193 X86BIOS_TRACE(Exiting 0x%06x, (seg << 4) + off, regs);
216 X86BIOS_TRACE(Calling INT 0x%02x, intno, regs);
226 X86BIOS_TRACE(Exiting INT 0x%02x, intno, regs);
236 if (addr == 0)
249 return (0);
258 return (0);
265 #define X86BIOS_PAGE_SIZE 0x00001000 /* 4K */
267 #define X86BIOS_IVT_SIZE 0x00000500 /* 1K + 256 (BDA) */
269 #define X86BIOS_IVT_BASE 0x00000000
270 #define X86BIOS_RAM_BASE 0x00001000
271 #define X86BIOS_ROM_BASE 0x000a0000
319 if (addr != 0)
330 for (i = pa / X86BIOS_PAGE_SIZE, j = 0;
357 if ((addr & 1) != 0)
374 if ((addr & 3) != 0)
403 if ((addr & 1) != 0)
420 if ((addr & 3) != 0)
432 if (port == 0xb2) /* APM scratch register */
433 return (0);
434 if (port >= 0x80 && port < 0x88) /* POST status register */
435 return (0);
447 if (port >= 0x80 && port < 0x88) /* POST status register */
448 return (0);
450 if ((port & 1) != 0) {
466 if (port >= 0x80 && port < 0x88) /* POST status register */
467 return (0);
469 if ((port & 1) != 0) {
473 } else if ((port & 2) != 0) {
488 if (port == 0xb2) /* APM scratch register */
490 if (port >= 0x80 && port < 0x88) /* POST status register */
502 if (port >= 0x80 && port < 0x88) /* POST status register */
505 if ((port & 1) != 0) {
518 if (port >= 0x80 && port < 0x88) /* POST status register */
521 if ((port & 1) != 0) {
525 } else if ((port & 2) != 0) {
538 if (offset == NULL || size == 0)
541 x86bios_rom_phys, X86BIOS_PAGE_SIZE, 0);
557 if (addr == NULL || size == 0)
561 paddr % X86BIOS_PAGE_SIZE != 0)
584 X86BIOS_TRACE(Calling 0x%06x, (seg << 4) + off, regs);
588 x86bios_fault = 0;
596 X86BIOS_TRACE(Exiting 0x%06x, (seg << 4) + off, regs);
598 printf("Page fault at 0x%06x from 0x%04x:0x%04x.\n",
622 if (intno < 0 || intno > 255)
626 X86BIOS_TRACE(Calling INT 0x%02x, intno, regs);
630 x86bios_fault = 0;
638 X86BIOS_TRACE(Exiting INT 0x%02x, intno, regs);
640 printf("Page fault at 0x%06x from 0x%04x:0x%04x.\n",
690 x86bios_rom_phys = *(uint16_t *)((caddr_t)x86bios_ivt + 0x40e);
692 if (x86bios_rom_phys != 0 && x86bios_rom_phys < X86BIOS_ROM_BASE &&
711 X86BIOS_ROM_BASE - x86bios_rom_phys, PAT_WRITE_BACK) != 0)
716 X86BIOS_RAM_BASE, x86bios_rom_phys, X86BIOS_PAGE_SIZE, 0);
729 printf("x86bios: IVT 0x%06jx-0x%06jx at %p\n",
733 printf("x86bios: SSEG 0x%06jx-0x%06jx at %p\n",
738 printf("x86bios: EBDA 0x%06jx-0x%06jx at %p\n",
741 printf("x86bios: ROM 0x%06jx-0x%06jx at %p\n",
747 return (0);
761 if (x86bios_map_mem() != 0)
780 return (0);
790 return (0);
802 if (p == NULL || p[0] != 0x55 || p[1] != 0xaa ||
803 (p[3] != 0xe9 && p[3] != 0xeb))
819 return (0);
822 p += le16toh(*(uint16_t *)(p + 0x18));
823 if (bcmp(p, "PCIR", 4) != 0 ||
824 le16toh(*(uint16_t *)(p + 0x0a)) < 0x18 || *(p + 0x14) != 0)
825 return (0);
828 vendor = le16toh(*(uint16_t *)(p + 0x04));
829 device = le16toh(*(uint16_t *)(p + 0x06));
830 progif = *(p + 0x0d);
831 subclass = *(p + 0x0e);
832 class = *(p + 0x0f);
836 return (0);