663 	uint32_t irq_base;  in read_enabler()  local
667 	irq_base = n * 32;  in read_enabler()
670 		    irq_base + i);  in read_enabler()
686 	uint32_t irq_base;  in write_enabler()  local
689 	irq_base = n * 32;  in write_enabler()
697 		    irq_base + i);  in write_enabler()
711 	uint32_t irq_base;  in read_pendr()  local
715 	irq_base = n * 32;  in read_pendr()
718 		    irq_base + i);  in read_pendr()
738 	uint32_t irq_base;  in write_pendr()  local
744 	irq_base = n * 32;  in write_pendr()
751 		    irq_base + i);  in write_pendr()
789 	uint32_t irq_base;  in read_activer()  local
793 	irq_base = n * 32;  in read_activer()
796 		    irq_base + i);  in read_activer()
815 	uint32_t irq_base;  in write_activer()  local
820 	irq_base = n * 32;  in write_activer()
827 		    irq_base + i);  in write_activer()
864 	uint32_t irq_base;  in read_priorityr()  local
868 	irq_base = n * 4;  in read_priorityr()
871 		    irq_base + i);  in read_priorityr()
883 write_priorityr(struct hypctx *hypctx, u_int irq_base, u_int size, uint64_t val)  in write_priorityr()  argument
890 		    irq_base + i);  in write_priorityr()
905 	uint32_t irq_base;  in read_config()  local
909 	irq_base = n * 16;  in read_config()
912 		    irq_base + i);  in read_config()
927 	uint32_t irq_base;  in write_config()  local
930 	irq_base = n * 16;  in write_config()
937 		if (irq_base + i < VGIC_PRV_I_NUM)  in write_config()
941 		    irq_base + i);  in write_config()
1250 	u_int irq_base;  in dist_ipriorityr_write()  local
1252 	irq_base = (reg - GICD_IPRIORITYR(0)) + offset;  in dist_ipriorityr_write()
1254 	MPASS(irq_base > 31);  in dist_ipriorityr_write()
1255 	write_priorityr(hypctx, irq_base, size, wval);  in dist_ipriorityr_write()
1590 	u_int irq_base;  in redist_ipriorityr_write()  local
1592 	irq_base = (reg - GICR_IPRIORITYR(0)) + offset;  in redist_ipriorityr_write()
1593 	write_priorityr(hypctx, irq_base, size, wval);  in redist_ipriorityr_write()