64 #define ATU_CFG_BUS(x)		(((x) & 0x0ff) << 20)
65 #define ATU_CFG_SLOT(x)		(((x) & 0x01f) << 15)
66 #define ATU_CFG_FUNC(x)		(((x) & 0x007) << 12)
67 #define ATU_CFG_REG(x)		(((x) & 0xfff) << 0)
69 #define ATU_TYPE_MEM		0x2
70 #define ATU_TYPE_IO		0x6
71 #define ATU_TYPE_CFG0		0xA
72 #define ATU_TYPE_CFG1		0xB
73 #define ATY_TYPE_NOR_MSG	0xC
82 #define	PCIE_CLIENT_BASIC_STRAP_CONF		0x000000
85 #define	 STRAP_CONF_LANES(n)				((((n) / 2) & 0x3) << 4)
89 #define	 STRAP_CONF_CONF_EN				(1 << 0)
90 #define	PCIE_CLIENT_HOT_RESET_CTRL		0x000018
92 #define	 HOT_RESET_CTRL_HOT_RESET_IN			(1 << 0)
93 #define	PCIE_CLIENT_BASIC_STATUS0		0x000044
94 #define	PCIE_CLIENT_BASIC_STATUS1		0x000048
95 #define	 STATUS1_LINK_ST_GET(x)				(((x) >> 20) & 0x3)
97 #define	PCIE_CLIENT_INT_MASK			0x00004C
98 #define	PCIE_CLIENT_INT_STATUS			0x000050
114 #define	 PCIE_CLIENT_INT_PWR_STCG			(1 << 0)
120 #define	PCIE_CORE_CTRL0				0x900000
121 #define	 CORE_CTRL_LANES_GET(x)				(((x) >> 20) & 0x3)
122 #define	PCIE_CORE_CTRL1				0x900004
123 #define	PCIE_CORE_CONFIG_VENDOR			0x900044
124 #define	PCIE_CORE_INT_STATUS			0x90020c
125 #define	 PCIE_CORE_INT_PRFPE				(1 << 0)
139 #define	PCIE_CORE_INT_MASK			0x900210
140 #define	PCIE_CORE_PHY_FUNC_CONF			0x9002C0
141 #define	PCIE_CORE_RC_BAR_CONF			0x900300
143 #define PCIE_RC_CONFIG_STD_BASE			0x800000
144 #define PCIE_RC_CONFIG_PRIV_BASE		0xA00000
145 #define	PCIE_RC_CONFIG_DCSR			0xA000C8
146 #define	 PCIE_RC_CONFIG_DCSR_MPS_MASK			(0x7 << 5)
147 #define	 PCIE_RC_CONFIG_DCSR_MPS_128			(0 << 5)
149 #define	 PCIE_RC_CONFIG_LINK_CAP		0xA00CC
152 #define	PCIE_RC_CONFIG_LCS			0xA000D0
153 #define	PCIE_RC_CONFIG_THP_CAP			0xA00274
154 #define	 PCIE_RC_CONFIG_THP_CAP_NEXT_MASK		0xFFF00000
156 #define	PCIE_CORE_OB_ADDR0(n)			(0xC00000 + 0x20 * (n) + 0x00)
157 #define	PCIE_CORE_OB_ADDR1(n)			(0xC00000 + 0x20 * (n) + 0x04)
158 #define	PCIE_CORE_OB_DESC0(n)			(0xC00000 + 0x20 * (n) + 0x08)
159 #define	PCIE_CORE_OB_DESC1(n)			(0xC00000 + 0x20 * (n) + 0x0C)
160 #define	PCIE_CORE_OB_DESC2(n)			(0xC00000 + 0x20 * (n) + 0x10)
161 #define	PCIE_CORE_OB_DESC3(n)			(0xC00000 + 0x20 * (n) + 0x14)
163 #define	PCIE_CORE_IB_ADDR0(n)			(0xC00800 + 0x8 * (n) + 0x00)
164 #define	PCIE_CORE_IB_ADDR1(n)			(0xC00800 + 0x8 * (n) + 0x04)
241 	{NULL,		 	 0},
267 		val = 0xFFFFFFFF;  in rk_pcie_local_cfg_read()
290 		val2 &= ~(0xffff << ((reg & 3) << 3));  in rk_pcie_local_cfg_write()
291 		val2 |= ((val & 0xffff) << ((reg & 3) << 3));  in rk_pcie_local_cfg_write()
296 		val2 &= ~(0xff << ((reg & 3) << 3));  in rk_pcie_local_cfg_write()
297 		val2 |= ((val & 0xff) << ((reg & 3) << 3));  in rk_pcie_local_cfg_write()
315 		if (slot > 0 || func > 0)  in rk_pcie_check_dev()
326 	if (bus == sc->sub_bus  && slot != 0 )  in rk_pcie_check_dev()
339 	max_size = idx == 0 ? ATU_OB_REGION_0_SIZE: ATU_OB_REGION_SIZE;  in rk_pcie_map_out_atu()
346 	addr0 = (uint32_t)pa & 0xFFFFFF00;  in rk_pcie_map_out_atu()
370 	APB_WR4(sc, PCIE_CORE_OB_ADDR1(idx), 0);  in rk_pcie_map_cfg_atu()
389 	addr0 = (uint32_t)pa & 0xFFFFFF00;  in rk_pcie_map_in_atu()
404 	for (i = 0; i < nranges; i++) {  in rk_pcie_decode_ranges()
407 			if (sc->io_range.size != 0) {  in rk_pcie_decode_ranges()
417 				if (sc->pref_mem_range.size != 0) {  in rk_pcie_decode_ranges()
425 				if (sc->mem_range.size != 0) {  in rk_pcie_decode_ranges()
435 	if (sc->mem_range.size == 0) {  in rk_pcie_decode_ranges()
440 	return (0);  in rk_pcie_decode_ranges()
461 		return (0xFFFFFFFFU);  in rk_pcie_read_config()
468 	rk_pcie_map_cfg_atu(sc, 0, type);  in rk_pcie_read_config()
485 	if (ret != 0)  in rk_pcie_read_config()
486 		data = 0xFFFFFFFF;  in rk_pcie_read_config()
509 	rk_pcie_map_cfg_atu(sc, 0, type);  in rk_pcie_write_config()
536 	if (rv != 0)  in rk_pcie_alloc_msi()
551 	if (rv != 0)  in rk_pcie_release_msi()
567 	if (rv != 0)  in rk_pcie_map_msi()
582 	if (rv != 0)  in rk_pcie_alloc_msix()
596 	if (rv != 0)  in rk_pcie_release_msix()
619 	if (rv != 0)  in rk_pcie_get_id()
623 	return (0);  in rk_pcie_get_id()
651 	rv = regulator_get_by_ofw_property(sc->dev, 0,  in rk_pcie_parse_fdt_resources()
653 	if (rv != 0 && rv != ENOENT) {  in rk_pcie_parse_fdt_resources()
657 	rv = regulator_get_by_ofw_property(sc->dev, 0,  in rk_pcie_parse_fdt_resources()
659 	if (rv != 0 && rv != ENOENT) {  in rk_pcie_parse_fdt_resources()
663 	rv = regulator_get_by_ofw_property(sc->dev, 0,  in rk_pcie_parse_fdt_resources()
665 	if (rv != 0 && rv != ENOENT) {  in rk_pcie_parse_fdt_resources()
669 	rv = regulator_get_by_ofw_property(sc->dev, 0,  in rk_pcie_parse_fdt_resources()
671 	if (rv != 0 && rv != ENOENT) {  in rk_pcie_parse_fdt_resources()
677 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "core", &sc->hwreset_core);  in rk_pcie_parse_fdt_resources()
678 	if (rv != 0) {  in rk_pcie_parse_fdt_resources()
682 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "mgmt", &sc->hwreset_mgmt);  in rk_pcie_parse_fdt_resources()
683 	if (rv != 0) {  in rk_pcie_parse_fdt_resources()
687 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "mgmt-sticky",  in rk_pcie_parse_fdt_resources()
689 	if (rv != 0) {  in rk_pcie_parse_fdt_resources()
693 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "pipe", &sc->hwreset_pipe);  in rk_pcie_parse_fdt_resources()
694 	if (rv != 0) {  in rk_pcie_parse_fdt_resources()
698 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "pm", &sc->hwreset_pm);  in rk_pcie_parse_fdt_resources()
699 	if (rv != 0) {  in rk_pcie_parse_fdt_resources()
703 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "aclk", &sc->hwreset_aclk);  in rk_pcie_parse_fdt_resources()
704 	if (rv != 0) {  in rk_pcie_parse_fdt_resources()
708 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "pclk", &sc->hwreset_pclk);  in rk_pcie_parse_fdt_resources()
709 	if (rv != 0) {  in rk_pcie_parse_fdt_resources()
715 	rv = clk_get_by_ofw_name(sc->dev, 0, "aclk", &sc->clk_aclk);  in rk_pcie_parse_fdt_resources()
716 	if (rv != 0) {  in rk_pcie_parse_fdt_resources()
720 	rv = clk_get_by_ofw_name(sc->dev, 0, "aclk-perf", &sc->clk_aclk_perf);  in rk_pcie_parse_fdt_resources()
721 	if (rv != 0) {  in rk_pcie_parse_fdt_resources()
725 	rv = clk_get_by_ofw_name(sc->dev, 0, "hclk", &sc->clk_hclk);  in rk_pcie_parse_fdt_resources()
726 	if (rv != 0) {  in rk_pcie_parse_fdt_resources()
730 	rv = clk_get_by_ofw_name(sc->dev, 0, "pm", &sc->clk_pm);  in rk_pcie_parse_fdt_resources()
731 	if (rv != 0) {  in rk_pcie_parse_fdt_resources()
737 	for (i = 0; i < MAX_LANES; i++ ) {  in rk_pcie_parse_fdt_resources()
739 		rv = phy_get_by_ofw_name(sc->dev, 0, buf, sc->phys + i);  in rk_pcie_parse_fdt_resources()
740 		if (rv != 0) {  in rk_pcie_parse_fdt_resources()
749 	if (rv != 0 && rv != ENOENT) {  in rk_pcie_parse_fdt_resources()
754 	return (0);  in rk_pcie_parse_fdt_resources()
765 	if (rv != 0) {  in rk_pcie_enable_resources()
770 	if (rv != 0) {  in rk_pcie_enable_resources()
775 	if (rv != 0) {  in rk_pcie_enable_resources()
780 	if (rv != 0) {  in rk_pcie_enable_resources()
785 	if (rv != 0) {  in rk_pcie_enable_resources()
790 	if (rv != 0) {  in rk_pcie_enable_resources()
795 	if (rv != 0) {  in rk_pcie_enable_resources()
803 	if (rv != 0) {  in rk_pcie_enable_resources()
808 	if (rv != 0) {  in rk_pcie_enable_resources()
813 	if (rv != 0) {  in rk_pcie_enable_resources()
818 	if (rv != 0) {  in rk_pcie_enable_resources()
826 		if (rv != 0) {  in rk_pcie_enable_resources()
834 		if (rv != 0) {  in rk_pcie_enable_resources()
842 		if (rv != 0) {  in rk_pcie_enable_resources()
850 		if (rv != 0) {  in rk_pcie_enable_resources()
860 	if (rv != 0) {  in rk_pcie_enable_resources()
865 	if (rv != 0) {  in rk_pcie_enable_resources()
870 	if (rv != 0) {  in rk_pcie_enable_resources()
877 	    (sc->link_is_gen2 ? STRAP_CONF_GEN_2: 0);  in rk_pcie_enable_resources()
879 	val |= STRAP_CONF_LANES(~0) << 16 | STRAP_CONF_LANES(sc->num_lanes);  in rk_pcie_enable_resources()
884 	for (i = 0; i < MAX_LANES; i++) {  in rk_pcie_enable_resources()
886 		if (rv != 0) {  in rk_pcie_enable_resources()
894 	if (rv != 0) {  in rk_pcie_enable_resources()
899 	if (rv != 0) {  in rk_pcie_enable_resources()
904 	if (rv != 0) {  in rk_pcie_enable_resources()
909 	if (rv != 0) {  in rk_pcie_enable_resources()
913 	return (0);  in rk_pcie_enable_resources()
924 		rv = gpio_pin_set_active(sc->gpio_ep, 0);  in rk_pcie_setup_hw()
925 		if (rv != 0) {  in rk_pcie_setup_hw()
933 	if (rv != 0)  in rk_pcie_setup_hw()
938 	val |= 0xFFFF << 8;  in rk_pcie_setup_hw()
956 		if (rv != 0) {  in rk_pcie_setup_hw()
963 	for (i = 500; i > 0; i--) {  in rk_pcie_setup_hw()
969 	if (i <= 0) {  in rk_pcie_setup_hw()
971 		    "Gen1 link training timeouted: 0x%08X.\n", val);  in rk_pcie_setup_hw()
972 		return (0);  in rk_pcie_setup_hw()
981 			for (i = 500; i > 0; i--) {  in rk_pcie_setup_hw()
988 			if (i <= 0)  in rk_pcie_setup_hw()
990 				    "timeouted: 0x%08X.\n", val);  in rk_pcie_setup_hw()
998 	return (0);  in rk_pcie_setup_hw()
1010 	APB_WR4(sc, PCIE_CORE_CONFIG_VENDOR, 0x1D87); /* Rockchip vendor ID*/  in rk_pcie_setup_sw()
1041 	rk_pcie_map_in_atu(sc, 2, 64 - 1, 0);  in rk_pcie_setup_sw()
1044 	/* - region 0 (32 MB) is used for config access */  in rk_pcie_setup_sw()
1045 	region = 0;  in rk_pcie_setup_sw()
1046 	rk_pcie_map_out_atu(sc, region++, ATU_TYPE_CFG0, 25 - 1, 0);  in rk_pcie_setup_sw()
1049 	for (i = 0; i  < sc->mem_range.size / ATU_OB_REGION_SIZE; i++) {  in rk_pcie_setup_sw()
1056 	for (i = 0; i  < sc->io_range.size / ATU_OB_REGION_SIZE; i++) {  in rk_pcie_setup_sw()
1061 	APB_WR4(sc, PCIE_CORE_RC_BAR_CONF, 0);  in rk_pcie_setup_sw()
1062 	return (0);  in rk_pcie_setup_sw()
1078 		device_printf(sc->dev, "'sys' interrupt received: 0x%04X\n",  in rk_pcie_sys_irq()
1098 	device_printf(sc->dev, "'client' interrupt received: 0x%04X\n", irq);  in rk_pcie_client_irq()
1134 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in rk_pcie_probe()
1157 	sc->bus_start = 0;  in rk_pcie_attach()
1158 	sc->bus_end =  0x1F;  in rk_pcie_attach()
1164 	if (rv != 0)  in rk_pcie_attach()
1176 		sc->num_lanes = 0;  in rk_pcie_attach()
1189 	if (rv != 0) {  in rk_pcie_attach()
1206 	if (rv != 0) {  in rk_pcie_attach()
1214 	if (rv != 0) {  in rk_pcie_attach()
1230 	if (rv != 0) {  in rk_pcie_attach()
1245 	if (rv != 0) {  in rk_pcie_attach()
1260 	if (rv != 0) {  in rk_pcie_attach()
1277 	    1, 0,				/* alignment, bounds */  in rk_pcie_attach()
1284 	    sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */  in rk_pcie_attach()
1287 	if (rv != 0)  in rk_pcie_attach()
1291 	if (rv != 0)  in rk_pcie_attach()
1296 	if (rv != 0)  in rk_pcie_attach()
1299 	if (rv != 0)  in rk_pcie_attach()
1303 	if (rv != 0)  in rk_pcie_attach()
1308 	if (rv != 0) {  in rk_pcie_attach()
1316 	if (rv != 0) {  in rk_pcie_attach()
1324 	if (rv != 0) {  in rk_pcie_attach()
1358 	return (0);  in rk_pcie_attach()
1375 	for (int i = 0; i < MAX_LANES; i++) {  in rk_pcie_attach()