Lines Matching +full:clear +full:- +full:gpios
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
67 RK_GPIO_PORTA_EOI, /* Clear interrupt register */
117 {"rockchip,gpio-bank", 1},
124 { -1, 0 }
130 #define RK_GPIO_ISRC(sc, irq) (&(sc->isrcs[irq].isrc))
134 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
135 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
136 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
139 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
141 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
146 struct rk_gpio_reg *rk_reg = &sc->regs[reg]; in rk_gpio_read_bit()
149 if (rk_reg->single) { in rk_gpio_read_bit()
150 value = RK_GPIO_READ(sc, rk_reg->offset); in rk_gpio_read_bit()
154 rk_reg->offset + 4 : rk_reg->offset); in rk_gpio_read_bit()
163 struct rk_gpio_reg *rk_reg = &sc->regs[reg]; in rk_gpio_write_bit()
166 if (rk_reg->single) { in rk_gpio_write_bit()
167 value = RK_GPIO_READ(sc, rk_reg->offset); in rk_gpio_write_bit()
172 RK_GPIO_WRITE(sc, rk_reg->offset, value); in rk_gpio_write_bit()
180 rk_reg->offset + 4 : rk_reg->offset, value); in rk_gpio_write_bit()
187 struct rk_gpio_reg *rk_reg = &sc->regs[reg]; in rk_gpio_read_4()
190 if (rk_reg->single) in rk_gpio_read_4()
191 value = RK_GPIO_READ(sc, rk_reg->offset); in rk_gpio_read_4()
193 value = (RK_GPIO_READ(sc, rk_reg->offset) & 0xffff) | in rk_gpio_read_4()
194 (RK_GPIO_READ(sc, rk_reg->offset + 4) << 16); in rk_gpio_read_4()
201 struct rk_gpio_reg *rk_reg = &sc->regs[reg]; in rk_gpio_write_4()
203 if (rk_reg->single) in rk_gpio_write_4()
204 RK_GPIO_WRITE(sc, rk_reg->offset, value); in rk_gpio_write_4()
206 RK_GPIO_WRITE(sc, rk_reg->offset, in rk_gpio_write_4()
208 RK_GPIO_WRITE(sc, rk_reg->offset + 4, in rk_gpio_write_4()
217 struct trapframe *tf = curthread->td_intr_frame; in rk_gpio_intr()
226 int pin = ffs(status) - 1; in rk_gpio_intr()
230 device_printf(sc->sc_dev, "Interrupt pin=%d unhandled\n", in rk_gpio_intr()
235 if ((sc->version == RK_GPIO_TYPE_V1) && in rk_gpio_intr()
236 (sc->isrcs[pin].mode & GPIO_INTR_EDGE_BOTH)) { in rk_gpio_intr()
257 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in rk_gpio_probe()
272 sc->sc_dev = dev; in rk_gpio_attach()
273 sc->pinctrl = device_get_parent(dev); in rk_gpio_attach()
274 parent_node = ofw_bus_get_node(sc->pinctrl); in rk_gpio_attach()
276 node = ofw_bus_get_node(sc->sc_dev); in rk_gpio_attach()
277 if (!OF_hasprop(node, "gpio-controller")) in rk_gpio_attach()
280 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN); in rk_gpio_attach()
282 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) { in rk_gpio_attach()
284 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); in rk_gpio_attach()
285 mtx_destroy(&sc->sc_mtx); in rk_gpio_attach()
289 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); in rk_gpio_attach()
290 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); in rk_gpio_attach()
292 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) { in rk_gpio_attach()
297 err = clk_enable(sc->clk); in rk_gpio_attach()
300 clk_get_name(sc->clk)); in rk_gpio_attach()
305 if ((err = bus_setup_intr(dev, sc->sc_res[1], in rk_gpio_attach()
307 sc, &sc->ihandle))) { in rk_gpio_attach()
318 if (ofw_bus_node_is_compatible(parent_node, "rockchip,rk3568-pinctrl")) in rk_gpio_attach()
319 sc->version = RK_GPIO_TYPE_V2; in rk_gpio_attach()
321 sc->version = RK_GPIO_TYPE_V1; in rk_gpio_attach()
323 switch (sc->version) { in rk_gpio_attach()
325 sc->regs[RK_GPIO_SWPORTA_DR] = (struct rk_gpio_reg){ 1, 0x00 }; in rk_gpio_attach()
326 sc->regs[RK_GPIO_SWPORTA_DDR] = (struct rk_gpio_reg){ 1, 0x04 }; in rk_gpio_attach()
327 sc->regs[RK_GPIO_INTEN] = (struct rk_gpio_reg){ 1, 0x30 }; in rk_gpio_attach()
328 sc->regs[RK_GPIO_INTMASK] = (struct rk_gpio_reg){ 1, 0x34 }; in rk_gpio_attach()
329 sc->regs[RK_GPIO_INTTYPE_LEVEL] = (struct rk_gpio_reg){ 1, 0x38 }; in rk_gpio_attach()
330 sc->regs[RK_GPIO_INT_POLARITY] = (struct rk_gpio_reg){ 1, 0x3c }; in rk_gpio_attach()
331 sc->regs[RK_GPIO_INT_STATUS] = (struct rk_gpio_reg){ 1, 0x40 }; in rk_gpio_attach()
332 sc->regs[RK_GPIO_INT_RAWSTATUS] = (struct rk_gpio_reg){ 1, 0x44 }; in rk_gpio_attach()
333 sc->regs[RK_GPIO_DEBOUNCE] = (struct rk_gpio_reg){ 1, 0x48 }; in rk_gpio_attach()
334 sc->regs[RK_GPIO_PORTA_EOI] = (struct rk_gpio_reg){ 1, 0x4c }; in rk_gpio_attach()
335 sc->regs[RK_GPIO_EXT_PORTA] = (struct rk_gpio_reg){ 1, 0x50 }; in rk_gpio_attach()
338 sc->regs[RK_GPIO_SWPORTA_DR] = (struct rk_gpio_reg){ 0, 0x00 }; in rk_gpio_attach()
339 sc->regs[RK_GPIO_SWPORTA_DDR] = (struct rk_gpio_reg){ 0, 0x08 }; in rk_gpio_attach()
340 sc->regs[RK_GPIO_INTEN] = (struct rk_gpio_reg){ 0, 0x10 }; in rk_gpio_attach()
341 sc->regs[RK_GPIO_INTMASK] = (struct rk_gpio_reg){ 0, 0x18 }; in rk_gpio_attach()
342 sc->regs[RK_GPIO_INTTYPE_LEVEL] = (struct rk_gpio_reg){ 0, 0x20 }; in rk_gpio_attach()
343 sc->regs[RK_GPIO_INTTYPE_BOTH] = (struct rk_gpio_reg){ 0, 0x30 }; in rk_gpio_attach()
344 sc->regs[RK_GPIO_INT_POLARITY] = (struct rk_gpio_reg){ 0, 0x28 }; in rk_gpio_attach()
345 sc->regs[RK_GPIO_INT_STATUS] = (struct rk_gpio_reg){ 1, 0x50 }; in rk_gpio_attach()
346 sc->regs[RK_GPIO_INT_RAWSTATUS] = (struct rk_gpio_reg){ 1, 0x58 }; in rk_gpio_attach()
347 sc->regs[RK_GPIO_DEBOUNCE] = (struct rk_gpio_reg){ 0, 0x38 }; in rk_gpio_attach()
348 sc->regs[RK_GPIO_PORTA_EOI] = (struct rk_gpio_reg){ 0, 0x60 }; in rk_gpio_attach()
349 sc->regs[RK_GPIO_EXT_PORTA] = (struct rk_gpio_reg){ 1, 0x70 }; in rk_gpio_attach()
352 device_printf(dev, "Unknown gpio version %08x\n", sc->version); in rk_gpio_attach()
358 sc->isrcs[i].irq = i; in rk_gpio_attach()
359 sc->isrcs[i].mode = GPIO_INTR_CONFORM; in rk_gpio_attach()
376 sc->pin_cached[i].is_gpio = 2; in rk_gpio_attach()
379 sc->swporta = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR); in rk_gpio_attach()
380 sc->swporta_ddr = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR); in rk_gpio_attach()
383 sc->sc_busdev = gpiobus_add_bus(dev); in rk_gpio_attach()
384 if (sc->sc_busdev == NULL) { in rk_gpio_attach()
400 if (sc->sc_busdev) in rk_gpio_detach()
402 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); in rk_gpio_detach()
403 mtx_destroy(&sc->sc_mtx); in rk_gpio_detach()
404 clk_disable(sc->clk); in rk_gpio_detach()
416 return (sc->sc_busdev); in rk_gpio_get_bus()
441 pin = pin - (bank * 8); in rk_gpio_pin_getname()
457 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { in rk_gpio_pin_getflags()
458 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); in rk_gpio_pin_getflags()
461 if (sc->pin_cached[pin].is_gpio == 0) in rk_gpio_pin_getflags()
465 rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags); in rk_gpio_pin_getflags()
468 sc->pin_cached[pin].flags = *flags; in rk_gpio_pin_getflags()
470 if (sc->swporta_ddr & (1 << pin)) in rk_gpio_pin_getflags()
500 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { in rk_gpio_pin_setflags()
501 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); in rk_gpio_pin_setflags()
504 if (sc->pin_cached[pin].is_gpio == 0) in rk_gpio_pin_setflags()
508 …if (__predict_false((flags & GPIO_PIN_INPUT) && ((flags & GPIO_FLAGS_PINCTRL) != sc->pin_cached[pi… in rk_gpio_pin_setflags()
509 rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags); in rk_gpio_pin_setflags()
510 sc->pin_cached[pin].flags = flags & GPIO_FLAGS_PINCTRL; in rk_gpio_pin_setflags()
517 sc->swporta_ddr &= ~(1 << pin); in rk_gpio_pin_setflags()
519 sc->swporta_ddr |= (1 << pin); in rk_gpio_pin_setflags()
521 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, sc->swporta_ddr); in rk_gpio_pin_setflags()
556 sc->swporta |= (1 << pin); in rk_gpio_pin_set()
558 sc->swporta &= ~(1 << pin); in rk_gpio_pin_set()
559 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); in rk_gpio_pin_set()
576 if (sc->swporta & (1 << pin)) in rk_gpio_pin_toggle()
577 sc->swporta &= ~(1 << pin); in rk_gpio_pin_toggle()
579 sc->swporta |= (1 << pin); in rk_gpio_pin_toggle()
580 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); in rk_gpio_pin_toggle()
599 sc->swporta = reg; in rk_gpio_pin_access_32()
640 sc->swporta_ddr = reg; in rk_gpio_pin_config_32()
648 pcell_t *gpios, uint32_t *pin, uint32_t *flags) in rk_gpio_map_gpios() argument
651 /* The gpios are mapped as <pin flags> */ in rk_gpio_map_gpios()
652 *pin = gpios[0]; in rk_gpio_map_gpios()
653 *flags = gpios[1]; in rk_gpio_map_gpios()
673 if (daf->ncells != 2) in rk_gpio_pic_map_fdt()
676 irq = daf->cells[0]; in rk_gpio_pic_map_fdt()
681 if (daf->cells[1] == 1) in rk_gpio_pic_map_fdt()
683 else if (daf->cells[1] == 2) in rk_gpio_pic_map_fdt()
685 else if (daf->cells[1] == 3) in rk_gpio_pic_map_fdt()
687 else if (daf->cells[1] == 4) in rk_gpio_pic_map_fdt()
689 else if (daf->cells[1] == 8) in rk_gpio_pic_map_fdt()
706 irq = dag->gpio_pin_num; in rk_gpio_pic_map_gpio()
708 device_printf(sc->sc_dev, "Invalid interrupt %u\n", in rk_gpio_pic_map_gpio()
715 *modep = dag->gpio_intr_mode; in rk_gpio_pic_map_gpio()
723 switch (data->type) { in rk_gpio_pic_map()
731 device_printf(sc->sc_dev, "Wrong type\n"); in rk_gpio_pic_map()
767 if (rkisrc->irq != pin) { in rk_pic_setup_intr()
772 if (isrc->isrc_handlers != 0) { in rk_pic_setup_intr()
774 return (rkisrc->mode == mode ? 0 : EINVAL); in rk_pic_setup_intr()
776 rkisrc->mode = mode; in rk_pic_setup_intr()
794 if (sc->version == RK_GPIO_TYPE_V1) { in rk_pic_setup_intr()
837 if (isrc->isrc_handlers == 0) { in rk_pic_teardown_intr()
838 irqsrc->mode = GPIO_INTR_CONFORM; in rk_pic_teardown_intr()
840 rk_gpio_write_bit(sc, RK_GPIO_INTEN, irqsrc->irq, 0); in rk_pic_teardown_intr()
841 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, irqsrc->irq, 0); in rk_pic_teardown_intr()
842 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, irqsrc->irq, 0); in rk_pic_teardown_intr()