1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
49 #include <contrib/device-tree/include/dt-bindings/phy/phy.h>
57 	{"rockchip,rk3568-naneng-combphy",	1},
72 	int		mode;  member
174 	switch (sc->mode) {  in rk3568_combphy_enable()
179 		bus_write_4(sc->mem, PHYREG7,  in rk3568_combphy_enable()
183 		bus_write_4(sc->mem, PHYREG15,  in rk3568_combphy_enable()
184 		    bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN);  in rk3568_combphy_enable()
187 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3,  in rk3568_combphy_enable()
190 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2,  in rk3568_combphy_enable()
194 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0,  in rk3568_combphy_enable()
198 		SYSCON_WRITE_4(sc->pipe_grf, PIPE_GRF_PIPE_CON0,  in rk3568_combphy_enable()
207 		bus_write_4(sc->mem, PHYREG32,  in rk3568_combphy_enable()
208 		    (bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) |  in rk3568_combphy_enable()
212 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3,  in rk3568_combphy_enable()
215 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2,  in rk3568_combphy_enable()
217 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0,  in rk3568_combphy_enable()
226 		bus_write_4(sc->mem, PHYREG32,  in rk3568_combphy_enable()
227 		    (bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) |  in rk3568_combphy_enable()
231 		bus_write_4(sc->mem, PHYREG15,  in rk3568_combphy_enable()
232 		    bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN);  in rk3568_combphy_enable()
234 		/* Set PLL KVCO fine tuning signals */  in rk3568_combphy_enable()
235 		bus_write_4(sc->mem, PHYREG33,  in rk3568_combphy_enable()
236 		    (bus_read_4(sc->mem, PHYREG33) & PHYREG33_PLL_KVCO_MASK) |  in rk3568_combphy_enable()
240 		bus_write_4(sc->mem, PHYREG12, PHYREG12_PLL_LPF_ADJ_VALUE);  in rk3568_combphy_enable()
242 		/* Set PLL input clock divider 1/2 */  in rk3568_combphy_enable()
243 		bus_write_4(sc->mem, PHYREG6,  in rk3568_combphy_enable()
244 		    (bus_read_4(sc->mem, PHYREG6) & PHYREG6_PLL_DIV_MASK) |  in rk3568_combphy_enable()
247 		/* Set PLL loop divider */  in rk3568_combphy_enable()
248 		bus_write_4(sc->mem, PHYREG18, PHYREG18_PLL_LOOP);  in rk3568_combphy_enable()
250 		/* Set PLL LPF R1 to su_trim[0:7] */  in rk3568_combphy_enable()
251 		bus_write_4(sc->mem, PHYREG11, PHYREG11_SU_TRIM_0_7);  in rk3568_combphy_enable()
254 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3,  in rk3568_combphy_enable()
256 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2,  in rk3568_combphy_enable()
258 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0,  in rk3568_combphy_enable()
264 		printf("Unsupported mode=%d\n", sc->mode);  in rk3568_combphy_enable()
265 		return (-1);  in rk3568_combphy_enable()
268 	clk_get_freq(sc->ref_clk, &rate);  in rk3568_combphy_enable()
273 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1,  in rk3568_combphy_enable()
276 		if (sc->mode == PHY_TYPE_USB3 || sc->mode == PHY_TYPE_SATA) {  in rk3568_combphy_enable()
278 			bus_write_4(sc->mem, PHYREG15,  in rk3568_combphy_enable()
279 			    (bus_read_4(sc->mem, PHYREG15) &  in rk3568_combphy_enable()
283 			bus_write_4(sc->mem, PHYREG16, PHYREG16_SSC_CNT_VALUE);  in rk3568_combphy_enable()
288 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1,  in rk3568_combphy_enable()
293 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1,  in rk3568_combphy_enable()
296 		if (sc->mode == PHY_TYPE_PCIE) {  in rk3568_combphy_enable()
297 			/* Set PLL KVCO fine tuning signals */  in rk3568_combphy_enable()
298 			bus_write_4(sc->mem, PHYREG33,  in rk3568_combphy_enable()
299 			    (bus_read_4(sc->mem, PHYREG33) &  in rk3568_combphy_enable()
303 			bus_write_4(sc->mem, PHYREG12,  in rk3568_combphy_enable()
306 			/* Set PLL input clock divider 1/2 */  in rk3568_combphy_enable()
307 			bus_write_4(sc->mem, PHYREG6,  in rk3568_combphy_enable()
308 			    (bus_read_4(sc->mem, PHYREG6) &  in rk3568_combphy_enable()
311 			/* Set PLL loop divider */  in rk3568_combphy_enable()
312 			bus_write_4(sc->mem, PHYREG18, PHYREG18_PLL_LOOP);  in rk3568_combphy_enable()
314 			/* Set PLL LPF R1 to su_trim[0:7] */  in rk3568_combphy_enable()
315 			bus_write_4(sc->mem, PHYREG11, PHYREG11_SU_TRIM_0_7);  in rk3568_combphy_enable()
317 		if (sc->mode == PHY_TYPE_SATA) {  in rk3568_combphy_enable()
319 			bus_write_4(sc->mem, PHYREG32,  in rk3568_combphy_enable()
320 			    (bus_read_4(sc->mem, PHYREG32) & ~0x000000f0) |  in rk3568_combphy_enable()
330 	if (OF_hasprop(sc->node, "rockchip,ext-refclk")) {  in rk3568_combphy_enable()
331 		device_printf(dev, "UNSUPPORTED rockchip,ext-refclk\n");  in rk3568_combphy_enable()
333 	if (OF_hasprop(sc->node, "rockchip,enable-ssc")) {  in rk3568_combphy_enable()
334 		device_printf(dev, "setting rockchip,enable-ssc\n");  in rk3568_combphy_enable()
335 		bus_write_4(sc->mem, PHYREG8,  in rk3568_combphy_enable()
336 		    bus_read_4(sc->mem, PHYREG8) | PHYREG8_SSC_EN);  in rk3568_combphy_enable()
339 	if (hwreset_deassert(sc->phy_reset))  in rk3568_combphy_enable()
361 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in rk3568_combphy_probe()
375 	sc->dev = dev;  in rk3568_combphy_attach()
376 	sc->node = ofw_bus_get_node(dev);  in rk3568_combphy_attach()
379 	if (!(sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,  in rk3568_combphy_attach()
386 	if (OF_hasprop(sc->node, "rockchip,pipe-grf") &&  in rk3568_combphy_attach()
387 	    syscon_get_by_ofw_property(dev, sc->node, "rockchip,pipe-grf",  in rk3568_combphy_attach()
388 	    &sc->pipe_grf))  in rk3568_combphy_attach()
390 	if (OF_hasprop(sc->node, "rockchip,pipe-phy-grf") &&  in rk3568_combphy_attach()
391 	    syscon_get_by_ofw_property(dev, sc->node, "rockchip,pipe-phy-grf",  in rk3568_combphy_attach()
392 	    &sc->pipe_phy_grf))  in rk3568_combphy_attach()
396 	if (clk_get_by_ofw_name(dev, 0, "ref", &sc->ref_clk)) {  in rk3568_combphy_attach()
400 	if (clk_enable(sc->ref_clk))  in rk3568_combphy_attach()
402 	if (clk_get_by_ofw_name(dev, 0, "apb", &sc->apb_clk)) {  in rk3568_combphy_attach()
406 	if (clk_enable(sc->apb_clk))  in rk3568_combphy_attach()
408 	if (clk_get_by_ofw_name(dev, 0, "pipe", &sc->pipe_clk)) {  in rk3568_combphy_attach()
412 	if (clk_enable(sc->pipe_clk))  in rk3568_combphy_attach()
416 	if (hwreset_get_by_ofw_idx(dev, sc->node, 0, &sc->phy_reset)) {  in rk3568_combphy_attach()
420 	hwreset_assert(sc->phy_reset);  in rk3568_combphy_attach()
424 	phy_init.ofw_node = sc->node;  in rk3568_combphy_attach()
434 	sc->phynode = phynode;  in rk3568_combphy_attach()
435 	sc->mode = 0;  in rk3568_combphy_attach()
449 	/* Store the phy mode that is handed to us in id */  in rk3568_combphy_map()
450 	sc->mode = *id;  in rk3568_combphy_map()