52 #define	GRF_EMMCPHY_BASE	0xf780
53 #define	GRF_EMMCPHY_CON0	(GRF_EMMCPHY_BASE + 0x00)
55 #define	  PHYCTRL_FRQSEL_200M	0
64 #define	 PHYCTRL_ITAPDLYENA	(1 << 0)
65 #define	GRF_EMMCPHY_CON1	(GRF_EMMCPHY_BASE + 0x04)
69 #define	 PHYCTRL_STRBSEL	0xf
70 #define	GRF_EMMCPHY_CON2	(GRF_EMMCPHY_BASE + 0x08)
73 #define	 PHYCTRL_REN_DAT	0xff
74 #define	GRF_EMMCPHY_CON3	(GRF_EMMCPHY_BASE + 0x0c)
77 #define	 PHYCTRL_PU_DAT		0xff
78 #define	GRF_EMMCPHY_CON4	(GRF_EMMCPHY_BASE + 0x10)
81 #define	 PHYCTRL_OD_RELEASE_DAT		0xff
82 #define	GRF_EMMCPHY_CON5	(GRF_EMMCPHY_BASE + 0x14)
85 #define	 PHYCTRL_ODEN_DAT	0xff
86 #define	GRF_EMMCPHY_CON6	(GRF_EMMCPHY_BASE + 0x18)
94 #define	 PHYCTRL_PDB		(1 << 0)
95 #define	GRF_EMMCPHY_STATUS	(GRF_EMMCPHY_BASE + 0x20)
99 #define	 PHYCTRL_EXR_NINST	(1 << 0)
103 	{ NULL,				0 }
123     rk_emmcphy_phynode_methods, 0, phynode_class);
142 	if (phy != 0) {  in rk_emmcphy_enable()
149 		val = SHIFTIN(0, PHYCTRL_DR_TY);  in rk_emmcphy_enable()
162 	val = 0;  in rk_emmcphy_enable()
166 		return (0);  in rk_emmcphy_enable()
172 	error = clk_get_by_ofw_name(dev, 0, "emmcclk", &sc->clk);  in rk_emmcphy_enable()
173 	if (error != 0) {  in rk_emmcphy_enable()
181 		if (error != 0) {  in rk_emmcphy_enable()
186 		rate = 0;  in rk_emmcphy_enable()
188 	if (rate != 0) {  in rk_emmcphy_enable()
210 	if ((val & PHYCTRL_CALDONE) == 0) {  in rk_emmcphy_enable()
225 	if (rate != 0) {  in rk_emmcphy_enable()
246 		if ((val & PHYCTRL_DLLRDY) == 0) {  in rk_emmcphy_enable()
252 	return (0);  in rk_emmcphy_enable()
262 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in rk_emmcphy_probe()
284 	    sizeof(handle)) <= 0) {  in rk_emmcphy_attach()
291 	    "arasan,soc-ctl-syscon", &sc->syscon) != 0) {  in rk_emmcphy_attach()
303 	phy_init.id = 0;  in rk_emmcphy_attach()
318 	return (0);  in rk_emmcphy_attach()
335 EARLY_DRIVER_MODULE(rk_emmcphy, simplebus, rk_emmcphy_driver, 0, 0,