Lines Matching +full:tegra210 +full:- +full:xusb +full:- +full:padctl
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
50 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
56 #define FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(x, i) (((x) >> (11 + ((i) - 1) * 6)) & 0x3F);
324 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
325 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
352 {"nvidia,tegra210-xusb-padctl", 1},
385 .name = n "-" #p, \
401 /* Pads - a group of lannes. */
452 static char *usb_mux[] = {"snps", "xusb", "uart", "rsvd"};
453 static char *hsic_mux[] = {"snps", "xusb"};
454 static char *pci_mux[] = {"pcie-x1", "usb3-ss", "sata", "pcie-x4"};
474 .name = n "-" #p, \
512 LANE_MAP(0, PADCTL_PAD_PCIE, 6), /* port USB3-0 -> lane PCIE-0 */
513 LANE_MAP(1, PADCTL_PAD_PCIE, 5), /* port USB3-1 -> lane PCIE-1 */
514 LANE_MAP(2, PADCTL_PAD_PCIE, 0), /* port USB3-2 -> lane PCIE-0 */
515 LANE_MAP(2, PADCTL_PAD_PCIE, 2), /* port USB3-2 -> lane PCIE-2 */
516 LANE_MAP(3, PADCTL_PAD_PCIE, 4), /* port USB3-3 -> lane PCIE-4 */
538 /* -------------------------------------------------------------------------
548 if (sc->pcie_ena_cnt > 0) { in uphy_pex_enable()
549 sc->pcie_ena_cnt++; in uphy_pex_enable()
555 rv = clk_enable(pad->clk); in uphy_pex_enable()
557 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n", in uphy_pex_enable()
558 pad->name, rv); in uphy_pex_enable()
562 rv = hwreset_deassert(pad->reset); in uphy_pex_enable()
564 device_printf(sc->dev, "Cannot unreset pad '%s': %d\n", in uphy_pex_enable()
565 pad->name, rv); in uphy_pex_enable()
566 clk_disable(pad->clk); in uphy_pex_enable()
629 for (i = 30; i > 0; i--) { in uphy_pex_enable()
636 device_printf(sc->dev, "Timedout in calibration step 1 " in uphy_pex_enable()
637 "for pad '%s' (0x%08X).\n", pad->name, reg); in uphy_pex_enable()
645 for (i = 10; i > 0; i--) { in uphy_pex_enable()
652 device_printf(sc->dev, "Timedout in calibration step 2 " in uphy_pex_enable()
653 "for pad '%s'.\n", pad->name); in uphy_pex_enable()
662 for (i = 10; i > 0; i--) { in uphy_pex_enable()
669 device_printf(sc->dev, "Timedout while enabling PLL " in uphy_pex_enable()
670 "for pad '%s'.\n", pad->name); in uphy_pex_enable()
681 for (i = 10; i > 0; i--) { in uphy_pex_enable()
688 device_printf(sc->dev, "Timedout in RX calibration step 1 " in uphy_pex_enable()
689 "for pad '%s'.\n", pad->name); in uphy_pex_enable()
698 for (i = 10; i > 0; i--) { in uphy_pex_enable()
706 device_printf(sc->dev, "Timedout in RX calibration step 2 " in uphy_pex_enable()
707 "for pad '%s'.\n", pad->name); in uphy_pex_enable()
735 sc->pcie_ena_cnt++; in uphy_pex_enable()
740 hwreset_deassert(pad->reset); in uphy_pex_enable()
741 clk_disable(pad->clk); in uphy_pex_enable()
750 sc->pcie_ena_cnt--; in uphy_pex_disable()
751 if (sc->pcie_ena_cnt <= 0) { in uphy_pex_disable()
752 rv = hwreset_assert(pad->reset); in uphy_pex_disable()
754 device_printf(sc->dev, "Cannot reset pad '%s': %d\n", in uphy_pex_disable()
755 pad->name, rv); in uphy_pex_disable()
757 rv = clk_disable(pad->clk); in uphy_pex_disable()
759 device_printf(sc->dev, in uphy_pex_disable()
761 pad->name, rv); in uphy_pex_disable()
774 if (sc->sata_ena_cnt > 0) { in uphy_sata_enable()
775 sc->sata_ena_cnt++; in uphy_sata_enable()
779 rv = clk_enable(pad->clk); in uphy_sata_enable()
781 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n", in uphy_sata_enable()
782 pad->name, rv); in uphy_sata_enable()
786 rv = hwreset_deassert(pad->reset); in uphy_sata_enable()
788 device_printf(sc->dev, "Cannot unreset pad '%s': %d\n", in uphy_sata_enable()
789 pad->name, rv); in uphy_sata_enable()
790 clk_disable(pad->clk); in uphy_sata_enable()
864 for (i = 30; i > 0; i--) { in uphy_sata_enable()
871 device_printf(sc->dev, "Timedout in calibration step 1 " in uphy_sata_enable()
872 "for pad '%s'.\n", pad->name); in uphy_sata_enable()
880 for (i = 10; i > 0; i--) { in uphy_sata_enable()
887 device_printf(sc->dev, "Timedout in calibration step 2 " in uphy_sata_enable()
888 "for pad '%s'.\n", pad->name); in uphy_sata_enable()
897 for (i = 10; i > 0; i--) { in uphy_sata_enable()
904 device_printf(sc->dev, "Timedout while enabling PLL " in uphy_sata_enable()
905 "for pad '%s'.\n", pad->name); in uphy_sata_enable()
915 for (i = 10; i > 0; i--) { in uphy_sata_enable()
922 device_printf(sc->dev, "Timedout in RX calibration step 1 " in uphy_sata_enable()
923 "for pad '%s'.\n", pad->name); in uphy_sata_enable()
931 for (i = 10; i > 0; i--) { in uphy_sata_enable()
938 device_printf(sc->dev, "Timedout in RX calibration step 2 " in uphy_sata_enable()
939 "for pad '%s'.\n", pad->name); in uphy_sata_enable()
967 sc->sata_ena_cnt++; in uphy_sata_enable()
972 hwreset_deassert(pad->reset); in uphy_sata_enable()
973 clk_disable(pad->clk); in uphy_sata_enable()
982 sc->sata_ena_cnt--; in uphy_sata_disable()
983 if (sc->sata_ena_cnt <= 0) { in uphy_sata_disable()
984 rv = hwreset_assert(pad->reset); in uphy_sata_disable()
986 device_printf(sc->dev, "Cannot reset pad '%s': %d\n", in uphy_sata_disable()
987 pad->name, rv); in uphy_sata_disable()
989 rv = clk_disable(pad->clk); in uphy_sata_disable()
991 device_printf(sc->dev, in uphy_sata_disable()
993 pad->name, rv); in uphy_sata_disable()
1006 pad = port->lane->pad; in usb3_port_init()
1008 if (port->internal) in usb3_port_init()
1009 reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx); in usb3_port_init()
1011 reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx); in usb3_port_init()
1012 reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0); in usb3_port_init()
1013 reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion); in usb3_port_init()
1016 if (port->supply_vbus != NULL) { in usb3_port_init()
1017 rv = regulator_enable(port->supply_vbus); in usb3_port_init()
1019 device_printf(sc->dev, in usb3_port_init()
1025 reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx)); in usb3_port_init()
1028 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx), reg); in usb3_port_init()
1030 reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx)); in usb3_port_init()
1033 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx), reg); in usb3_port_init()
1035 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3(port->idx), 0xc0077f1f); in usb3_port_init()
1037 reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx)); in usb3_port_init()
1040 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx), reg); in usb3_port_init()
1042 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6(port->idx), 0xfcf01368); in usb3_port_init()
1044 if (pad->type == PADCTL_PAD_SATA) in usb3_port_init()
1052 reg &= ~ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(port->idx); in usb3_port_init()
1057 reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN_EARLY(port->idx); in usb3_port_init()
1062 reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN(port->idx); in usb3_port_init()
1075 rv = uphy_pex_enable(sc, lane->pad); in pcie_enable()
1080 reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); in pcie_enable()
1092 reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); in pcie_disable()
1095 uphy_pex_disable(sc, lane->pad); in pcie_disable()
1107 rv = uphy_sata_enable(sc, lane->pad, false); in sata_enable()
1112 reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx); in sata_enable()
1124 reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx); in sata_disable()
1127 uphy_sata_disable(sc, lane->pad); in sata_disable()
1142 device_printf(sc->dev, "Cannot find port for lane: %s\n", in hsic_enable()
1143 lane->name); in hsic_enable()
1145 pad = lane->pad; in hsic_enable()
1147 if (port->supply_vbus != NULL) { in hsic_enable()
1148 rv = regulator_enable(port->supply_vbus); in hsic_enable()
1150 device_printf(sc->dev, in hsic_enable()
1156 WR4(sc, XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL, sc->strobe_trim); in hsic_enable()
1158 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx)); in hsic_enable()
1160 reg |= HSIC_PAD_CTL1_TX_RTUNEP(sc->tx_rtune_p); in hsic_enable()
1161 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg); in hsic_enable()
1163 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx)); in hsic_enable()
1167 reg |= HSIC_PAD_CTL2_RX_STROBE_TRIM(sc->rx_strobe_trim); in hsic_enable()
1168 reg |= HSIC_PAD_CTL2_RX_DATA1_TRIM(sc->rx_data1_trim); in hsic_enable()
1169 reg |= HSIC_PAD_CTL2_RX_DATA0_TRIM(sc->rx_data0_trim); in hsic_enable()
1170 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx), reg); in hsic_enable()
1172 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx)); in hsic_enable()
1188 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx), reg); in hsic_enable()
1190 rv = clk_enable(pad->clk); in hsic_enable()
1192 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n", in hsic_enable()
1193 pad->name, rv); in hsic_enable()
1194 if (port->supply_vbus != NULL) in hsic_enable()
1195 regulator_disable(port->supply_vbus); in hsic_enable()
1213 clk_disable(pad->clk); in hsic_enable()
1226 device_printf(sc->dev, "Cannot find port for lane: %s\n", in hsic_disable()
1227 lane->name); in hsic_disable()
1230 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx)); in hsic_disable()
1240 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg); in hsic_disable()
1242 if (port->supply_vbus != NULL) { in hsic_disable()
1243 rv = regulator_disable(port->supply_vbus); in hsic_disable()
1245 device_printf(sc->dev, in hsic_disable()
1264 device_printf(sc->dev, "Cannot find port for lane: %s\n", in usb2_enable()
1265 lane->name); in usb2_enable()
1267 pad = lane->pad; in usb2_enable()
1276 reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0); in usb2_enable()
1277 reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST); in usb2_enable()
1280 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx)); in usb2_enable()
1287 reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level[lane->idx] + in usb2_enable()
1288 sc->hs_curr_level_offs); in usb2_enable()
1289 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg); in usb2_enable()
1291 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx)); in usb2_enable()
1297 reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj); in usb2_enable()
1298 reg |= USB2_OTG_PAD_CTL1_RPD_CTRL(sc->rpd_ctrl); in usb2_enable()
1299 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg); in usb2_enable()
1301 reg = RD4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx)); in usb2_enable()
1304 WR4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx), reg); in usb2_enable()
1306 if (port->supply_vbus != NULL) { in usb2_enable()
1307 rv = regulator_enable(port->supply_vbus); in usb2_enable()
1309 device_printf(sc->dev, in usb2_enable()
1314 rv = clk_enable(pad->clk); in usb2_enable()
1316 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n", in usb2_enable()
1317 pad->name, rv); in usb2_enable()
1318 if (port->supply_vbus != NULL) in usb2_enable()
1319 regulator_disable(port->supply_vbus); in usb2_enable()
1345 device_printf(sc->dev, "Cannot find port for lane: %s\n", in usb2_disable()
1346 lane->name); in usb2_disable()
1348 pad = lane->pad; in usb2_disable()
1354 if (port->supply_vbus != NULL) { in usb2_disable()
1355 rv = regulator_disable(port->supply_vbus); in usb2_disable()
1357 device_printf(sc->dev, in usb2_disable()
1363 rv = clk_disable(pad->clk); in usb2_disable()
1365 device_printf(sc->dev, "Cannot disable clock for pad '%s': %d\n", in usb2_disable()
1366 pad->name, rv); in usb2_disable()
1440 if (!lane->enabled) { in xusbpadctl_phy_enable()
1442 lane->name); in xusbpadctl_phy_enable()
1446 pad = lane->pad; in xusbpadctl_phy_enable()
1448 if (sc->phy_ena_cnt == 0) { in xusbpadctl_phy_enable()
1453 sc->phy_ena_cnt++; in xusbpadctl_phy_enable()
1457 rv = pad->enable(sc, lane); in xusbpadctl_phy_enable()
1459 rv = pad->disable(sc, lane); in xusbpadctl_phy_enable()
1464 if (sc->phy_ena_cnt == 1) { in xusbpadctl_phy_enable()
1469 sc->phy_ena_cnt--; in xusbpadctl_phy_enable()
1475 /* -------------------------------------------------------------------------
1525 if (type == lanes_tbl[i].pad->type && idx == lanes_tbl[i].idx) in search_pad_lane()
1545 if (strcmp(tmp->mux[tmp->mux_idx], "usb3-ss") != 0) in search_usb3_pad_lane()
1548 device_printf(sc->dev, "Duplicated mappings found for" in search_usb3_pad_lane()
1549 " lanes: %s and %s\n", lane->name, tmp->name); in search_usb3_pad_lane()
1574 for (i = 0; i < lane->nmux; i++) { in search_mux()
1575 if (strcmp(fnc_name, lane->mux[i]) == 0) in search_mux()
1578 return (-1); in search_mux()
1586 reg = RD4(sc, lane->reg); in config_lane()
1587 reg &= ~(lane->mask << lane->shift); in config_lane()
1588 reg |= (lane->mux_idx & lane->mask) << lane->shift; in config_lane()
1589 WR4(sc, lane->reg, reg); in config_lane()
1607 device_printf(sc->dev, "Cannot read lane name.\n"); in process_lane()
1613 device_printf(sc->dev, "Unknown lane: %s\n", name); in process_lane()
1621 device_printf(sc->dev, "Cannot read lane function.\n"); in process_lane()
1626 lane->mux_idx = search_mux(sc, lane, function); in process_lane()
1627 if (lane->mux_idx == ~0) { in process_lane()
1628 device_printf(sc->dev, "Unknown function %s for lane %s\n", in process_lane()
1636 device_printf(sc->dev, "Cannot configure lane: %s: %d\n", in process_lane()
1641 lane->xref = OF_xref_from_node(node); in process_lane()
1642 lane->pad = pad; in process_lane()
1643 lane->enabled = true; in process_lane()
1644 pad->lanes[pad->nlanes++] = lane; in process_lane()
1648 phy_init.id = lane - lanes_tbl; in process_lane()
1650 phynode = phynode_create(sc->dev, &xusbpadctl_phynode_class, &phy_init); in process_lane()
1652 device_printf(sc->dev, "Cannot create phy\n"); in process_lane()
1657 device_printf(sc->dev, "Cannot create phy\n"); in process_lane()
1682 device_printf(sc->dev, "Cannot read pad name.\n"); in process_pad()
1688 device_printf(sc->dev, "Unknown pad: %s\n", name); in process_pad()
1693 if (pad->clock_name != NULL) { in process_pad()
1694 rv = clk_get_by_ofw_name(sc->dev, node, pad->clock_name, in process_pad()
1695 &pad->clk); in process_pad()
1697 device_printf(sc->dev, "Cannot get '%s' clock\n", in process_pad()
1698 pad->clock_name); in process_pad()
1703 if (pad->reset_name != NULL) { in process_pad()
1704 rv = hwreset_get_by_ofw_name(sc->dev, node, pad->reset_name, in process_pad()
1705 &pad->reset); in process_pad()
1707 device_printf(sc->dev, "Cannot get '%s' reset\n", in process_pad()
1708 pad->reset_name); in process_pad()
1716 device_printf(sc->dev, "Cannot find 'lanes' subnode\n"); in process_pad()
1730 OF_device_register_xref(xref, sc->dev); in process_pad()
1732 pad->enabled = true; in process_pad()
1751 device_printf(sc->dev, "Cannot read port name.\n"); in process_port()
1757 device_printf(sc->dev, "Unknown port: %s\n", name); in process_port()
1762 regulator_get_by_ofw_property(sc->dev, node, in process_port()
1763 "vbus-supply", &port->supply_vbus); in process_port()
1766 port->internal = true; in process_port()
1769 if (port->lane == NULL) { in process_port()
1770 switch(port->type) { in process_port()
1773 port->lane = search_pad_lane(sc, PADCTL_PAD_USB2, in process_port()
1774 port->idx); in process_port()
1777 port->lane = search_pad_lane(sc, PADCTL_PAD_HSIC, in process_port()
1778 port->idx); in process_port()
1781 port->lane = search_usb3_pad_lane(sc, port->idx); in process_port()
1785 if (port->lane == NULL) { in process_port()
1786 device_printf(sc->dev, "Cannot find lane for port: %s\n", name); in process_port()
1791 if (port->type == PADCTL_PORT_USB3) { in process_port()
1792 rv = OF_getencprop(node, "nvidia,usb2-companion", in process_port()
1793 &(port->companion), sizeof(port->companion)); in process_port()
1795 device_printf(sc->dev, in process_port()
1796 "Missing 'nvidia,usb2-companion' property " in process_port()
1803 port->enabled = true; in process_port()
1821 device_printf(sc->dev, "Cannot find pads subnode.\n"); in parse_fdt()
1834 device_printf(sc->dev, "Cannot find ports subnode.\n"); in parse_fdt()
1855 sc->hs_curr_level[0] = FUSE_SKU_CALIB_0_HS_CURR_LEVEL_0(reg); in load_calibration()
1856 for (i = 1; i < nitems(sc->hs_curr_level); i++) { in load_calibration()
1857 sc->hs_curr_level[i] = in load_calibration()
1860 sc->hs_term_range_adj = FUSE_SKU_CALIB_0_HS_TERM_RANGE_ADJ(reg); in load_calibration()
1863 sc->rpd_ctrl = FUSE_USB_CALIB_EXT_0_RPD_CTRL(reg); in load_calibration()
1866 /* -------------------------------------------------------------------------
1877 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) in xusbpadctl_probe()
1880 device_set_desc(dev, "Tegra XUSB phy"); in xusbpadctl_probe()
1901 sc->dev = dev; in xusbpadctl_attach()
1904 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in xusbpadctl_attach()
1906 if (sc->mem_res == NULL) { in xusbpadctl_attach()
1911 rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst); in xusbpadctl_attach()
1913 device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv); in xusbpadctl_attach()
1916 rv = hwreset_deassert(sc->rst); in xusbpadctl_attach()
1918 device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv); in xusbpadctl_attach()
1931 if (!port->enabled) in xusbpadctl_attach()
1933 if (port->init == NULL) in xusbpadctl_attach()
1935 rv = port->init(sc, port); in xusbpadctl_attach()
1938 port->name); in xusbpadctl_attach()