119 /* Bits definition of M, N and P fields. */
391 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
682 get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p)  in get_divisors()  argument
689 	*m = get_masked(val, mnp_bits->m_shift, mnp_bits->m_width);  in get_divisors()
695 set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n,  in set_divisors()  argument
701 	val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width);  in set_divisors()
900     uint32_t m, uint32_t n, uint32_t p)  in pll_set_std()  argument
907 	if (m >= (1 << mnp_bits->m_width))  in pll_set_std()
916 		    (*fout != (((fin / m) * n) /p)))  in pll_set_std()
919 		*fout = ((fin / m) * n) /p;  in pll_set_std()
931 	reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width);  in pll_set_std()
958 	*fout = ((fin / m) * n) / p;  in pll_set_std()
965 	uint32_t m, n, p;  in plla_set_freq()  local
968 	m = 3;  in plla_set_freq()
969 	n = (*fout * p * m + fin / 2)/ fin;  in plla_set_freq()
970 	dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);  in plla_set_freq()
971 	return (pll_set_std(sc,  fin, fout, flags, m, n, p));  in plla_set_freq()
977 	uint32_t m, n, p;  in pllc_set_freq()  local
980 	m = 3;  in pllc_set_freq()
981 	n = (*fout * p * m + fin / 2)/ fin;  in pllc_set_freq()
982 	dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);  in pllc_set_freq()
983 	return (pll_set_std( sc, fin, fout, flags, m, n, p));  in pllc_set_freq()
989 	uint32_t m, n, p;  in pllc4_set_freq()  local
992 	m = 4;  in pllc4_set_freq()
993 	n = (*fout * p * m + fin / 2)/ fin;  in pllc4_set_freq()
994 	dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);  in pllc4_set_freq()
995 	return (pll_set_std( sc, fin, fout, flags, m, n, p));  in pllc4_set_freq()
1001 	uint32_t m, n, p;  in plldp_set_freq()  local
1004 	m = 4;  in plldp_set_freq()
1005 	n = (*fout * p * m + fin / 2)/ fin;  in plldp_set_freq()
1006 	dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);  in plldp_set_freq()
1007 	return (pll_set_std( sc, fin, fout, flags, m, n, p));  in plldp_set_freq()
1028 	uint32_t m, n, p;  in plld2_set_freq()  local
1050 		for (m = 1; m < (1 << mnp_bits->m_width); m++) {  in plld2_set_freq()
1051 			n = (*fout * p * m + fin / 2) / fin;  in plld2_set_freq()
1058 			vco = (fin * n) / m;  in plld2_set_freq()
1061 			pfd = fin / m;  in plld2_set_freq()
1072 				best_m = m;  in plld2_set_freq()
1097 	uint32_t m, n, p;  in pllrefe_set_freq()  local
1099 	m = 1;  in pllrefe_set_freq()
1101 	n = *fout * p * m / fin;  in pllrefe_set_freq()
1102 	dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);  in pllrefe_set_freq()
1103 	return (pll_set_std(sc, fin, fout, flags, m, n, p));  in pllrefe_set_freq()
1115 	uint32_t m, n, p;  in pllx_set_freq()  local
1126 	m = old_m;  in pllx_set_freq()
1133 	n = (*fout * p * m + fin / 2) / fin;  in pllx_set_freq()
1134 	dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);  in pllx_set_freq()
1136 	if (m >= (1 << mnp_bits->m_width))  in pllx_set_freq()
1145 		    (*fout != (((fin / m) * n) /p)))  in pllx_set_freq()
1147 		*fout = ((fin / m) * n) /p;  in pllx_set_freq()
1214 	*fout = ((fin / m) * n) / p;  in pllx_set_freq()
1287 		if (*fout == 480000000)  /* PLLU is fixed to 480 MHz */  in tegra210_pll_set_freq()
1335 	uint32_t m, n, p, pr;  in tegra210_pll_recalc()  local
1344 	get_divisors(sc, &m, &n, &pr);  in tegra210_pll_recalc()
1354 	dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): "  in tegra210_pll_recalc()
1356 	    clknode_get_name(clk), reg, misc_reg, m, n, p, pr,  in tegra210_pll_recalc()
1360 	if ((m == 0) || (n == 0) || (p == 0)) {  in tegra210_pll_recalc()
1368 	*freq = ((*freq / m) * n) / p;  in tegra210_pll_recalc()