1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
39 #include <dt-bindings/clock/tegra210-car.h>
40 #include <dt-bindings/reset/tegra210-car.h>
308 	/* bank L ->  0-31 */
332 	/* bank H -> 32-63 */
353 	/* bank U  -> 64-95 */
378 	/* bank V  -> 96-127 */
398 	/* bank W   -> 128-159*/
425 	/* bank X -> 160-191*/
442 	GATE(DPAUX, "dpaux", "dpaux_div", X(21)),
452 	/* bank Y -> 192-224*/
666 	if (sc->flags & DCF_HAVE_ENA)  in periph_init()
667 		MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK);  in periph_init()
669 	RD4(sc, sc->base_reg, &reg);  in periph_init()
673 	if (sc->flags & DCF_HAVE_MUX)  in periph_init()
674 		sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK;  in periph_init()
676 		sc->mux = 0;  in periph_init()
677 	if (sc->flags & DCF_HAVE_DIV)  in periph_init()
678 		sc->divider = (reg & sc->div_mask) + 2;  in periph_init()
680 		sc->divider = 1;  in periph_init()
681 	if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) {  in periph_init()
683 			sc->divider = 2;  in periph_init()
687 	if ((sc->flags & DCF_IS_MASK) == DCF_IS_AHUB) {  in periph_init()
688 		if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) {  in periph_init()
689 			sc->mux = 8 +  in periph_init()
693 	clknode_init_parent_idx(clk, sc->mux);  in periph_init()
705 	if (!(sc->flags & DCF_HAVE_MUX))  in periph_set_mux()
708 	sc->mux = idx;  in periph_set_mux()
710 	RD4(sc, sc->base_reg, &reg);  in periph_set_mux()
712 	if ((sc->flags & DCF_IS_MASK) == DCF_IS_AHUB) {  in periph_set_mux()
720 			reg |= (idx - 8) << PERLCK_AMUX_SHIFT;  in periph_set_mux()
725 	WR4(sc, sc->base_reg, reg);  in periph_set_mux()
739 	if (sc->flags & DCF_HAVE_DIV) {  in periph_recalc()
741 		RD4(sc, sc->base_reg, &reg);  in periph_recalc()
743 		*freq = (*freq << sc->div_f_width) / sc->divider;  in periph_recalc()
756 	if (!(sc->flags & DCF_HAVE_DIV)) {  in periph_set_freq()
761 	tmp = fin << sc->div_f_width;  in periph_set_freq()
766 	if (divider < (1 << sc->div_f_width))  in periph_set_freq()
767 		 divider = 1 << (sc->div_f_width - 1);  in periph_set_freq()
775 		MD4(sc, sc->base_reg, sc->div_mask,  in periph_set_freq()
776 		    (divider - (1 << sc->div_f_width)));  in periph_set_freq()
778 		sc->divider = divider;  in periph_set_freq()
791 	clk = clknode_create(clkdom, &tegra210_periph_class, &clkdef->clkdef);  in periph_register()
796 	sc->clkdev = clknode_get_device(clk);  in periph_register()
797 	sc->base_reg = clkdef->base_reg;  in periph_register()
798 	sc->div_width = clkdef->div_width;  in periph_register()
799 	sc->div_mask = (1 <<clkdef->div_width) - 1;  in periph_register()
800 	sc->div_f_width = clkdef->div_f_width;  in periph_register()
801 	sc->div_f_mask = (1 <<clkdef->div_f_width) - 1;  in periph_register()
802 	sc->flags = clkdef->flags;  in periph_register()
808 /* -------------------------------------------------------------------------- */
854 	mask = 1 << (sc->idx % 32);  in pgate_init()
857 	RD4(sc, get_enable_reg(sc->idx), &ena_reg);  in pgate_init()
858 	RD4(sc, get_reset_reg(sc->idx), &rst_reg);  in pgate_init()
861 	sc->enabled = ena_reg & mask ? 1 : 0;  in pgate_init()
874 	mask = 1 << (sc->idx % 32);  in pgate_set_gate()
875 	sc->enabled = enable;  in pgate_set_gate()
876 	base_reg = get_enable_reg(sc->idx);  in pgate_set_gate()
894 	mask = 1 << (sc->idx % 32);  in pgate_get_gate()
895 	base_reg = get_enable_reg(sc->idx);  in pgate_get_gate()
910 	CLKDEV_DEVICE_LOCK(sc->dev);  in tegra210_hwreset_by_idx()
912 		CLKDEV_MODIFY_4(sc->dev, DFLL_BASE, DFLL_BASE_DVFS_DFLL_RESET,  in tegra210_hwreset_by_idx()
914 		CLKDEV_READ_4(sc->dev, DFLL_BASE, &reg);  in tegra210_hwreset_by_idx()
919 		CLKDEV_WRITE_4(sc->dev, reset_reg, mask);  in tegra210_hwreset_by_idx()
920 		CLKDEV_READ_4(sc->dev, reset_reg, &reg);  in tegra210_hwreset_by_idx()
925 		CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0);  in tegra210_hwreset_by_idx()
926 		CLKDEV_READ_4(sc->dev, reset_reg, &reg);  in tegra210_hwreset_by_idx()
928 	CLKDEV_DEVICE_UNLOCK(sc->dev);  in tegra210_hwreset_by_idx()
939 	clk = clknode_create(clkdom, &tegra210_pgate_class, &clkdef->clkdef);  in pgate_register()
944 	sc->clkdev = clknode_get_device(clk);  in pgate_register()
945 	sc->idx = clkdef->idx;  in pgate_register()
946 	sc->flags = clkdef->flags;  in pgate_register()
958 		rv = periph_register(sc->clkdom, &periph_def[i]);  in tegra210_periph_clock()
963 		rv = pgate_register(sc->clkdom, &pgate_def[i]);  in tegra210_periph_clock()