Lines Matching +full:29 +full:v
50 #define PERLCK_MUX_SHIFT 29
260 #define V(n) ((3 * 32) + (n)) macro
273 #define TEGRA210_CLK_DEVD2_OUT U(29)
275 #define TEGRA210_CLK_CPUG V(0)
276 #define TEGRA210_CLK_ATOMICS V(16)
287 #define TEGRA210_CLK_EMC_LATENCY W(29)
301 #define TEGRA210_CLK_PLLG_REF X(29)
374 GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)),
378 /* bank V -> 96-127 */
379 GATE(CPUG, "cpug", "clk_m", V(0)),
380 GATE(MSELECT, "mselect", "pc_mselect", V(3)),
381 GATE(TSENSOR, "tsensor", "pc_tsensor", V(4)),
382 GATE(I2S4, "i2s5", "pc_i2s5", V(5)),
383 GATE(I2S3, "i2s4", "pc_i2s4", V(6)),
384 GATE(I2C4, "i2c4", "pc_i2c4", V(7)),
385 GATE(D_AUDIO, "ahub", "pc_ahub", V(10)),
386 GATE(APB2APE, "apb2ape", "clk_m", V(11)),
387 GATE(HDA2CODEC_2X, "hda2codec_2x", "pc_hda2codec_2x", V(15)),
388 GATE(ATOMICS, "atomics", "clk_m", V(16)),
389 GATE(SPDIF_2X, "spdif_doubler", "clk_m", V(22)),
390 GATE(ACTMON, "actmon", "pc_actmon", V(23)),
391 GATE(EXTERN1, "extperiph1", "pc_extperiph1", V(24)),
392 GATE(EXTERN2, "extperiph2", "pc_extperiph2", V(25)),
393 GATE(EXTERN3, "extperiph3", "pc_extperiph3", V(26)),
394 GATE(SATA_OOB, "sata_oob", "pc_sata_oob", V(27)),
395 GATE(SATA, "sata", "pc_sata", V(28)),
396 GATE(HDA, "hda", "pc_hda", V(29)),
422 GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", W(29)),
450 GATE(PLLG_REF, "pllg_ref", "clk_m", X(29)),
474 GATE(IQC1, "iqc1", "clk_m", Y(29)),